From: Boris Brezillon <boris.brezillon@bootlin.com>
To: Chris Packham <Chris.Packham@alliedtelesis.co.nz>
Cc: "linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
"stable@vger.kernel.org" <stable@vger.kernel.org>,
Daniel Mack <daniel@zonque.org>,
Miquel Raynal <miquel.raynal@bootlin.com>
Subject: Re: [PATCH v2] mtd: rawnand: marvell: check for RDY bits after enabling the IRQ
Date: Fri, 28 Sep 2018 08:56:56 +0200 [thread overview]
Message-ID: <20180928085656.6b0be35a@bbrezillon> (raw)
In-Reply-To: <20180928084046.221bdda0@bbrezillon>
On Fri, 28 Sep 2018 08:40:46 +0200
Boris Brezillon <boris.brezillon@bootlin.com> wrote:
> > marvell-nfc f10d0000.nand-controller: Timeout on RDDREQ while draining
> > FIFO (data) (NDSR: 0x00000810)
> > ttyS ttyS1: tty_port_close_start: tty->count = 1 port count = 2
> > marvell-nfc f10d0000.nand-controller: Timeout on RDDREQ while draining
> > FIFO (data) (NDSR: 0x00000810)
> > marvell-nfc f10d0000.nand-controller: Timeout on RDDREQ while draining
> > FIFO (data) (NDSR: 0x00000810)
> > marvell-nfc f10d0000.nand-controller: Timeout on RDDREQ while draining
> > FIFO (data) (NDSR: 0x00000810)
> > marvell-nfc f10d0000.nand-controller: Timeout on RDDREQ while draining
> > FIFO (data) (NDSR: 0x00000810)
> > marvell-nfc f10d0000.nand-controller: Timeout on RDDREQ while draining
> > FIFO (data) (NDSR: 0x00000810)
> > marvell-nfc f10d0000.nand-controller: Timeout on RDDREQ while draining
> > FIFO (data) (NDSR: 0x00000810)
> >
> > ... (RDDREQ messages repeat).
>
> Hm, that's weird, unless RDDREQ is a 'clear-on-read' bit, that
> shouldn't happen.
BTW, I dropped the patch.
next prev parent reply other threads:[~2018-09-28 6:57 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-27 7:17 [PATCH v2] mtd: rawnand: marvell: check for RDY bits after enabling the IRQ Daniel Mack
2018-09-27 8:11 ` Miquel Raynal
2018-09-27 8:56 ` Boris Brezillon
2018-09-27 21:55 ` Chris Packham
2018-09-28 6:40 ` Boris Brezillon
2018-09-28 6:56 ` Boris Brezillon [this message]
2018-09-28 8:12 ` Miquel Raynal
2018-09-28 7:43 ` Daniel Mack
2018-09-28 8:24 ` Miquel Raynal
2018-09-28 8:29 ` Daniel Mack
2018-09-30 21:10 ` Chris Packham
2018-10-01 5:31 ` Daniel Mack
2018-10-01 19:59 ` Chris Packham
2018-10-01 20:34 ` Boris Brezillon
2018-10-01 21:41 ` Boris Brezillon
2018-10-01 22:01 ` Chris Packham
2018-10-01 22:13 ` Boris Brezillon
2018-10-01 22:15 ` Chris Packham
2018-10-02 9:36 ` Boris Brezillon
2018-10-02 9:37 ` Boris Brezillon
2018-10-02 6:46 ` Miquel Raynal
2018-10-02 7:25 ` Miquel Raynal
2018-10-02 8:22 ` Daniel Mack
2018-10-02 20:53 ` Chris Packham
2018-10-03 7:33 ` Miquel Raynal
2018-10-03 7:54 ` Daniel Mack
2018-10-01 22:44 ` Boris Brezillon
2018-10-02 7:42 ` Daniel Mack
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