From: Boris Brezillon <boris.brezillon@bootlin.com>
To: Chris Packham <Chris.Packham@alliedtelesis.co.nz>
Cc: Daniel Mack <daniel@zonque.org>,
Miquel Raynal <miquel.raynal@bootlin.com>,
"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
"stable@vger.kernel.org" <stable@vger.kernel.org>
Subject: Re: [PATCH v2] mtd: rawnand: marvell: check for RDY bits after enabling the IRQ
Date: Mon, 1 Oct 2018 23:41:20 +0200 [thread overview]
Message-ID: <20181001234120.425ae1f5@bbrezillon> (raw)
In-Reply-To: <20181001223438.08a9d8c0@bbrezillon>
On Mon, 1 Oct 2018 22:34:38 +0200
Boris Brezillon <boris.brezillon@bootlin.com> wrote:
> >
> > I'd previously tried readl() based on the same hunch. No change.
> >
> > I think my snippet above might be misleading. While a delay between
> > readl_relaxed() and the if should not change the outcome, this is also a
> > delay between marvell_nfc_enable_int() and marvell_nfc_disable_int()
> > which is probably more significant. Sure enough if I move the delay to
> > just before the marvell_nfc_disable_int() the error is not seen.
>
> AFAICT, your timeout always happens when waiting for RDREQ, not RDYM.
> So maybe disabling MRDY too early has a side-effect on the RDREQ event.
Can you try with this patch [1]? It should ensure that NDSR_RDY bits
are cleared before starting an operation.
[1]http://code.bulix.org/lgs30c-468205
next prev parent reply other threads:[~2018-10-01 21:41 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-27 7:17 [PATCH v2] mtd: rawnand: marvell: check for RDY bits after enabling the IRQ Daniel Mack
2018-09-27 8:11 ` Miquel Raynal
2018-09-27 8:56 ` Boris Brezillon
2018-09-27 21:55 ` Chris Packham
2018-09-28 6:40 ` Boris Brezillon
2018-09-28 6:56 ` Boris Brezillon
2018-09-28 8:12 ` Miquel Raynal
2018-09-28 7:43 ` Daniel Mack
2018-09-28 8:24 ` Miquel Raynal
2018-09-28 8:29 ` Daniel Mack
2018-09-30 21:10 ` Chris Packham
2018-10-01 5:31 ` Daniel Mack
2018-10-01 19:59 ` Chris Packham
2018-10-01 20:34 ` Boris Brezillon
2018-10-01 21:41 ` Boris Brezillon [this message]
2018-10-01 22:01 ` Chris Packham
2018-10-01 22:13 ` Boris Brezillon
2018-10-01 22:15 ` Chris Packham
2018-10-02 9:36 ` Boris Brezillon
2018-10-02 9:37 ` Boris Brezillon
2018-10-02 6:46 ` Miquel Raynal
2018-10-02 7:25 ` Miquel Raynal
2018-10-02 8:22 ` Daniel Mack
2018-10-02 20:53 ` Chris Packham
2018-10-03 7:33 ` Miquel Raynal
2018-10-03 7:54 ` Daniel Mack
2018-10-01 22:44 ` Boris Brezillon
2018-10-02 7:42 ` Daniel Mack
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