* [PATCH 1/2] drm/i915: Fix VIDEO_DIP_CTL bit shifts
@ 2018-10-05 18:56 Dhinakaran Pandiyan
2018-10-05 18:56 ` [PATCH 2/2] drm/i915: Move VIDEO_DIP_CTL definitions to their right place Dhinakaran Pandiyan
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Dhinakaran Pandiyan @ 2018-10-05 18:56 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, Rodrigo Vivi
The shifts for VSC_SELECT bits are wrong, fix it. Good thing is the
definitions are unused.
v2: Moves definitions in another patch (Manasi)
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Fixes: 7af2be6d54d4 ("drm/i915/icl: Add VIDEO_DIP registers")
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a71c507cfb9b..61148b9a4a8e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4593,12 +4593,12 @@ enum {
#define DRM_DIP_ENABLE (1 << 28)
#define PSR_VSC_BIT_7_SET (1 << 27)
-#define VSC_SELECT_MASK (0x3 << 26)
-#define VSC_SELECT_SHIFT 26
-#define VSC_DIP_HW_HEA_DATA (0 << 26)
-#define VSC_DIP_HW_HEA_SW_DATA (1 << 26)
-#define VSC_DIP_HW_DATA_SW_HEA (2 << 26)
-#define VSC_DIP_SW_HEA_DATA (3 << 26)
+#define VSC_SELECT_MASK (0x3 << 25)
+#define VSC_SELECT_SHIFT 25
+#define VSC_DIP_HW_HEA_DATA (0 << 25)
+#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
+#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
+#define VSC_DIP_SW_HEA_DATA (3 << 25)
#define VDIP_ENABLE_PPS (1 << 24)
/* Panel power sequencing */
--
2.17.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/2] drm/i915: Move VIDEO_DIP_CTL definitions to their right place.
2018-10-05 18:56 [PATCH 1/2] drm/i915: Fix VIDEO_DIP_CTL bit shifts Dhinakaran Pandiyan
@ 2018-10-05 18:56 ` Dhinakaran Pandiyan
2018-10-05 19:03 ` Manasi Navare
2018-10-05 19:44 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Fix VIDEO_DIP_CTL bit shifts Patchwork
2018-10-06 2:00 ` ✓ Fi.CI.IGT: " Patchwork
2 siblings, 1 reply; 6+ messages in thread
From: Dhinakaran Pandiyan @ 2018-10-05 18:56 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
The bits weren't defined in descending order.
v2: Move definitions in a separate patch (Manasi)
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 19 +++++++++----------
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 61148b9a4a8e..a98b95922818 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4584,6 +4584,15 @@ enum {
#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
#define VIDEO_DIP_FREQ_MASK (3 << 16)
/* HSW and later: */
+#define DRM_DIP_ENABLE (1 << 28)
+#define PSR_VSC_BIT_7_SET (1 << 27)
+#define VSC_SELECT_MASK (0x3 << 25)
+#define VSC_SELECT_SHIFT 25
+#define VSC_DIP_HW_HEA_DATA (0 << 25)
+#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
+#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
+#define VSC_DIP_SW_HEA_DATA (3 << 25)
+#define VDIP_ENABLE_PPS (1 << 24)
#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
@@ -4591,16 +4600,6 @@ enum {
#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
-#define DRM_DIP_ENABLE (1 << 28)
-#define PSR_VSC_BIT_7_SET (1 << 27)
-#define VSC_SELECT_MASK (0x3 << 25)
-#define VSC_SELECT_SHIFT 25
-#define VSC_DIP_HW_HEA_DATA (0 << 25)
-#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
-#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
-#define VSC_DIP_SW_HEA_DATA (3 << 25)
-#define VDIP_ENABLE_PPS (1 << 24)
-
/* Panel power sequencing */
#define PPS_BASE 0x61200
#define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 2/2] drm/i915: Move VIDEO_DIP_CTL definitions to their right place.
2018-10-05 18:56 ` [PATCH 2/2] drm/i915: Move VIDEO_DIP_CTL definitions to their right place Dhinakaran Pandiyan
@ 2018-10-05 19:03 ` Manasi Navare
2018-10-29 20:46 ` Dhinakaran Pandiyan
0 siblings, 1 reply; 6+ messages in thread
From: Manasi Navare @ 2018-10-05 19:03 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx
On Fri, Oct 05, 2018 at 11:56:43AM -0700, Dhinakaran Pandiyan wrote:
> The bits weren't defined in descending order.
> v2: Move definitions in a separate patch (Manasi)
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 19 +++++++++----------
> 1 file changed, 9 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 61148b9a4a8e..a98b95922818 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4584,6 +4584,15 @@ enum {
> #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
> #define VIDEO_DIP_FREQ_MASK (3 << 16)
> /* HSW and later: */
> +#define DRM_DIP_ENABLE (1 << 28)
> +#define PSR_VSC_BIT_7_SET (1 << 27)
> +#define VSC_SELECT_MASK (0x3 << 25)
> +#define VSC_SELECT_SHIFT 25
> +#define VSC_DIP_HW_HEA_DATA (0 << 25)
> +#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
> +#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
> +#define VSC_DIP_SW_HEA_DATA (3 << 25)
> +#define VDIP_ENABLE_PPS (1 << 24)
> #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
> #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
> #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
> @@ -4591,16 +4600,6 @@ enum {
> #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
> #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
>
> -#define DRM_DIP_ENABLE (1 << 28)
> -#define PSR_VSC_BIT_7_SET (1 << 27)
> -#define VSC_SELECT_MASK (0x3 << 25)
> -#define VSC_SELECT_SHIFT 25
> -#define VSC_DIP_HW_HEA_DATA (0 << 25)
> -#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
> -#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
> -#define VSC_DIP_SW_HEA_DATA (3 << 25)
> -#define VDIP_ENABLE_PPS (1 << 24)
> -
> /* Panel power sequencing */
> #define PPS_BASE 0x61200
> #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
> --
> 2.17.1
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 2/2] drm/i915: Move VIDEO_DIP_CTL definitions to their right place.
2018-10-05 19:03 ` Manasi Navare
@ 2018-10-29 20:46 ` Dhinakaran Pandiyan
0 siblings, 0 replies; 6+ messages in thread
From: Dhinakaran Pandiyan @ 2018-10-29 20:46 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Fri, 2018-10-05 at 12:03 -0700, Manasi Navare wrote:
> On Fri, Oct 05, 2018 at 11:56:43AM -0700, Dhinakaran Pandiyan wrote:
> > The bits weren't defined in descending order.
> > v2: Move definitions in a separate patch (Manasi)
> >
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Thanks for the reviews, pushed.
-DK
>
> Manasi
>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 19 +++++++++----------
> > 1 file changed, 9 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 61148b9a4a8e..a98b95922818 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4584,6 +4584,15 @@ enum {
> > #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
> > #define VIDEO_DIP_FREQ_MASK (3 << 16)
> > /* HSW and later: */
> > +#define DRM_DIP_ENABLE (1 << 28)
> > +#define PSR_VSC_BIT_7_SET (1 << 27)
> > +#define VSC_SELECT_MASK (0x3 << 25)
> > +#define VSC_SELECT_SHIFT 25
> > +#define VSC_DIP_HW_HEA_DATA (0 << 25)
> > +#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
> > +#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
> > +#define VSC_DIP_SW_HEA_DATA (3 << 25)
> > +#define VDIP_ENABLE_PPS (1 << 24)
> > #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
> > #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
> > #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
> > @@ -4591,16 +4600,6 @@ enum {
> > #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
> > #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
> >
> > -#define DRM_DIP_ENABLE (1 << 28)
> > -#define PSR_VSC_BIT_7_SET (1 << 27)
> > -#define VSC_SELECT_MASK (0x3 << 25)
> > -#define VSC_SELECT_SHIFT 25
> > -#define VSC_DIP_HW_HEA_DATA (0 << 25)
> > -#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
> > -#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
> > -#define VSC_DIP_SW_HEA_DATA (3 << 25)
> > -#define VDIP_ENABLE_PPS (1 << 24)
> > -
> > /* Panel power sequencing */
> > #define PPS_BASE 0x61200
> > #define VLV_PPS_BASE (VLV_DISPLAY_BASE +
> > PPS_BASE)
> > --
> > 2.17.1
> >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Fix VIDEO_DIP_CTL bit shifts
2018-10-05 18:56 [PATCH 1/2] drm/i915: Fix VIDEO_DIP_CTL bit shifts Dhinakaran Pandiyan
2018-10-05 18:56 ` [PATCH 2/2] drm/i915: Move VIDEO_DIP_CTL definitions to their right place Dhinakaran Pandiyan
@ 2018-10-05 19:44 ` Patchwork
2018-10-06 2:00 ` ✓ Fi.CI.IGT: " Patchwork
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2018-10-05 19:44 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915: Fix VIDEO_DIP_CTL bit shifts
URL : https://patchwork.freedesktop.org/series/50636/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4941 -> Patchwork_10381 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/50636/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_10381 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_module_reload@basic-reload:
fi-blb-e6850: NOTRUN -> INCOMPLETE (fdo#107718)
igt@gem_exec_suspend@basic-s4-devices:
fi-bdw-samus: NOTRUN -> INCOMPLETE (fdo#107773)
==== Possible fixes ====
igt@drv_selftest@live_coherency:
fi-gdg-551: DMESG-FAIL (fdo#107164) -> PASS
igt@gem_exec_suspend@basic-s3:
fi-bdw-samus: INCOMPLETE (fdo#107773) -> PASS
fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS
fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
== Participating hosts (46 -> 40) ==
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-u2 fi-ctg-p8600
== Build changes ==
* Linux: CI_DRM_4941 -> Patchwork_10381
CI_DRM_4941: f63d55e904fffdda6bc114ca7ee2a7ff642b9e6b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4670: 7e066794d2ea860f4199fd67549080de17b6b852 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10381: 7689163267c8715cd4784d711550ed94ddfd2fa5 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7689163267c8 drm/i915: Move VIDEO_DIP_CTL definitions to their right place.
120b1b6bdea3 drm/i915: Fix VIDEO_DIP_CTL bit shifts
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10381/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Fix VIDEO_DIP_CTL bit shifts
2018-10-05 18:56 [PATCH 1/2] drm/i915: Fix VIDEO_DIP_CTL bit shifts Dhinakaran Pandiyan
2018-10-05 18:56 ` [PATCH 2/2] drm/i915: Move VIDEO_DIP_CTL definitions to their right place Dhinakaran Pandiyan
2018-10-05 19:44 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Fix VIDEO_DIP_CTL bit shifts Patchwork
@ 2018-10-06 2:00 ` Patchwork
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2018-10-06 2:00 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915: Fix VIDEO_DIP_CTL bit shifts
URL : https://patchwork.freedesktop.org/series/50636/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4941_full -> Patchwork_10381_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10381_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10381_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10381_full:
=== IGT changes ===
==== Warnings ====
igt@perf_pmu@rc6:
shard-kbl: SKIP -> PASS
igt@pm_rc6_residency@rc6-accuracy:
shard-snb: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_10381_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_cpu_reloc@full:
shard-skl: NOTRUN -> INCOMPLETE (fdo#108073)
igt@gem_eio@in-flight-suspend:
shard-skl: NOTRUN -> INCOMPLETE (fdo#104108, fdo#107773) +1
igt@gem_exec_schedule@pi-ringfull-blt:
shard-skl: NOTRUN -> FAIL (fdo#103158) +2
igt@gem_userptr_blits@invalid-null-pointer:
shard-glk: PASS -> DMESG-WARN (fdo#106538, fdo#105763) +1
igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
shard-skl: NOTRUN -> DMESG-WARN (fdo#107956)
igt@kms_cursor_crc@cursor-64x21-random:
shard-apl: PASS -> FAIL (fdo#103232) +4
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
shard-glk: PASS -> FAIL (fdo#103167)
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
shard-apl: PASS -> FAIL (fdo#103167) +4
igt@kms_panel_fitting@legacy:
shard-skl: NOTRUN -> FAIL (fdo#105456)
igt@kms_plane@pixel-format-pipe-b-planes:
shard-skl: NOTRUN -> DMESG-WARN (fdo#106885)
{igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb}:
shard-skl: NOTRUN -> FAIL (fdo#108145) +2
igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
shard-apl: PASS -> FAIL (fdo#103166)
shard-glk: PASS -> FAIL (fdo#103166)
==== Possible fixes ====
igt@gem_exec_await@wide-contexts:
shard-glk: FAIL (fdo#106680) -> PASS
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
shard-glk: DMESG-WARN (fdo#107956) -> PASS
igt@kms_cursor_crc@cursor-256x85-sliding:
shard-apl: FAIL (fdo#103232) -> PASS +5
igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS +3
igt@kms_flip@plain-flip-fb-recreate:
shard-skl: FAIL (fdo#100368) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
shard-apl: FAIL (fdo#103167) -> PASS +1
shard-glk: FAIL (fdo#103167) -> PASS +1
igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
shard-glk: FAIL (fdo#103166) -> PASS +1
shard-apl: FAIL (fdo#103166) -> PASS +2
igt@kms_setmode@basic:
shard-kbl: FAIL (fdo#99912) -> PASS
==== Warnings ====
igt@kms_cursor_crc@cursor-64x64-suspend:
shard-apl: FAIL (fdo#103232, fdo#103191) -> INCOMPLETE (fdo#103927)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#105456 https://bugs.freedesktop.org/show_bug.cgi?id=105456
fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
fdo#106680 https://bugs.freedesktop.org/show_bug.cgi?id=106680
fdo#106885 https://bugs.freedesktop.org/show_bug.cgi?id=106885
fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
fdo#108073 https://bugs.freedesktop.org/show_bug.cgi?id=108073
fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (6 -> 6) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4941 -> Patchwork_10381
CI_DRM_4941: f63d55e904fffdda6bc114ca7ee2a7ff642b9e6b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4670: 7e066794d2ea860f4199fd67549080de17b6b852 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10381: 7689163267c8715cd4784d711550ed94ddfd2fa5 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10381/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-10-29 20:46 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-10-05 18:56 [PATCH 1/2] drm/i915: Fix VIDEO_DIP_CTL bit shifts Dhinakaran Pandiyan
2018-10-05 18:56 ` [PATCH 2/2] drm/i915: Move VIDEO_DIP_CTL definitions to their right place Dhinakaran Pandiyan
2018-10-05 19:03 ` Manasi Navare
2018-10-29 20:46 ` Dhinakaran Pandiyan
2018-10-05 19:44 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Fix VIDEO_DIP_CTL bit shifts Patchwork
2018-10-06 2:00 ` ✓ Fi.CI.IGT: " Patchwork
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