From: Will Deacon <will.deacon@arm.com>
To: Punit Agrawal <punit.agrawal@arm.com>
Cc: Randy Dunlap <rdunlap@infradead.org>,
linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, steve.capper@arm.com,
Catalin Marinas <catalin.marinas@arm.com>,
Jonathan Corbet <corbet@lwn.net>
Subject: Re: [PATCH v2] Documentation/arm64: HugeTLB page implementation
Date: Tue, 9 Oct 2018 12:50:49 +0100 [thread overview]
Message-ID: <20181009115049.GA6248@arm.com> (raw)
In-Reply-To: <87ftxf7812.fsf@e105922-lin.cambridge.arm.com>
On Tue, Oct 09, 2018 at 11:02:01AM +0100, Punit Agrawal wrote:
> Randy Dunlap <rdunlap@infradead.org> writes:
>
> > On 10/8/18 3:03 AM, Punit Agrawal wrote:
> >> Arm v8 architecture supports multiple page sizes - 4k, 16k and
> >> 64k. Based on the active page size, the Linux port supports
> >> corresponding hugepage sizes at PMD and PUD(4k only) levels.
> >>
> >> In addition, the architecture also supports caching larger sized
> >> ranges (composed of multiple entries) at the PTE and PMD level in the
> >> TLBs using the contiguous bit. The Linux port makes use of this
> >> architectural support to enable additional hugepage sizes.
> >>
> >> Describe the two different types of hugepages supported by the arm64
> >> kernel and the hugepage sizes enabled by each.
> >>
> >> Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
> >> Cc: Catalin Marinas <catalin.marinas@arm.com>
> >> Cc: Will Deacon <will.deacon@arm.com>
> >> Cc: Jonathan Corbet <corbet@lwn.net>
> >
> > Acked-by: Randy Dunlap <rdunlap@infradead.org>
>
> Thanks!
>
> Catalin, Will - I assume you'll pick this up at some point? Or do arm64
> documentation patches get routed by another tree?
Acked-by: Will Deacon <will.deacon@arm.com>
Catalin can pick this up for 4.20.
Will
WARNING: multiple messages have this Message-ID (diff)
From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2] Documentation/arm64: HugeTLB page implementation
Date: Tue, 9 Oct 2018 12:50:49 +0100 [thread overview]
Message-ID: <20181009115049.GA6248@arm.com> (raw)
In-Reply-To: <87ftxf7812.fsf@e105922-lin.cambridge.arm.com>
On Tue, Oct 09, 2018 at 11:02:01AM +0100, Punit Agrawal wrote:
> Randy Dunlap <rdunlap@infradead.org> writes:
>
> > On 10/8/18 3:03 AM, Punit Agrawal wrote:
> >> Arm v8 architecture supports multiple page sizes - 4k, 16k and
> >> 64k. Based on the active page size, the Linux port supports
> >> corresponding hugepage sizes at PMD and PUD(4k only) levels.
> >>
> >> In addition, the architecture also supports caching larger sized
> >> ranges (composed of multiple entries) at the PTE and PMD level in the
> >> TLBs using the contiguous bit. The Linux port makes use of this
> >> architectural support to enable additional hugepage sizes.
> >>
> >> Describe the two different types of hugepages supported by the arm64
> >> kernel and the hugepage sizes enabled by each.
> >>
> >> Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
> >> Cc: Catalin Marinas <catalin.marinas@arm.com>
> >> Cc: Will Deacon <will.deacon@arm.com>
> >> Cc: Jonathan Corbet <corbet@lwn.net>
> >
> > Acked-by: Randy Dunlap <rdunlap@infradead.org>
>
> Thanks!
>
> Catalin, Will - I assume you'll pick this up at some point? Or do arm64
> documentation patches get routed by another tree?
Acked-by: Will Deacon <will.deacon@arm.com>
Catalin can pick this up for 4.20.
Will
next prev parent reply other threads:[~2018-10-09 11:50 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-05 14:34 [PATCH] Documentation/arm64: HugeTLB page implementation Punit Agrawal
2018-10-05 14:34 ` Punit Agrawal
2018-10-06 16:30 ` Randy Dunlap
2018-10-06 16:30 ` Randy Dunlap
2018-10-08 9:39 ` Punit Agrawal
2018-10-08 9:39 ` Punit Agrawal
2018-10-08 10:03 ` [PATCH v2] " Punit Agrawal
2018-10-08 10:03 ` Punit Agrawal
2018-10-08 19:49 ` Randy Dunlap
2018-10-08 19:49 ` Randy Dunlap
2018-10-09 10:02 ` Punit Agrawal
2018-10-09 10:02 ` Punit Agrawal
2018-10-09 11:50 ` Will Deacon [this message]
2018-10-09 11:50 ` Will Deacon
2018-10-10 17:08 ` Catalin Marinas
2018-10-10 17:08 ` Catalin Marinas
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