* [Buildroot] [PATCH v3 1/3] arch: add support for RISC-V 32-bit (riscv32) architecture
@ 2018-10-21 14:00 Mark Corbin
2018-10-21 14:00 ` [Buildroot] [PATCH v3 2/3] configs/qemu: add qemu_riscv32_virt_defconfig Mark Corbin
2018-10-21 14:01 ` [Buildroot] [PATCH v3 3/3] support/config-fragments: add RISC-V 32-bit to autobuild configs Mark Corbin
0 siblings, 2 replies; 4+ messages in thread
From: Mark Corbin @ 2018-10-21 14:00 UTC (permalink / raw)
To: buildroot
This enables a riscv32 system to be built with a Buildroot generated
toolchain (gcc >= 7.x, binutils >= 2.30, glibc only).
This requires a custom version of glibc 2.26 from the riscv-glibc
repository. Note that there are no tags in this repository, so the
glibc version just consists of the 40 character commit id string.
Thanks to Fabrice Bellard for pointing me towards the 32-bit glibc
repository and for providing the necessary patch to get it to build.
Signed-off-by: Mark Corbin <mark.corbin@embecosm.com>
---
Changes v2 -> v3:
- updated the autobuild configuration for RISC-V 64-bit as the
default RISC-V configuration is now 32-bit.
Changes v1 -> v2:
- regenerated the glibc patch correctly (Romain)
- modified the conditional test for RISC-V 32-bit in glibc.mk
to use the more consistent style for multiple variables (Romain)
---
arch/Config.in.riscv | 23 +++++++-
arch/arch.mk.riscv | 4 +-
configs/qemu_riscv64_virt_defconfig | 1 +
...C-V-32-bit-build-of-riscv-glibc-2.26.patch | 59 +++++++++++++++++++
.../glibc.hash | 7 +++
package/glibc/glibc.mk | 7 +++
.../br-riscv64-internal-glibc.config | 1 +
7 files changed, 98 insertions(+), 4 deletions(-)
create mode 100644 package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/0001-Fix-RISC-V-32-bit-build-of-riscv-glibc-2.26.patch
create mode 100644 package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/glibc.hash
diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv
index 4361890bf4..4615f3c797 100644
--- a/arch/Config.in.riscv
+++ b/arch/Config.in.riscv
@@ -66,13 +66,26 @@ config BR2_RISCV_ISA_CUSTOM_RVC
endif
config BR2_RISCV_64
- bool
- default y
+ bool "64-bit"
+ default n
select BR2_ARCH_IS_64
choice
prompt "Target ABI"
- default BR2_RISCV_ABI_LP64
+ default BR2_RISCV_ABI_ILP32 if !BR2_ARCH_IS_64
+ default BR2_RISCV_ABI_LP64 if BR2_ARCH_IS_64
+
+config BR2_RISCV_ABI_ILP32
+ bool "ilp32"
+ depends on !BR2_ARCH_IS_64
+
+config BR2_RISCV_ABI_ILP32F
+ bool "ilp32f"
+ depends on !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF
+
+config BR2_RISCV_ABI_ILP32D
+ bool "ilp32d"
+ depends on !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD
config BR2_RISCV_ABI_LP64
bool "lp64"
@@ -88,12 +101,16 @@ config BR2_RISCV_ABI_LP64D
endchoice
config BR2_ARCH
+ default "riscv32" if !BR2_ARCH_IS_64
default "riscv64" if BR2_ARCH_IS_64
config BR2_ENDIAN
default "LITTLE"
config BR2_GCC_TARGET_ABI
+ default "ilp32" if BR2_RISCV_ABI_ILP32
+ default "ilp32f" if BR2_RISCV_ABI_ILP32F
+ default "ilp32d" if BR2_RISCV_ABI_ILP32D
default "lp64" if BR2_RISCV_ABI_LP64
default "lp64f" if BR2_RISCV_ABI_LP64F
default "lp64d" if BR2_RISCV_ABI_LP64D
diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv
index 022d1a6809..f3bf2b3467 100644
--- a/arch/arch.mk.riscv
+++ b/arch/arch.mk.riscv
@@ -5,8 +5,10 @@
ifeq ($(BR2_riscv),y)
-ifeq ($(BR2_ARCH_IS_64),y)
+ifeq ($(BR2_RISCV_64),y)
GCC_TARGET_ARCH := rv64i
+else
+GCC_TARGET_ARCH := rv32i
endif
ifeq ($(BR2_RISCV_ISA_RVM),y)
diff --git a/configs/qemu_riscv64_virt_defconfig b/configs/qemu_riscv64_virt_defconfig
index 59343ee98f..e15f804341 100644
--- a/configs/qemu_riscv64_virt_defconfig
+++ b/configs/qemu_riscv64_virt_defconfig
@@ -1,5 +1,6 @@
# Architecture
BR2_riscv=y
+BR2_RISCV_64=y
# System
BR2_SYSTEM_DHCP="eth0"
diff --git a/package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/0001-Fix-RISC-V-32-bit-build-of-riscv-glibc-2.26.patch b/package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/0001-Fix-RISC-V-32-bit-build-of-riscv-glibc-2.26.patch
new file mode 100644
index 0000000000..0596587ac5
--- /dev/null
+++ b/package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/0001-Fix-RISC-V-32-bit-build-of-riscv-glibc-2.26.patch
@@ -0,0 +1,59 @@
+From 4909cfbbe8dd512b8fc0892859549c26e1b14d30 Mon Sep 17 00:00:00 2001
+From: Mark Corbin <mark.corbin@embecosm.com>
+Date: Sun, 21 Oct 2018 10:38:18 +0100
+Subject: [PATCH 1/1] Fix RISC-V 32-bit build of riscv-glibc 2.26
+
+This patch fixes two build errors with the 32-bit version of
+glibc-2.26 from the riscv-glibc repository.
+
+A void reference to 'refsym' has been added to dl-runtime.c to avoid
+an 'unused variable' error when building with '-Werror'.
+
+Some data types were hard-coded for 64-bit in ldsodefs.h. These have
+been modified to allow 32-bit builds.
+
+This patch was provided by Fabrice Bellard as part of his RISC-V
+Buildroot development source.
+
+Signed-off-by: Mark Corbin <mark.corbin@embecosm.com>
+---
+ elf/dl-runtime.c | 1 +
+ sysdeps/riscv/ldsodefs.h | 4 ++--
+ 2 files changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/elf/dl-runtime.c b/elf/dl-runtime.c
+index 51d3819d4a..e728e8907e 100644
+--- a/elf/dl-runtime.c
++++ b/elf/dl-runtime.c
+@@ -146,6 +146,7 @@ _dl_fixup (
+ if (__glibc_unlikely (GLRO(dl_bind_not)))
+ return value;
+
++ (void)refsym;
+ return elf_machine_fixup_plt (l, result, refsym, sym, reloc, rel_addr, value);
+ }
+
+diff --git a/sysdeps/riscv/ldsodefs.h b/sysdeps/riscv/ldsodefs.h
+index db993df80a..91e7a8c88f 100644
+--- a/sysdeps/riscv/ldsodefs.h
++++ b/sysdeps/riscv/ldsodefs.h
+@@ -25,14 +25,14 @@ struct La_riscv_regs;
+ struct La_riscv_retval;
+
+ #define ARCH_PLTENTER_MEMBERS \
+- Elf64_Addr (*riscv_gnu_pltenter) (Elf64_Sym *, unsigned int, \
++ ElfW(Addr) (*riscv_gnu_pltenter) (ElfW(Sym) *, unsigned int, \
+ uintptr_t *, uintptr_t *, \
+ const struct La_riscv_regs *, \
+ unsigned int *, const char *name, \
+ long int *framesizep);
+
+ #define ARCH_PLTEXIT_MEMBERS \
+- unsigned int (*riscv_gnu_pltexit) (Elf64_Sym *, unsigned int, \
++ unsigned int (*riscv_gnu_pltexit) (ElfW(Sym) *, unsigned int, \
+ uintptr_t *, uintptr_t *, \
+ const struct La_riscv_regs *, \
+ struct La_riscv_retval *, \
+--
+2.17.1
+
diff --git a/package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/glibc.hash b/package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/glibc.hash
new file mode 100644
index 0000000000..3eb5e04e96
--- /dev/null
+++ b/package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/glibc.hash
@@ -0,0 +1,7 @@
+# Locally calculated (fetched from Github)
+sha256 a40f908125135bad2cf92c18d07ad25b3091b161b3a5d3aea46c23ffd2ac90b8 glibc-4e2943456e690d89f48e6e710757dd09404b0c9a.tar.gz
+
+# Hashes for license files
+sha256 8177f97513213526df2cf6184d8ff986c675afb514d4e68a404010521b880643 COPYING
+sha256 dc626520dcd53a22f727af3ee42c770e56c97a64fe3adb063799d8ab032fe551 COPYING.LIB
+sha256 61abdd6930c9c599062d89e916b3e7968783879b6be0ee1c6229dd6169def431 LICENSES
diff --git a/package/glibc/glibc.mk b/package/glibc/glibc.mk
index 708c22f723..408711bfb7 100644
--- a/package/glibc/glibc.mk
+++ b/package/glibc/glibc.mk
@@ -7,6 +7,9 @@
ifeq ($(BR2_arc),y)
GLIBC_VERSION = arc-2018.03-release
GLIBC_SITE = $(call github,foss-for-synopsys-dwc-arc-processors,glibc,$(GLIBC_VERSION))
+else ifeq ($(BR2_riscv):$(BR2_RISCV_64),y:)
+GLIBC_VERSION = 4e2943456e690d89f48e6e710757dd09404b0c9a
+GLIBC_SITE = $(call github,riscv,riscv-glibc,$(GLIBC_VERSION))
else
# Generate version string using:
# git describe --match 'glibc-*' --abbrev=40 origin/release/MAJOR.MINOR/master
@@ -79,7 +82,11 @@ GLIBC_CONF_ENV = \
# Override the default library locations of /lib64/<abi> and
# /usr/lib64/<abi>/ for RISC-V.
ifeq ($(BR2_riscv),y)
+ifeq ($(BR2_RISCV_64),y)
GLIBC_CONF_ENV += libc_cv_slibdir=/lib64 libc_cv_rtlddir=/lib
+else
+GLIBC_CONF_ENV += libc_cv_slibdir=/lib32 libc_cv_rtlddir=/lib
+endif
endif
# Even though we use the autotools-package infrastructure, we have to
diff --git a/support/config-fragments/autobuild/br-riscv64-internal-glibc.config b/support/config-fragments/autobuild/br-riscv64-internal-glibc.config
index 75aa5dd915..d952c73a86 100644
--- a/support/config-fragments/autobuild/br-riscv64-internal-glibc.config
+++ b/support/config-fragments/autobuild/br-riscv64-internal-glibc.config
@@ -1,2 +1,3 @@
BR2_riscv=y
+BR2_RISCV_64=y
BR2_TOOLCHAIN_BUILDROOT_GLIBC=y
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Buildroot] [PATCH v3 2/3] configs/qemu: add qemu_riscv32_virt_defconfig
2018-10-21 14:00 [Buildroot] [PATCH v3 1/3] arch: add support for RISC-V 32-bit (riscv32) architecture Mark Corbin
@ 2018-10-21 14:00 ` Mark Corbin
2018-10-21 14:37 ` Matthew Weber
2018-10-21 14:01 ` [Buildroot] [PATCH v3 3/3] support/config-fragments: add RISC-V 32-bit to autobuild configs Mark Corbin
1 sibling, 1 reply; 4+ messages in thread
From: Mark Corbin @ 2018-10-21 14:00 UTC (permalink / raw)
To: buildroot
Add RISC-V 32-bit defconfig for QEMU virt machine.
Tested with QEMU 2.12.1
Signed-off-by: Mark Corbin <mark.corbin@embecosm.com>
---
board/qemu/riscv32-virt/linux.config | 23 +++++++++++++++++++++++
board/qemu/riscv32-virt/readme.txt | 7 +++++++
configs/qemu_riscv32_virt_defconfig | 24 ++++++++++++++++++++++++
3 files changed, 54 insertions(+)
create mode 100644 board/qemu/riscv32-virt/linux.config
create mode 100644 board/qemu/riscv32-virt/readme.txt
create mode 100644 configs/qemu_riscv32_virt_defconfig
diff --git a/board/qemu/riscv32-virt/linux.config b/board/qemu/riscv32-virt/linux.config
new file mode 100644
index 0000000000..c25583f768
--- /dev/null
+++ b/board/qemu/riscv32-virt/linux.config
@@ -0,0 +1,23 @@
+CONFIG_ARCH_RV32I=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=8
+CONFIG_PCI=y
+CONFIG_SYSVIPC=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_WIRELESS is not set
+CONFIG_VIRTIO_BLK=y
+CONFIG_NETDEVICES=y
+CONFIG_VIRTIO_NET=y
+# CONFIG_ETHERNET is not set
+# CONFIG_WLAN is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_VIRT_DRIVERS=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT4_FS=y
+CONFIG_TMPFS=y
diff --git a/board/qemu/riscv32-virt/readme.txt b/board/qemu/riscv32-virt/readme.txt
new file mode 100644
index 0000000000..2da99580e5
--- /dev/null
+++ b/board/qemu/riscv32-virt/readme.txt
@@ -0,0 +1,7 @@
+Run the emulation with:
+
+ qemu-system-riscv32 -M virt -kernel output/images/bbl -append "root=/dev/vda ro console=ttyS0" -drive file=output/images/rootfs.ext2,format=raw,id=hd0 -device virtio-blk-device,drive=hd0 -netdev user,id=net0 -device virtio-net-device,netdev=net0 -nographic
+
+The login prompt will appear in the terminal that started Qemu.
+
+Tested with QEMU 2.12.1
diff --git a/configs/qemu_riscv32_virt_defconfig b/configs/qemu_riscv32_virt_defconfig
new file mode 100644
index 0000000000..aec85e4639
--- /dev/null
+++ b/configs/qemu_riscv32_virt_defconfig
@@ -0,0 +1,24 @@
+# Architecture
+BR2_riscv=y
+
+# System
+BR2_SYSTEM_DHCP="eth0"
+
+# Filesystem
+BR2_TARGET_ROOTFS_EXT2=y
+BR2_TARGET_GENERIC_GETTY=y
+BR2_TARGET_GENERIC_GETTY_PORT="ttyS0"
+
+# Linux headers same as kernel, a 4.15 series
+BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_15=y
+
+# Kernel
+BR2_LINUX_KERNEL=y
+BR2_LINUX_KERNEL_CUSTOM_GIT=y
+BR2_LINUX_KERNEL_CUSTOM_REPO_URL="https://github.com/riscv/riscv-linux.git"
+BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="fe92d7905c6ea0ebeabeb725b8040754ede7c220"
+BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
+BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="board/qemu/riscv32-virt/linux.config"
+
+# Bootloader
+BR2_TARGET_RISCV_PK=y
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Buildroot] [PATCH v3 3/3] support/config-fragments: add RISC-V 32-bit to autobuild configs
2018-10-21 14:00 [Buildroot] [PATCH v3 1/3] arch: add support for RISC-V 32-bit (riscv32) architecture Mark Corbin
2018-10-21 14:00 ` [Buildroot] [PATCH v3 2/3] configs/qemu: add qemu_riscv32_virt_defconfig Mark Corbin
@ 2018-10-21 14:01 ` Mark Corbin
1 sibling, 0 replies; 4+ messages in thread
From: Mark Corbin @ 2018-10-21 14:01 UTC (permalink / raw)
To: buildroot
Add a minimal RISC-V 32-bit autobuild configuration for the
internal toolchain with glibc.
Signed-off-by: Mark Corbin <mark.corbin@embecosm.com>
---
.../config-fragments/autobuild/br-riscv32-internal-glibc.config | 2 ++
support/config-fragments/autobuild/toolchain-configs.csv | 1 +
2 files changed, 3 insertions(+)
create mode 100644 support/config-fragments/autobuild/br-riscv32-internal-glibc.config
diff --git a/support/config-fragments/autobuild/br-riscv32-internal-glibc.config b/support/config-fragments/autobuild/br-riscv32-internal-glibc.config
new file mode 100644
index 0000000000..75aa5dd915
--- /dev/null
+++ b/support/config-fragments/autobuild/br-riscv32-internal-glibc.config
@@ -0,0 +1,2 @@
+BR2_riscv=y
+BR2_TOOLCHAIN_BUILDROOT_GLIBC=y
diff --git a/support/config-fragments/autobuild/toolchain-configs.csv b/support/config-fragments/autobuild/toolchain-configs.csv
index f24ec9ced0..3681bc519f 100644
--- a/support/config-fragments/autobuild/toolchain-configs.csv
+++ b/support/config-fragments/autobuild/toolchain-configs.csv
@@ -51,6 +51,7 @@ support/config-fragments/autobuild/br-powerpc64le-power8-glibc.config,x86_64
support/config-fragments/autobuild/br-powerpc64-power7-glibc.config,x86_64
support/config-fragments/autobuild/br-powerpc-e500mc-full.config,x86_64
support/config-fragments/autobuild/br-powerpc-internal-full.config,any
+support/config-fragments/autobuild/br-riscv32-internal-glibc.config,any
support/config-fragments/autobuild/br-riscv64-internal-glibc.config,any
support/config-fragments/autobuild/br-sh4-full.config,x86_64
support/config-fragments/autobuild/br-sparc-uclibc.config,x86_64
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Buildroot] [PATCH v3 2/3] configs/qemu: add qemu_riscv32_virt_defconfig
2018-10-21 14:00 ` [Buildroot] [PATCH v3 2/3] configs/qemu: add qemu_riscv32_virt_defconfig Mark Corbin
@ 2018-10-21 14:37 ` Matthew Weber
0 siblings, 0 replies; 4+ messages in thread
From: Matthew Weber @ 2018-10-21 14:37 UTC (permalink / raw)
To: buildroot
Mark,
On Sun, Oct 21, 2018 at 3:02 PM Mark Corbin <mark.corbin@embecosm.com> wrote:
>
> Add RISC-V 32-bit defconfig for QEMU virt machine.
>
> Tested with QEMU 2.12.1
>
> Signed-off-by: Mark Corbin <mark.corbin@embecosm.com>
> ---
> board/qemu/riscv32-virt/linux.config | 23 +++++++++++++++++++++++
> board/qemu/riscv32-virt/readme.txt | 7 +++++++
> configs/qemu_riscv32_virt_defconfig | 24 ++++++++++++++++++++++++
> 3 files changed, 54 insertions(+)
> create mode 100644 board/qemu/riscv32-virt/linux.config
> create mode 100644 board/qemu/riscv32-virt/readme.txt
> create mode 100644 configs/qemu_riscv32_virt_defconfig
>
> diff --git a/board/qemu/riscv32-virt/linux.config b/board/qemu/riscv32-virt/linux.config
> new file mode 100644
> index 0000000000..c25583f768
> --- /dev/null
> +++ b/board/qemu/riscv32-virt/linux.config
> @@ -0,0 +1,23 @@
> +CONFIG_ARCH_RV32I=y
> +CONFIG_SMP=y
> +CONFIG_NR_CPUS=8
> +CONFIG_PCI=y
> +CONFIG_SYSVIPC=y
> +CONFIG_NET=y
> +CONFIG_PACKET=y
> +CONFIG_UNIX=y
> +CONFIG_INET=y
> +# CONFIG_WIRELESS is not set
> +CONFIG_VIRTIO_BLK=y
> +CONFIG_NETDEVICES=y
> +CONFIG_VIRTIO_NET=y
> +# CONFIG_ETHERNET is not set
> +# CONFIG_WLAN is not set
> +CONFIG_SERIAL_8250=y
> +CONFIG_SERIAL_8250_CONSOLE=y
> +CONFIG_SERIAL_OF_PLATFORM=y
> +CONFIG_VIRT_DRIVERS=y
> +CONFIG_VIRTIO_MMIO=y
> +CONFIG_EXT2_FS=y
> +CONFIG_EXT4_FS=y
> +CONFIG_TMPFS=y
> diff --git a/board/qemu/riscv32-virt/readme.txt b/board/qemu/riscv32-virt/readme.txt
> new file mode 100644
> index 0000000000..2da99580e5
> --- /dev/null
> +++ b/board/qemu/riscv32-virt/readme.txt
> @@ -0,0 +1,7 @@
> +Run the emulation with:
> +
> + qemu-system-riscv32 -M virt -kernel output/images/bbl -append "root=/dev/vda ro console=ttyS0" -drive file=output/images/rootfs.ext2,format=raw,id=hd0 -device virtio-blk-device,drive=hd0 -netdev user,id=net0 -device virtio-net-device,netdev=net0 -nographic
> +
> +The login prompt will appear in the terminal that started Qemu.
Worked for my build. Thanks for adding the readme!
Linux buildroot 4.15.0 #1 SMP Sun Oct 21 08:31:02 CDT 2018 riscv32 GNU/Linux
Tested-by: Matt Weber <matthew.weber@rockwellcollins.com>
> +
> +Tested with QEMU 2.12.1
> diff --git a/configs/qemu_riscv32_virt_defconfig b/configs/qemu_riscv32_virt_defconfig
> new file mode 100644
> index 0000000000..aec85e4639
> --- /dev/null
> +++ b/configs/qemu_riscv32_virt_defconfig
> @@ -0,0 +1,24 @@
> +# Architecture
> +BR2_riscv=y
> +
> +# System
> +BR2_SYSTEM_DHCP="eth0"
> +
> +# Filesystem
> +BR2_TARGET_ROOTFS_EXT2=y
> +BR2_TARGET_GENERIC_GETTY=y
> +BR2_TARGET_GENERIC_GETTY_PORT="ttyS0"
> +
> +# Linux headers same as kernel, a 4.15 series
> +BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_15=y
> +
> +# Kernel
> +BR2_LINUX_KERNEL=y
> +BR2_LINUX_KERNEL_CUSTOM_GIT=y
> +BR2_LINUX_KERNEL_CUSTOM_REPO_URL="https://github.com/riscv/riscv-linux.git"
> +BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="fe92d7905c6ea0ebeabeb725b8040754ede7c220"
> +BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
> +BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="board/qemu/riscv32-virt/linux.config"
> +
> +# Bootloader
> +BR2_TARGET_RISCV_PK=y
> --
> 2.17.1
>
> _______________________________________________
> buildroot mailing list
> buildroot at busybox.net
> http://lists.busybox.net/mailman/listinfo/buildroot
--
Matthew L Weber / Pr Software Engineer
Airborne Information Systems / RC Linux Secure Platforms
MS 131-100, C Ave NE, Cedar Rapids, IA, 52498, USA
www.rockwellcollins.com
Note: Any Export License Required Information and License Restricted
Third Party Intellectual Property (TPIP) content must be encrypted and
sent to matthew.weber at corp.rockwellcollins.com.
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-10-21 14:37 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-10-21 14:00 [Buildroot] [PATCH v3 1/3] arch: add support for RISC-V 32-bit (riscv32) architecture Mark Corbin
2018-10-21 14:00 ` [Buildroot] [PATCH v3 2/3] configs/qemu: add qemu_riscv32_virt_defconfig Mark Corbin
2018-10-21 14:37 ` Matthew Weber
2018-10-21 14:01 ` [Buildroot] [PATCH v3 3/3] support/config-fragments: add RISC-V 32-bit to autobuild configs Mark Corbin
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