From: Moritz Fischer <mdf@kernel.org>
To: Mike Looijmans <mike.looijmans@topic.nl>
Cc: linux-fpga@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, michal.simek@xilinx.com,
mdf@kernel.org, atull@kernel.org
Subject: Re: [PATCH] zynq-fpga: Only route PR via PCAP when required
Date: Tue, 23 Oct 2018 10:01:19 +0100 [thread overview]
Message-ID: <20181023090119.GA2205@archbook> (raw)
In-Reply-To: <1540276279-2903-1-git-send-email-mike.looijmans@topic.nl>
Hi Mike,
seems like a good usecase (though uncommon), question below
On Tue, Oct 23, 2018 at 08:31:19AM +0200, Mike Looijmans wrote:
> The Xilinx Zynq FPGA driver takes ownership of the PR interface, making
> it impossible to use the ICAP interface for partial reconfiguration.
>
> This patch changes the driver to only activate PR over PCAP while the
> device is actively being accessed by the driver for programming.
>
> This allows both PCAP and ICAP interfaces to be used for PR.
>
> Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
> ---
> drivers/fpga/zynq-fpga.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
> index 3110e00..f6c205a 100644
> --- a/drivers/fpga/zynq-fpga.c
> +++ b/drivers/fpga/zynq-fpga.c
> @@ -497,6 +497,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr,
> int err;
> u32 intr_status;
>
> + /* Release 'PR' control back to the ICAP */
> + zynq_fpga_write(priv, CTRL_OFFSET,
> + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK);
> +
Shouldn't that be after the below stanza that enables the clock?
> err = clk_enable(priv->clk);
> if (err)
> return err;
> --
> 1.9.1
>
Cheers,
Moritz
WARNING: multiple messages have this Message-ID (diff)
From: mdf@kernel.org (Moritz Fischer)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] zynq-fpga: Only route PR via PCAP when required
Date: Tue, 23 Oct 2018 10:01:19 +0100 [thread overview]
Message-ID: <20181023090119.GA2205@archbook> (raw)
In-Reply-To: <1540276279-2903-1-git-send-email-mike.looijmans@topic.nl>
Hi Mike,
seems like a good usecase (though uncommon), question below
On Tue, Oct 23, 2018 at 08:31:19AM +0200, Mike Looijmans wrote:
> The Xilinx Zynq FPGA driver takes ownership of the PR interface, making
> it impossible to use the ICAP interface for partial reconfiguration.
>
> This patch changes the driver to only activate PR over PCAP while the
> device is actively being accessed by the driver for programming.
>
> This allows both PCAP and ICAP interfaces to be used for PR.
>
> Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
> ---
> drivers/fpga/zynq-fpga.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
> index 3110e00..f6c205a 100644
> --- a/drivers/fpga/zynq-fpga.c
> +++ b/drivers/fpga/zynq-fpga.c
> @@ -497,6 +497,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr,
> int err;
> u32 intr_status;
>
> + /* Release 'PR' control back to the ICAP */
> + zynq_fpga_write(priv, CTRL_OFFSET,
> + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK);
> +
Shouldn't that be after the below stanza that enables the clock?
> err = clk_enable(priv->clk);
> if (err)
> return err;
> --
> 1.9.1
>
Cheers,
Moritz
next prev parent reply other threads:[~2018-10-23 9:01 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-23 6:31 [PATCH] zynq-fpga: Only route PR via PCAP when required Mike Looijmans
2018-10-23 6:31 ` Mike Looijmans
2018-10-23 9:01 ` Moritz Fischer [this message]
2018-10-23 9:01 ` Moritz Fischer
2018-10-23 10:53 ` Mike Looijmans
2018-10-23 10:53 ` Mike Looijmans
2018-10-23 11:04 ` Moritz Fischer
2018-10-23 11:04 ` Moritz Fischer
2018-10-26 7:54 ` Michal Simek
2018-10-26 7:54 ` Michal Simek
2018-10-26 17:04 ` Moritz Fischer
2018-10-26 17:04 ` Moritz Fischer
2018-10-24 7:53 ` [PATCH v2] " Mike Looijmans
2018-10-24 7:53 ` Mike Looijmans
2018-11-01 18:33 ` Alan Tull
2018-11-01 18:33 ` Alan Tull
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