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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Romain Izard <romain.izard.pro@gmail.com>
Cc: linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	linux-mtd <linux-mtd@lists.infradead.org>,
	linux-clk@vger.kernel.org
Subject: Re: Clock configuration for the SAMA5D2 NAND controller
Date: Tue, 30 Oct 2018 10:49:03 +0100	[thread overview]
Message-ID: <20181030104903.518f1fdd@xps13> (raw)
In-Reply-To: <CAGkQfmMphvck9rraYq+o8zA254q7ETYyniiUV-QBsUR9X+OFKQ@mail.gmail.com>

Hi Romain,

Romain Izard <romain.izard.pro@gmail.com> wrote on Wed, 17 Oct 2018
12:42:28 +0200:

> +linux-mtd, linux-clk
> 
> Le mer. 10 oct. 2018 à 19:05, Romain Izard
> <romain.izard.pro@gmail.com> a écrit :
> >
> > Hello,
> >
> > While evaluating a new flash memory chip for my product based on a SAMA5D2
> > chip, I tried to update my software to use the latest device tree bindings.
> >
> > Until now, I was using the legacy bindings for the NAND controller, that
> > preserved the timings configured by the bootloader in the EBI registers. The
> > bindings introduced in Linux 4.13 are used together with the NAND driver to
> > reconfigure the timings of the memory interface to match the speed profile
> > declared by some NAND components.
> >
> > However, when comparing the timings in the registers, there was a large
> > difference between what I calculated by hand in the past and the values
> > configured by the drivers. The difference was in fact a 2 factor.
> >
> > For me, the issue is due to the clock configuration declared in the SAMA5D2
> > device tree: The reference clock used by the nand-controller driver is the
> > clock for its parent node, which is directly the Master Clock. And on my
> > end, what I understood when writing the clock settings for my bootloader was
> > that the reference clock was the HSMC clock, which derives from the H32MX
> > clock, which runs at half the rate of the Master Clock.
> >
> > The documentation for the SAMA5D2 is not very precise on this topic, so I
> > would like to have some feedback. Is the clock used as a reference for the
> > chip select configuration registers the Master Clock itself, or is it the
> > peripheral clock for the HSMC module ?
> >

FYI I had the same issue on the Marvell NAND controller: the actual
frequency of the controller clock was half of the "parent" clock
retrieved by clk_get_rate(), hence I needed to double the clock period
for the timings derivation in ->setup_data_interface().

If you can't get more feedback from SAMA5 people and if this works for
you, please send a patch with a nice comment.


Thanks,
Miquèl

WARNING: multiple messages have this Message-ID (diff)
From: miquel.raynal@bootlin.com (Miquel Raynal)
To: linux-arm-kernel@lists.infradead.org
Subject: Clock configuration for the SAMA5D2 NAND controller
Date: Tue, 30 Oct 2018 10:49:03 +0100	[thread overview]
Message-ID: <20181030104903.518f1fdd@xps13> (raw)
In-Reply-To: <CAGkQfmMphvck9rraYq+o8zA254q7ETYyniiUV-QBsUR9X+OFKQ@mail.gmail.com>

Hi Romain,

Romain Izard <romain.izard.pro@gmail.com> wrote on Wed, 17 Oct 2018
12:42:28 +0200:

> +linux-mtd, linux-clk
> 
> Le mer. 10 oct. 2018 ? 19:05, Romain Izard
> <romain.izard.pro@gmail.com> a ?crit :
> >
> > Hello,
> >
> > While evaluating a new flash memory chip for my product based on a SAMA5D2
> > chip, I tried to update my software to use the latest device tree bindings.
> >
> > Until now, I was using the legacy bindings for the NAND controller, that
> > preserved the timings configured by the bootloader in the EBI registers. The
> > bindings introduced in Linux 4.13 are used together with the NAND driver to
> > reconfigure the timings of the memory interface to match the speed profile
> > declared by some NAND components.
> >
> > However, when comparing the timings in the registers, there was a large
> > difference between what I calculated by hand in the past and the values
> > configured by the drivers. The difference was in fact a 2 factor.
> >
> > For me, the issue is due to the clock configuration declared in the SAMA5D2
> > device tree: The reference clock used by the nand-controller driver is the
> > clock for its parent node, which is directly the Master Clock. And on my
> > end, what I understood when writing the clock settings for my bootloader was
> > that the reference clock was the HSMC clock, which derives from the H32MX
> > clock, which runs at half the rate of the Master Clock.
> >
> > The documentation for the SAMA5D2 is not very precise on this topic, so I
> > would like to have some feedback. Is the clock used as a reference for the
> > chip select configuration registers the Master Clock itself, or is it the
> > peripheral clock for the HSMC module ?
> >

FYI I had the same issue on the Marvell NAND controller: the actual
frequency of the controller clock was half of the "parent" clock
retrieved by clk_get_rate(), hence I needed to double the clock period
for the timings derivation in ->setup_data_interface().

If you can't get more feedback from SAMA5 people and if this works for
you, please send a patch with a nice comment.


Thanks,
Miqu?l

  reply	other threads:[~2018-10-30  9:49 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-10 17:05 Clock configuration for the SAMA5D2 NAND controller Romain Izard
2018-10-17 10:42 ` Romain Izard
2018-10-17 10:42   ` Romain Izard
2018-10-30  9:49   ` Miquel Raynal [this message]
2018-10-30  9:49     ` Miquel Raynal
2018-10-17 12:38 ` Boris Brezillon
2018-10-17 12:49   ` Romain Izard
2018-10-17 13:03     ` Boris Brezillon
2018-10-17 13:36       ` Romain Izard
2018-10-17 13:54         ` Boris Brezillon
2018-11-14 13:45 ` Tudor.Ambarus at microchip.com
2018-11-20 11:28   ` Tudor.Ambarus at microchip.com
2018-11-20 15:26     ` Romain Izard

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