* [PATCH 0/5] Make GEN macros more similar
@ 2018-11-01 8:35 Lucas De Marchi
2018-11-01 8:35 ` [PATCH 1/5] drm/i915: let IS_GEN receive 1 or 2 arguments Lucas De Marchi
` (7 more replies)
0 siblings, 8 replies; 23+ messages in thread
From: Lucas De Marchi @ 2018-11-01 8:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Jani, Rodrigo, Tvrtko (an whoever jumps in): continuing our conversation
here with the real patches so we can debate what's better looking to
the implementation.
I generated these patches with the following options:
- Let IS_GEN() receive 1 or 2 args (besides dev_priv)
and use that to compare a single gen in the first case
or a range. The idea is that IS_GEN(dev_priv, 4) can be
seen as a shortcut to IS_GEN(dev_priv, 4, 4)
- Replace IS_GEN<n> with the new macro
- Check some cases in which we could be checking a range
rather than manual comparisons
Last 2 patches is an attempt to convert cases in which we
can't use IS_GEN and we resort to INTEL_GEN(dev_priv) to
know if it's equal, greater than (gt), greater or equal (ge),
less than (lt) or less or equal (le). Actually I have mixed feelings
on converting them and maybe we should just let them as is.
Let me know what you think.
thanks
Lucas De Marchi
Lucas De Marchi (5):
drm/i915: let IS_GEN receive 1 or 2 arguments
drm/i915: replace IS_GEN<N> with IS_GEN(..., N)
drm/i915: merge gen checks to use range
drm/i915: add helper IS_GEN_* macros
RFC: drm/i915: convert a few cases to the helper IS_GEN_* macros
drivers/gpu/drm/i915/gvt/vgpu.c | 4 +-
drivers/gpu/drm/i915/i915_cmd_parser.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 42 ++++----
drivers/gpu/drm/i915/i915_drv.c | 18 ++--
drivers/gpu/drm/i915/i915_drv.h | 23 ++--
drivers/gpu/drm/i915/i915_gem.c | 12 +--
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +-
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 10 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 +-
drivers/gpu/drm/i915/i915_gem_stolen.c | 7 +-
drivers/gpu/drm/i915/i915_gem_tiling.c | 4 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 18 ++--
drivers/gpu/drm/i915/i915_irq.c | 30 +++---
drivers/gpu/drm/i915/i915_perf.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 4 +-
drivers/gpu/drm/i915/i915_suspend.c | 12 +--
drivers/gpu/drm/i915/intel_atomic.c | 2 +-
drivers/gpu/drm/i915/intel_audio.c | 2 +-
drivers/gpu/drm/i915/intel_cdclk.c | 12 +--
drivers/gpu/drm/i915/intel_crt.c | 6 +-
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 16 +--
drivers/gpu/drm/i915/intel_display.c | 116 ++++++++++-----------
drivers/gpu/drm/i915/intel_dp.c | 32 +++---
drivers/gpu/drm/i915/intel_engine_cs.c | 4 +-
drivers/gpu/drm/i915/intel_fbc.c | 24 ++---
drivers/gpu/drm/i915/intel_fifo_underrun.c | 6 +-
drivers/gpu/drm/i915/intel_guc_fw.c | 2 +-
drivers/gpu/drm/i915/intel_hangcheck.c | 2 +-
drivers/gpu/drm/i915/intel_i2c.c | 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 6 +-
drivers/gpu/drm/i915/intel_lvds.c | 4 +-
drivers/gpu/drm/i915/intel_mocs.c | 4 +-
drivers/gpu/drm/i915/intel_overlay.c | 10 +-
drivers/gpu/drm/i915/intel_panel.c | 8 +-
drivers/gpu/drm/i915/intel_pipe_crc.c | 8 +-
drivers/gpu/drm/i915/intel_pm.c | 86 +++++++--------
drivers/gpu/drm/i915/intel_psr.c | 10 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 28 ++---
drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
drivers/gpu/drm/i915/intel_sprite.c | 14 +--
drivers/gpu/drm/i915/intel_uc.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 22 ++--
drivers/gpu/drm/i915/intel_wopcm.c | 4 +-
46 files changed, 328 insertions(+), 316 deletions(-)
--
2.19.1.1.g56c4683e68
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^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 1/5] drm/i915: let IS_GEN receive 1 or 2 arguments 2018-11-01 8:35 [PATCH 0/5] Make GEN macros more similar Lucas De Marchi @ 2018-11-01 8:35 ` Lucas De Marchi 2018-11-01 8:35 ` [PATCH 2/5] drm/i915: replace IS_GEN<N> with IS_GEN(..., N) Lucas De Marchi ` (6 subsequent siblings) 7 siblings, 0 replies; 23+ messages in thread From: Lucas De Marchi @ 2018-11-01 8:35 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi By letting IS_GEN receive more than 1 argument (besides the dev_priv) we can use the same macro to check for ranges. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c9e5bab6861b..3b0bdab5a57a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2361,9 +2361,15 @@ intel_info(const struct drm_i915_private *dev_priv) GENMASK((e) - 1, (s) - 1)) /* Returns true if Gen is in inclusive range [Start, End] */ -#define IS_GEN(dev_priv, s, e) \ +#define _IS_GEN_ARG2(dev_priv, s, e) \ (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e)))) +#define _IS_GEN_ARG1(dev_priv, g) \ + (!!((dev_priv)->info.gen_mask & BIT((g) - 1))) + +#define IS_GEN(dev_priv, ...) \ + CONCATENATE(_IS_GEN_ARG, COUNT_ARGS(__VA_ARGS__))((dev_priv), ##__VA_ARGS__) + /* * Return true if revision is in range [since,until] inclusive. * -- 2.19.1.1.g56c4683e68 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 2/5] drm/i915: replace IS_GEN<N> with IS_GEN(..., N) 2018-11-01 8:35 [PATCH 0/5] Make GEN macros more similar Lucas De Marchi 2018-11-01 8:35 ` [PATCH 1/5] drm/i915: let IS_GEN receive 1 or 2 arguments Lucas De Marchi @ 2018-11-01 8:35 ` Lucas De Marchi 2018-11-01 11:17 ` Jani Nikula 2018-11-01 11:35 ` Tvrtko Ursulin 2018-11-01 8:35 ` [PATCH 3/5] drm/i915: merge gen checks to use range Lucas De Marchi ` (5 subsequent siblings) 7 siblings, 2 replies; 23+ messages in thread From: Lucas De Marchi @ 2018-11-01 8:35 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi Now that IS_GEN can accept 1 or 2 parameters, replace the use of IS_GEN<N> by passing N as argument. This was generated with: @@ expression e; @@ ( - IS_GEN2(e) + IS_GEN(e, 2) | - IS_GEN3(e) + IS_GEN(e, 3) | - IS_GEN4(e) + IS_GEN(e, 4) | - IS_GEN5(e) + IS_GEN(e, 5) | - IS_GEN6(e) + IS_GEN(e, 6) | - IS_GEN7(e) + IS_GEN(e, 7) | - IS_GEN8(e) + IS_GEN(e, 8) | - IS_GEN9(e) + IS_GEN(e, 9) | - IS_GEN10(e) + IS_GEN(e, 10) | - IS_GEN11(e) + IS_GEN(e, 11) ) Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/gvt/vgpu.c | 4 +- drivers/gpu/drm/i915/i915_cmd_parser.c | 2 +- drivers/gpu/drm/i915/i915_debugfs.c | 16 ++--- drivers/gpu/drm/i915/i915_drv.c | 18 +++--- drivers/gpu/drm/i915/i915_drv.h | 8 +-- drivers/gpu/drm/i915/i915_gem.c | 12 ++-- drivers/gpu/drm/i915/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 10 +-- drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +- drivers/gpu/drm/i915/i915_gem_stolen.c | 7 +- drivers/gpu/drm/i915/i915_gem_tiling.c | 4 +- drivers/gpu/drm/i915/i915_gpu_error.c | 18 +++--- drivers/gpu/drm/i915/i915_irq.c | 24 +++---- drivers/gpu/drm/i915/i915_perf.c | 4 +- drivers/gpu/drm/i915/i915_suspend.c | 12 ++-- drivers/gpu/drm/i915/intel_atomic.c | 2 +- drivers/gpu/drm/i915/intel_audio.c | 2 +- drivers/gpu/drm/i915/intel_cdclk.c | 10 +-- drivers/gpu/drm/i915/intel_crt.c | 6 +- drivers/gpu/drm/i915/intel_device_info.c | 16 ++--- drivers/gpu/drm/i915/intel_display.c | 74 +++++++++++----------- drivers/gpu/drm/i915/intel_dp.c | 24 +++---- drivers/gpu/drm/i915/intel_engine_cs.c | 4 +- drivers/gpu/drm/i915/intel_fbc.c | 22 +++---- drivers/gpu/drm/i915/intel_fifo_underrun.c | 6 +- drivers/gpu/drm/i915/intel_guc_fw.c | 2 +- drivers/gpu/drm/i915/intel_hangcheck.c | 2 +- drivers/gpu/drm/i915/intel_lrc.c | 4 +- drivers/gpu/drm/i915/intel_lvds.c | 4 +- drivers/gpu/drm/i915/intel_mocs.c | 2 +- drivers/gpu/drm/i915/intel_overlay.c | 10 +-- drivers/gpu/drm/i915/intel_panel.c | 8 +-- drivers/gpu/drm/i915/intel_pipe_crc.c | 8 +-- drivers/gpu/drm/i915/intel_pm.c | 60 +++++++++--------- drivers/gpu/drm/i915/intel_psr.c | 4 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 28 ++++---- drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +- drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +- drivers/gpu/drm/i915/intel_sprite.c | 6 +- drivers/gpu/drm/i915/intel_uc.c | 2 +- drivers/gpu/drm/i915/intel_uncore.c | 18 +++--- drivers/gpu/drm/i915/intel_wopcm.c | 4 +- 43 files changed, 243 insertions(+), 242 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c index c628be05fbfe..e1c860f80eb0 100644 --- a/drivers/gpu/drm/i915/gvt/vgpu.c +++ b/drivers/gpu/drm/i915/gvt/vgpu.c @@ -148,10 +148,10 @@ int intel_gvt_init_vgpu_types(struct intel_gvt *gvt) gvt->types[i].avail_instance = min(low_avail / vgpu_types[i].low_mm, high_avail / vgpu_types[i].high_mm); - if (IS_GEN8(gvt->dev_priv)) + if (IS_GEN(gvt->dev_priv, 8)) sprintf(gvt->types[i].name, "GVTg_V4_%s", vgpu_types[i].name); - else if (IS_GEN9(gvt->dev_priv)) + else if (IS_GEN(gvt->dev_priv, 9)) sprintf(gvt->types[i].name, "GVTg_V5_%s", vgpu_types[i].name); diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c index 95478db9998b..33e8eed64423 100644 --- a/drivers/gpu/drm/i915/i915_cmd_parser.c +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c @@ -865,7 +865,7 @@ void intel_engine_init_cmd_parser(struct intel_engine_cs *engine) int cmd_table_count; int ret; - if (!IS_GEN7(engine->i915)) + if (!IS_GEN(engine->i915, 7)) return; switch (engine->id) { diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 041319d48ca3..28d95f9d0b0e 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1064,7 +1064,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) intel_runtime_pm_get(dev_priv); - if (IS_GEN5(dev_priv)) { + if (IS_GEN(dev_priv, 5)) { u16 rgvswctl = I915_READ16(MEMSWCTL); u16 rgvstat = I915_READ16(MEMSTAT_ILK); @@ -1785,7 +1785,7 @@ static int i915_emon_status(struct seq_file *m, void *unused) unsigned long temp, chipset, gfx; int ret; - if (!IS_GEN5(dev_priv)) + if (!IS_GEN(dev_priv, 5)) return -ENODEV; ret = mutex_lock_interruptible(&dev->struct_mutex); @@ -2030,7 +2030,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", swizzle_string(dev_priv->mm.bit_6_swizzle_y)); - if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) { + if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) { seq_printf(m, "DDC = 0x%08x\n", I915_READ(DCC)); seq_printf(m, "DDC2 = 0x%08x\n", @@ -2115,12 +2115,12 @@ static void gen6_ppgtt_info(struct seq_file *m, struct intel_engine_cs *engine; enum intel_engine_id id; - if (IS_GEN6(dev_priv)) + if (IS_GEN(dev_priv, 6)) seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); for_each_engine(engine, dev_priv, id) { seq_printf(m, "%s\n", engine->name); - if (IS_GEN7(dev_priv)) + if (IS_GEN(dev_priv, 7)) seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(engine))); seq_printf(m, "PP_DIR_BASE: 0x%08x\n", @@ -4260,7 +4260,7 @@ i915_cache_sharing_get(void *data, u64 *val) struct drm_i915_private *dev_priv = data; u32 snpcr; - if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) + if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))) return -ENODEV; intel_runtime_pm_get(dev_priv); @@ -4280,7 +4280,7 @@ i915_cache_sharing_set(void *data, u64 val) struct drm_i915_private *dev_priv = data; u32 snpcr; - if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) + if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))) return -ENODEV; if (val > 3) @@ -4537,7 +4537,7 @@ static int i915_sseu_status(struct seq_file *m, void *unused) cherryview_sseu_device_status(dev_priv, &sseu); } else if (IS_BROADWELL(dev_priv)) { broadwell_sseu_device_status(dev_priv, &sseu); - } else if (IS_GEN9(dev_priv)) { + } else if (IS_GEN(dev_priv, 9)) { gen9_sseu_device_status(dev_priv, &sseu); } else if (INTEL_GEN(dev_priv) >= 10) { gen10_sseu_device_status(dev_priv, &sseu); diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 198d625f2871..dcfa88289630 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -131,15 +131,15 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) switch (id) { case INTEL_PCH_IBX_DEVICE_ID_TYPE: DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); - WARN_ON(!IS_GEN5(dev_priv)); + WARN_ON(!IS_GEN(dev_priv, 5)); return PCH_IBX; case INTEL_PCH_CPT_DEVICE_ID_TYPE: DRM_DEBUG_KMS("Found CougarPoint PCH\n"); - WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv)); + WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv)); return PCH_CPT; case INTEL_PCH_PPT_DEVICE_ID_TYPE: DRM_DEBUG_KMS("Found PantherPoint PCH\n"); - WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv)); + WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv)); /* PantherPoint is CPT compatible */ return PCH_CPT; case INTEL_PCH_LPT_DEVICE_ID_TYPE: @@ -216,9 +216,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv) * make an educated guess as to which PCH is really there. */ - if (IS_GEN5(dev_priv)) + if (IS_GEN(dev_priv, 5)) id = INTEL_PCH_IBX_DEVICE_ID_TYPE; - else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) + else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) id = INTEL_PCH_CPT_DEVICE_ID_TYPE; else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE; @@ -955,7 +955,7 @@ static int i915_mmio_setup(struct drm_i915_private *dev_priv) int mmio_bar; int mmio_size; - mmio_bar = IS_GEN2(dev_priv) ? 1 : 0; + mmio_bar = IS_GEN(dev_priv, 2) ? 1 : 0; /* * Before gen4, the registers and the GTT are behind different BARs. * However, from gen4 onwards, the registers and the GTT are shared @@ -1330,7 +1330,7 @@ intel_get_dram_info(struct drm_i915_private *dev_priv) /* Need to calculate bandwidth only for Gen9 */ if (IS_BROXTON(dev_priv)) ret = bxt_get_dram_info(dev_priv); - else if (IS_GEN9(dev_priv)) + else if (IS_GEN(dev_priv, 9)) ret = skl_get_dram_info(dev_priv); else ret = skl_dram_get_channels_info(dev_priv); @@ -1411,7 +1411,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) pci_set_master(pdev); /* overlay on gen2 is broken and can't address above 1G */ - if (IS_GEN2(dev_priv)) { + if (IS_GEN(dev_priv, 2)) { ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30)); if (ret) { DRM_ERROR("failed to set DMA mask\n"); @@ -1548,7 +1548,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv) acpi_video_register(); } - if (IS_GEN5(dev_priv)) + if (IS_GEN(dev_priv, 5)) intel_gpu_ips_init(dev_priv); intel_audio_init(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3b0bdab5a57a..8d22353a3da6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2539,8 +2539,8 @@ intel_info(const struct drm_i915_private *dev_priv) #define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10))) #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) -#define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv)) -#define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) +#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) +#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) #define ENGINE_MASK(id) BIT(id) #define RENDER_RING ENGINE_MASK(RCS) @@ -2561,7 +2561,7 @@ intel_info(const struct drm_i915_private *dev_priv) #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS) #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS) -#define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv) +#define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN(dev_priv, 7) #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc) #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop) @@ -2613,7 +2613,7 @@ intel_info(const struct drm_i915_private *dev_priv) /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte * rows, which changed the alignment requirements and fence programming. */ -#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \ +#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \ !(IS_I915G(dev_priv) || \ IS_I915GM(dev_priv))) #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 93d09282710d..8bc0d23bc950 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -5222,15 +5222,15 @@ void i915_gem_init_swizzling(struct drm_i915_private *dev_priv) I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | DISP_TILE_SURFACE_SWIZZLING); - if (IS_GEN5(dev_priv)) + if (IS_GEN(dev_priv, 5)) return; I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); - if (IS_GEN6(dev_priv)) + if (IS_GEN(dev_priv, 6)) I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); - else if (IS_GEN7(dev_priv)) + else if (IS_GEN(dev_priv, 7)) I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); - else if (IS_GEN8(dev_priv)) + else if (IS_GEN(dev_priv, 8)) I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); else BUG(); @@ -5252,10 +5252,10 @@ static void init_unused_rings(struct drm_i915_private *dev_priv) init_unused_ring(dev_priv, SRB1_BASE); init_unused_ring(dev_priv, SRB2_BASE); init_unused_ring(dev_priv, SRB3_BASE); - } else if (IS_GEN2(dev_priv)) { + } else if (IS_GEN(dev_priv, 2)) { init_unused_ring(dev_priv, SRB0_BASE); init_unused_ring(dev_priv, SRB1_BASE); - } else if (IS_GEN3(dev_priv)) { + } else if (IS_GEN(dev_priv, 3)) { init_unused_ring(dev_priv, PRB1_BASE); init_unused_ring(dev_priv, PRB2_BASE); } diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index b97963db0287..96cc10080465 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -311,7 +311,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915, address_mode = INTEL_LEGACY_64B_CONTEXT; desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT; - if (IS_GEN8(i915)) + if (IS_GEN(i915, 8)) desc |= GEN8_CTX_L3LLC_COHERENT; /* TODO: WaDisableLiteRestore when we start using semaphore diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 1a1c04db6c80..844bd5ad87bc 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1380,7 +1380,7 @@ eb_relocate_entry(struct i915_execbuffer *eb, * batchbuffers. */ if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && - IS_GEN6(eb->i915)) { + IS_GEN(eb->i915, 6)) { err = i915_vma_bind(target, target->obj->cache_level, PIN_GLOBAL); if (WARN_ONCE(err, @@ -1893,7 +1893,7 @@ static int i915_reset_gen7_sol_offsets(struct i915_request *rq) u32 *cs; int i; - if (!IS_GEN7(rq->i915) || rq->engine->id != RCS) { + if (!IS_GEN(rq->i915, 7) || rq->engine->id != RCS) { DRM_DEBUG("sol reset is gen7/rcs only\n"); return -EINVAL; } diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c index d548ac05ccd7..24df2e2a8fc1 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c @@ -193,9 +193,9 @@ static void fence_write(struct drm_i915_fence_reg *fence, * and explicitly managed for internal users. */ - if (IS_GEN2(fence->i915)) + if (IS_GEN(fence->i915, 2)) i830_write_fence_reg(fence, vma); - else if (IS_GEN3(fence->i915)) + else if (IS_GEN(fence->i915, 3)) i915_write_fence_reg(fence, vma); else i965_write_fence_reg(fence, vma); @@ -596,13 +596,13 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv) swizzle_y = I915_BIT_6_SWIZZLE_NONE; } } - } else if (IS_GEN5(dev_priv)) { + } else if (IS_GEN(dev_priv, 5)) { /* On Ironlake whatever DRAM config, GPU always do * same swizzling setup. */ swizzle_x = I915_BIT_6_SWIZZLE_9_10; swizzle_y = I915_BIT_6_SWIZZLE_9; - } else if (IS_GEN2(dev_priv)) { + } else if (IS_GEN(dev_priv, 2)) { /* As far as we know, the 865 doesn't have these bit 6 * swizzling issues. */ @@ -647,7 +647,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv) } /* check for L-shaped memory aka modified enhanced addressing */ - if (IS_GEN4(dev_priv) && + if (IS_GEN(dev_priv, 4) && !(I915_READ(DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) { swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index a98c29147d5e..b887fa51f801 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2195,9 +2195,9 @@ int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv) { gtt_write_workarounds(dev_priv); - if (IS_GEN6(dev_priv)) + if (IS_GEN(dev_priv, 6)) gen6_ppgtt_enable(dev_priv); - else if (IS_GEN7(dev_priv)) + else if (IS_GEN(dev_priv, 7)) gen7_ppgtt_enable(dev_priv); return 0; @@ -2279,7 +2279,7 @@ static bool needs_idle_maps(struct drm_i915_private *dev_priv) /* Query intel_iommu to see if we need the workaround. Presumably that * was loaded first. */ - return IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_vtd_active(); + return IS_GEN(dev_priv, 5) && IS_MOBILE(dev_priv) && intel_vtd_active(); } static void gen6_check_faults(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c index f29a7ff7c362..2f756a97689a 100644 --- a/drivers/gpu/drm/i915/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c @@ -102,7 +102,7 @@ static int i915_adjust_stolen(struct drm_i915_private *dev_priv, resource_size_t ggtt_start; ggtt_start = I915_READ(PGTBL_CTL); - if (IS_GEN4(dev_priv)) + if (IS_GEN(dev_priv, 4)) ggtt_start = (ggtt_start & PGTBL_ADDRESS_LO_MASK) | (ggtt_start & PGTBL_ADDRESS_HI_MASK) << 28; else @@ -156,7 +156,7 @@ static int i915_adjust_stolen(struct drm_i915_private *dev_priv, * GEN3 firmware likes to smash pci bridges into the stolen * range. Apparently this works. */ - if (r == NULL && !IS_GEN3(dev_priv)) { + if (r == NULL && !IS_GEN(dev_priv, 3)) { DRM_ERROR("conflict detected with stolen region: %pR\n", dsm); @@ -194,7 +194,8 @@ static void g4x_get_stolen_reserved(struct drm_i915_private *dev_priv, * Whether ILK really reuses the ELK register for this is unclear. * Let's see if we catch anyone with this supposedly enabled on ILK. */ - WARN(IS_GEN5(dev_priv), "ILK stolen reserved found? 0x%08x\n", reg_val); + WARN(IS_GEN(dev_priv, 5), "ILK stolen reserved found? 0x%08x\n", + reg_val); if (!(reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK)) return; diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index d9dc9df523b5..39319ff1679c 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -87,7 +87,7 @@ u32 i915_gem_fence_size(struct drm_i915_private *i915, } /* Previous chips need a power-of-two fence region when tiling */ - if (IS_GEN3(i915)) + if (IS_GEN(i915, 3)) ggtt_size = 1024*1024; else ggtt_size = 512*1024; @@ -162,7 +162,7 @@ i915_tiling_ok(struct drm_i915_gem_object *obj, return false; } - if (IS_GEN2(i915) || + if (IS_GEN(i915, 2) || (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915))) tile_width = 128; else diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index c8d8f79688a8..c9f8aa47005a 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -720,7 +720,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); } - if (IS_GEN7(dev_priv)) + if (IS_GEN(dev_priv, 7)) err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); for (i = 0; i < ARRAY_SIZE(error->engine); i++) { @@ -1234,7 +1234,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error, if (!HWS_NEEDS_PHYSICAL(dev_priv)) { i915_reg_t mmio; - if (IS_GEN7(dev_priv)) { + if (IS_GEN(dev_priv, 7)) { switch (engine->id) { default: case RCS: @@ -1250,7 +1250,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error, mmio = VEBOX_HWS_PGA_GEN7; break; } - } else if (IS_GEN6(engine->i915)) { + } else if (IS_GEN(engine->i915, 6)) { mmio = RING_HWS_PGA_GEN6(engine->mmio_base); } else { /* XXX: gen8 returns to sanity */ @@ -1272,10 +1272,10 @@ static void error_record_engine_registers(struct i915_gpu_state *error, ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine)); - if (IS_GEN6(dev_priv)) + if (IS_GEN(dev_priv, 6)) ee->vm_info.pp_dir_base = I915_READ(RING_PP_DIR_BASE_READ(engine)); - else if (IS_GEN7(dev_priv)) + else if (IS_GEN(dev_priv, 7)) ee->vm_info.pp_dir_base = I915_READ(RING_PP_DIR_BASE(engine)); else if (INTEL_GEN(dev_priv) >= 8) @@ -1645,7 +1645,7 @@ static void capture_reg_state(struct i915_gpu_state *error) error->forcewake = I915_READ_FW(FORCEWAKE_VLV); } - if (IS_GEN7(dev_priv)) + if (IS_GEN(dev_priv, 7)) error->err_int = I915_READ(GEN7_ERR_INT); if (INTEL_GEN(dev_priv) >= 8) { @@ -1653,7 +1653,7 @@ static void capture_reg_state(struct i915_gpu_state *error) error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); } - if (IS_GEN6(dev_priv)) { + if (IS_GEN(dev_priv, 6)) { error->forcewake = I915_READ_FW(FORCEWAKE); error->gab_ctl = I915_READ(GAB_CTL); error->gfx_mode = I915_READ(GFX_MODE); @@ -1673,7 +1673,7 @@ static void capture_reg_state(struct i915_gpu_state *error) error->ccid = I915_READ(CCID); /* 3: Feature specific registers */ - if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { + if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) { error->gam_ecochk = I915_READ(GAM_ECOCHK); error->gac_eco = I915_READ(GAC_ECO_BITS); } @@ -1697,7 +1697,7 @@ static void capture_reg_state(struct i915_gpu_state *error) error->ier = I915_READ(DEIER); error->gtier[0] = I915_READ(GTIER); error->ngtier = 1; - } else if (IS_GEN2(dev_priv)) { + } else if (IS_GEN(dev_priv, 2)) { error->ier = I915_READ16(IER); } else if (!IS_VALLEYVIEW(dev_priv)) { error->ier = I915_READ(IER); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 5d1f53723388..068cccb3aba8 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -950,7 +950,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) if (mode->flags & DRM_MODE_FLAG_INTERLACE) vtotal /= 2; - if (IS_GEN2(dev_priv)) + if (IS_GEN(dev_priv, 2)) position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; else position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; @@ -1030,7 +1030,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, if (stime) *stime = ktime_get(); - if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { + if (IS_GEN(dev_priv, 2) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { /* No obvious pixelcount register. Only query vertical * scanout position from Display scan line register. */ @@ -1090,7 +1090,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, else position += vtotal - vbl_end; - if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { + if (IS_GEN(dev_priv, 2) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { *vpos = position; *hpos = 0; } else { @@ -2547,7 +2547,7 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv, I915_WRITE(SDEIIR, pch_iir); } - if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT) + if (IS_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT) ironlake_rps_change_irq_handler(dev_priv); } @@ -3243,7 +3243,7 @@ void i915_clear_error_registers(struct drm_i915_private *dev_priv) { u32 eir; - if (!IS_GEN2(dev_priv)) + if (!IS_GEN(dev_priv, 2)) I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER)); if (INTEL_GEN(dev_priv) < 4) @@ -3586,11 +3586,11 @@ static void ironlake_irq_reset(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); - if (IS_GEN5(dev_priv)) + if (IS_GEN(dev_priv, 5)) I915_WRITE(HWSTAM, 0xffffffff); GEN3_IRQ_RESET(DE); - if (IS_GEN7(dev_priv)) + if (IS_GEN(dev_priv, 7)) I915_WRITE(GEN7_ERR_INT, 0xffffffff); if (IS_HASWELL(dev_priv)) { @@ -4042,7 +4042,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) } gt_irqs |= GT_RENDER_USER_INTERRUPT; - if (IS_GEN5(dev_priv)) { + if (IS_GEN(dev_priv, 5)) { gt_irqs |= ILK_BSD_USER_INTERRUPT; } else { gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; @@ -4833,7 +4833,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) if (INTEL_GEN(dev_priv) >= 8) rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; - if (IS_GEN2(dev_priv)) { + if (IS_GEN(dev_priv, 2)) { /* Gen2 doesn't have a hardware frame counter */ dev->max_vblank_count = 0; } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { @@ -4849,7 +4849,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) * Gen2 doesn't have a hardware frame counter and so depends on * vblank interrupts to produce sane vblank seuquence numbers. */ - if (!IS_GEN2(dev_priv)) + if (!IS_GEN(dev_priv, 2)) dev->vblank_disable_immediate = true; /* Most platforms treat the display irq block as an always-on @@ -4914,14 +4914,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv) dev->driver->disable_vblank = ironlake_disable_vblank; dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; } else { - if (IS_GEN2(dev_priv)) { + if (IS_GEN(dev_priv, 2)) { dev->driver->irq_preinstall = i8xx_irq_reset; dev->driver->irq_postinstall = i8xx_irq_postinstall; dev->driver->irq_handler = i8xx_irq_handler; dev->driver->irq_uninstall = i8xx_irq_reset; dev->driver->enable_vblank = i8xx_enable_vblank; dev->driver->disable_vblank = i8xx_disable_vblank; - } else if (IS_GEN3(dev_priv)) { + } else if (IS_GEN(dev_priv, 3)) { dev->driver->irq_preinstall = i915_irq_reset; dev->driver->irq_postinstall = i915_irq_postinstall; dev->driver->irq_uninstall = i915_irq_reset; diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 2c2b63be7a6c..92daddf79cb0 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -3449,7 +3449,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.ops.read = gen8_oa_read; dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read; - if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv)) { + if (IS_GEN(dev_priv, 8) || IS_GEN(dev_priv, 9)) { dev_priv->perf.oa.ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr; dev_priv->perf.oa.ops.is_valid_mux_reg = @@ -3465,7 +3465,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set; dev_priv->perf.oa.ops.disable_metric_set = gen8_disable_metric_set; - if (IS_GEN8(dev_priv)) { + if (IS_GEN(dev_priv, 8)) { dev_priv->perf.oa.ctx_oactxctrl_offset = 0x120; dev_priv->perf.oa.ctx_flexeu0_offset = 0x2ce; diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 8f3aa4dc0c98..f40ba5e429e0 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -65,7 +65,7 @@ int i915_save_state(struct drm_i915_private *dev_priv) i915_save_display(dev_priv); - if (IS_GEN4(dev_priv)) + if (IS_GEN(dev_priv, 4)) pci_read_config_word(pdev, GCDGMBUS, &dev_priv->regfile.saveGCDGMBUS); @@ -77,14 +77,14 @@ int i915_save_state(struct drm_i915_private *dev_priv) dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); /* Scratch space */ - if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) { + if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) { for (i = 0; i < 7; i++) { dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i)); dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); } for (i = 0; i < 3; i++) dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i)); - } else if (IS_GEN2(dev_priv)) { + } else if (IS_GEN(dev_priv, 2)) { for (i = 0; i < 7; i++) dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); } else if (HAS_GMCH_DISPLAY(dev_priv)) { @@ -108,7 +108,7 @@ int i915_restore_state(struct drm_i915_private *dev_priv) mutex_lock(&dev_priv->drm.struct_mutex); - if (IS_GEN4(dev_priv)) + if (IS_GEN(dev_priv, 4)) pci_write_config_word(pdev, GCDGMBUS, dev_priv->regfile.saveGCDGMBUS); i915_restore_display(dev_priv); @@ -122,14 +122,14 @@ int i915_restore_state(struct drm_i915_private *dev_priv) I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000); /* Scratch space */ - if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) { + if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) { for (i = 0; i < 7; i++) { I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]); I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); } for (i = 0; i < 3; i++) I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]); - } else if (IS_GEN2(dev_priv)) { + } else if (IS_GEN(dev_priv, 2)) { for (i = 0; i < 7; i++) I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); } else if (HAS_GMCH_DISPLAY(dev_priv)) { diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index a5a2c8fe58a7..c1d5248b3a8b 100644 --- a/drivers/gpu/drm/i915/intel_atomic.c +++ b/drivers/gpu/drm/i915/intel_atomic.c @@ -232,7 +232,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta if (plane_state && plane_state->base.fb && plane_state->base.fb->format->is_yuv && plane_state->base.fb->format->num_planes > 1) { - if (IS_GEN9(dev_priv) && + if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) { mode = SKL_PS_SCALER_MODE_NV12; } else if (icl_is_hdr_plane(to_intel_plane(plane_state->base.plane))) { diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c index ccd88da20a14..37d68a75dda5 100644 --- a/drivers/gpu/drm/i915/intel_audio.c +++ b/drivers/gpu/drm/i915/intel_audio.c @@ -758,7 +758,7 @@ static void i915_audio_component_codec_wake_override(struct device *kdev, struct drm_i915_private *dev_priv = kdev_to_i915(kdev); u32 tmp; - if (!IS_GEN9(dev_priv)) + if (!IS_GEN(dev_priv, 9)) return; i915_audio_component_get_power(kdev); diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index 8d74276029e6..b9a3a2312686 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -2140,7 +2140,7 @@ static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv, { if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) return DIV_ROUND_UP(pixel_rate, 2); - else if (IS_GEN9(dev_priv) || + else if (IS_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) return pixel_rate; else if (IS_CHERRYVIEW(dev_priv)) @@ -2176,7 +2176,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { /* Display WA #1145: glk,cnl */ min_cdclk = max(316800, min_cdclk); - } else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) { + } else if (IS_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv)) { /* Display WA #1144: skl,bxt */ min_cdclk = max(432000, min_cdclk); } @@ -2537,7 +2537,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) return 2 * max_cdclk_freq; - else if (IS_GEN9(dev_priv) || + else if (IS_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) return max_cdclk_freq; else if (IS_CHERRYVIEW(dev_priv)) @@ -2806,9 +2806,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) dev_priv->display.get_cdclk = hsw_get_cdclk; else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv->display.get_cdclk = vlv_get_cdclk; - else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) + else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; - else if (IS_GEN5(dev_priv)) + else if (IS_GEN(dev_priv, 5)) dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk; else if (IS_GM45(dev_priv)) dev_priv->display.get_cdclk = gm45_get_cdclk; diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 68f2fb89ece3..bf4fd739b68c 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -322,7 +322,7 @@ intel_crt_mode_valid(struct drm_connector *connector, * DAC limit supposedly 355 MHz. */ max_clock = 270000; - else if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) + else if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) max_clock = 400000; else max_clock = 350000; @@ -666,7 +666,7 @@ intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe) /* Set the border color to purple. */ I915_WRITE(bclrpat_reg, 0x500050); - if (!IS_GEN2(dev_priv)) { + if (!IS_GEN(dev_priv, 2)) { uint32_t pipeconf = I915_READ(pipeconf_reg); I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); POSTING_READ(pipeconf_reg); @@ -981,7 +981,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv) else crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); - if (IS_GEN2(dev_priv)) + if (IS_GEN(dev_priv, 2)) connector->interlace_allowed = 0; else connector->interlace_allowed = 1; diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 89ed3a84a4fa..873f37b7b796 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -744,7 +744,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) if (INTEL_GEN(dev_priv) >= 10) { for_each_pipe(dev_priv, pipe) info->num_scalers[pipe] = 2; - } else if (IS_GEN9(dev_priv)) { + } else if (IS_GEN(dev_priv, 9)) { info->num_scalers[PIPE_A] = 2; info->num_scalers[PIPE_B] = 2; info->num_scalers[PIPE_C] = 1; @@ -752,10 +752,10 @@ void intel_device_info_runtime_init(struct intel_device_info *info) BUILD_BUG_ON(I915_NUM_ENGINES > BITS_PER_TYPE(intel_ring_mask_t)); - if (IS_GEN11(dev_priv)) + if (IS_GEN(dev_priv, 11)) for_each_pipe(dev_priv, pipe) info->num_sprites[pipe] = 6; - else if (IS_GEN10(dev_priv) || IS_GEMINILAKE(dev_priv)) + else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv)) for_each_pipe(dev_priv, pipe) info->num_sprites[pipe] = 3; else if (IS_BROXTON(dev_priv)) { @@ -783,7 +783,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) DRM_INFO("Display disabled (module parameter)\n"); info->num_pipes = 0; } else if (info->num_pipes > 0 && - (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) && + (IS_GEN(dev_priv, 7) || IS_GEN(dev_priv, 8)) && HAS_PCH_SPLIT(dev_priv)) { u32 fuse_strap = I915_READ(FUSE_STRAP); u32 sfuse_strap = I915_READ(SFUSE_STRAP); @@ -807,7 +807,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) DRM_INFO("PipeC fused off\n"); info->num_pipes -= 1; } - } else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) { + } else if (info->num_pipes > 0 && IS_GEN(dev_priv, 9)) { u32 dfsm = I915_READ(SKL_DFSM); u8 disabled_mask = 0; bool invalid; @@ -847,14 +847,14 @@ void intel_device_info_runtime_init(struct intel_device_info *info) cherryview_sseu_info_init(dev_priv); else if (IS_BROADWELL(dev_priv)) broadwell_sseu_info_init(dev_priv); - else if (IS_GEN9(dev_priv)) + else if (IS_GEN(dev_priv, 9)) gen9_sseu_info_init(dev_priv); - else if (IS_GEN10(dev_priv)) + else if (IS_GEN(dev_priv, 10)) gen10_sseu_info_init(dev_priv); else if (INTEL_GEN(dev_priv) >= 11) gen11_sseu_info_init(dev_priv); - if (IS_GEN6(dev_priv) && intel_vtd_active()) { + if (IS_GEN(dev_priv, 6) && intel_vtd_active()) { DRM_INFO("Disabling ppGTT for VT-d support\n"); info->ppgtt = INTEL_PPGTT_NONE; } diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c3cadc09f859..84c432cbdf5b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -999,7 +999,7 @@ static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, u32 line1, line2; u32 line_mask; - if (IS_GEN2(dev_priv)) + if (IS_GEN(dev_priv, 2)) line_mask = DSL_LINEMASK_GEN2; else line_mask = DSL_LINEMASK_GEN3; @@ -1125,7 +1125,7 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, u32 val; /* ILK FDI PLL is always enabled */ - if (IS_GEN5(dev_priv)) + if (IS_GEN(dev_priv, 5)) return; /* On Haswell, DDI ports are responsible for the FDI PLL setup */ @@ -1864,7 +1864,7 @@ static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state) static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) { - return IS_GEN2(dev_priv) ? 2048 : 4096; + return IS_GEN(dev_priv, 2) ? 2048 : 4096; } static unsigned int @@ -1877,7 +1877,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) case DRM_FORMAT_MOD_LINEAR: return cpp; case I915_FORMAT_MOD_X_TILED: - if (IS_GEN2(dev_priv)) + if (IS_GEN(dev_priv, 2)) return 128; else return 512; @@ -1886,7 +1886,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) return 128; /* fall through */ case I915_FORMAT_MOD_Y_TILED: - if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) + if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv)) return 128; else return 512; @@ -3190,8 +3190,8 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE; - if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) || - IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) + if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) || + IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) @@ -4107,7 +4107,7 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, temp = I915_READ(reg); temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_2; - if (IS_GEN6(dev_priv)) { + if (IS_GEN(dev_priv, 6)) { temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; /* SNB-B */ temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; @@ -4874,10 +4874,10 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, /* range checks */ if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || - (IS_GEN11(dev_priv) && + (IS_GEN(dev_priv, 11) && (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H || dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) || - (!IS_GEN11(dev_priv) && + (!IS_GEN(dev_priv, 11) && (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) { DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " @@ -5161,7 +5161,7 @@ intel_post_enable_primary(struct drm_crtc *crtc, * FIXME: Need to fix the logic to work when we turn off all planes * but leave the pipe running. */ - if (IS_GEN2(dev_priv)) + if (IS_GEN(dev_priv, 2)) intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); /* Underruns don't always raise interrupts, so check manually. */ @@ -5182,7 +5182,7 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) * Gen2 reports pipe underruns whenever all planes are disabled. * So disable underrun reporting before all the planes get disabled. */ - if (IS_GEN2(dev_priv)) + if (IS_GEN(dev_priv, 2)) intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); hsw_disable_ips(to_intel_crtc_state(crtc->state)); @@ -5242,7 +5242,7 @@ static bool needs_nv12_wa(struct drm_i915_private *dev_priv, if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) return false; - if ((IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) || + if ((IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) || IS_CANNONLAKE(dev_priv)) return true; @@ -5317,7 +5317,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, * Gen2 reports pipe underruns whenever all planes are disabled. * So disable underrun reporting before all the planes get disabled. */ - if (IS_GEN2(dev_priv) && old_primary_state->visible && + if (IS_GEN(dev_priv, 2) && old_primary_state->visible && (modeset || !new_primary_state->base.visible)) intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); } @@ -6108,7 +6108,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, intel_crtc->active = true; - if (!IS_GEN2(dev_priv)) + if (!IS_GEN(dev_priv, 2)) intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); intel_encoders_pre_enable(crtc, pipe_config, old_state); @@ -6160,7 +6160,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, * On gen2 planes are double buffered but the pipe isn't, so we must * wait for planes to fully turn off before disabling the pipe. */ - if (IS_GEN2(dev_priv)) + if (IS_GEN(dev_priv, 2)) intel_wait_for_vblank(dev_priv, pipe); intel_encoders_disable(crtc, old_crtc_state, old_state); @@ -6185,7 +6185,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); - if (!IS_GEN2(dev_priv)) + if (!IS_GEN(dev_priv, 2)) intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); if (!dev_priv->display.initial_watermarks) @@ -6789,7 +6789,7 @@ static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv, * Strictly speaking some registers are available before * gen7, but we only support DRRS on gen7+ */ - return IS_GEN7(dev_priv) || IS_CHERRYVIEW(dev_priv); + return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv); } static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state, @@ -8896,7 +8896,7 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc, /* We currently do not free assignements of panel fitters on * ivb/hsw (since we don't use the higher upscaling modes which * differentiates them) so just WARN about this case for now. */ - if (IS_GEN7(dev_priv)) { + if (IS_GEN(dev_priv, 7)) { WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); } @@ -9858,7 +9858,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); u32 cntl = 0; - if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) + if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) cntl |= MCURSOR_TRICKLE_FEED_DISABLE; if (INTEL_GEN(dev_priv) <= 10) { @@ -10328,7 +10328,7 @@ static int i9xx_pll_refclk(struct drm_device *dev, return dev_priv->vbt.lvds_ssc_freq; else if (HAS_PCH_SPLIT(dev_priv)) return 120000; - else if (!IS_GEN2(dev_priv)) + else if (!IS_GEN(dev_priv, 2)) return 96000; else return 48000; @@ -10361,7 +10361,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc, clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; } - if (!IS_GEN2(dev_priv)) { + if (!IS_GEN(dev_priv, 2)) { if (IS_PINEVIEW(dev_priv)) clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); @@ -10677,7 +10677,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat * the w/a on all three platforms. */ if (plane->id == PLANE_SPRITE0 && - (IS_GEN5(dev_priv) || IS_GEN6(dev_priv) || + (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) && (turn_on || (!needs_scaling(old_plane_state) && needs_scaling(to_intel_plane_state(plane_state))))) @@ -12223,7 +12223,7 @@ static void update_scanline_offset(const struct intel_crtc_state *crtc_state) * However if queried just before the start of vblank we'll get an * answer that's slightly in the future. */ - if (IS_GEN2(dev_priv)) { + if (IS_GEN(dev_priv, 2)) { const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; int vtotal; @@ -13427,7 +13427,7 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - if (!IS_GEN2(dev_priv)) + if (!IS_GEN(dev_priv, 2)) intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); if (crtc_state->has_pch_encoder) { @@ -14034,7 +14034,7 @@ static bool has_edp_a(struct drm_i915_private *dev_priv) if ((I915_READ(DP_A) & DP_DETECTED) == 0) return false; - if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) + if (IS_GEN(dev_priv, 5) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) return false; return true; @@ -14245,7 +14245,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) } vlv_dsi_init(dev_priv); - } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) { + } else if (!IS_GEN(dev_priv, 2) && !IS_PINEVIEW(dev_priv)) { bool found = false; if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { @@ -14279,7 +14279,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) intel_dp_init(dev_priv, DP_D, PORT_D); - } else if (IS_GEN2(dev_priv)) + } else if (IS_GEN(dev_priv, 2)) intel_dvo_init(dev_priv); if (SUPPORTS_TV(dev_priv)) @@ -14566,7 +14566,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, * require the entire fb to accommodate that to avoid * potential runtime errors at plane configuration time. */ - if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 && + if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 && is_ccs_modifier(fb->modifier)) stride_alignment *= 4; @@ -14771,7 +14771,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; dev_priv->display.crtc_enable = i9xx_crtc_enable; dev_priv->display.crtc_disable = i9xx_crtc_disable; - } else if (!IS_GEN2(dev_priv)) { + } else if (!IS_GEN(dev_priv, 2)) { dev_priv->display.get_pipe_config = i9xx_get_pipe_config; dev_priv->display.get_initial_plane_config = i9xx_get_initial_plane_config; @@ -14787,9 +14787,9 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) dev_priv->display.crtc_disable = i9xx_crtc_disable; } - if (IS_GEN5(dev_priv)) { + if (IS_GEN(dev_priv, 5)) { dev_priv->display.fdi_link_train = ironlake_fdi_link_train; - } else if (IS_GEN6(dev_priv)) { + } else if (IS_GEN(dev_priv, 6)) { dev_priv->display.fdi_link_train = gen6_fdi_link_train; } else if (IS_IVYBRIDGE(dev_priv)) { /* FIXME: detect B0+ stepping and use auto training */ @@ -14921,12 +14921,12 @@ static void sanitize_watermarks(struct drm_device *dev) static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv) { - if (IS_GEN5(dev_priv)) { + if (IS_GEN(dev_priv, 5)) { u32 fdi_pll_clk = I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK; dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000; - } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) { + } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) { dev_priv->fdi_pll_freq = 270000; } else { return; @@ -15032,10 +15032,10 @@ int intel_modeset_init(struct drm_device *dev) } /* maximum framebuffer dimensions */ - if (IS_GEN2(dev_priv)) { + if (IS_GEN(dev_priv, 2)) { dev->mode_config.max_width = 2048; dev->mode_config.max_height = 2048; - } else if (IS_GEN3(dev_priv)) { + } else if (IS_GEN(dev_priv, 3)) { dev->mode_config.max_width = 4096; dev->mode_config.max_height = 4096; } else { @@ -15046,7 +15046,7 @@ int intel_modeset_init(struct drm_device *dev) if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512; dev->mode_config.cursor_height = 1023; - } else if (IS_GEN2(dev_priv)) { + } else if (IS_GEN(dev_priv, 2)) { dev->mode_config.cursor_width = 64; dev->mode_config.cursor_height = 64; } else { diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 6b37d66194a3..0de05dda4705 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -455,7 +455,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) if (INTEL_GEN(dev_priv) >= 10) { source_rates = cnl_rates; size = ARRAY_SIZE(cnl_rates); - if (IS_GEN10(dev_priv)) + if (IS_GEN(dev_priv, 10)) max_rate = cnl_max_source_rate(intel_dp); else max_rate = icl_max_source_rate(intel_dp); @@ -1206,7 +1206,7 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp, to_i915(intel_dig_port->base.base.dev); uint32_t precharge, timeout; - if (IS_GEN6(dev_priv)) + if (IS_GEN(dev_priv, 6)) precharge = 3; else precharge = 5; @@ -2555,7 +2555,7 @@ static void edp_panel_on(struct intel_dp *intel_dp) pp_ctrl_reg = _pp_ctrl_reg(intel_dp); pp = ironlake_get_pp_control(intel_dp); - if (IS_GEN5(dev_priv)) { + if (IS_GEN(dev_priv, 5)) { /* ILK workaround: disable reset around power sequence */ pp &= ~PANEL_POWER_RESET; I915_WRITE(pp_ctrl_reg, pp); @@ -2563,7 +2563,7 @@ static void edp_panel_on(struct intel_dp *intel_dp) } pp |= PANEL_POWER_ON; - if (!IS_GEN5(dev_priv)) + if (!IS_GEN(dev_priv, 5)) pp |= PANEL_POWER_RESET; I915_WRITE(pp_ctrl_reg, pp); @@ -2572,7 +2572,7 @@ static void edp_panel_on(struct intel_dp *intel_dp) wait_panel_on(intel_dp); intel_dp->last_power_on = jiffies; - if (IS_GEN5(dev_priv)) { + if (IS_GEN(dev_priv, 5)) { pp |= PANEL_POWER_RESET; /* restore panel reset bit */ I915_WRITE(pp_ctrl_reg, pp); POSTING_READ(pp_ctrl_reg); @@ -2800,7 +2800,7 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp, * 1. Wait for the start of vertical blank on the enabled pipe going to FDI * 2. Program DP PLL enable */ - if (IS_GEN5(dev_priv)) + if (IS_GEN(dev_priv, 5)) intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); intel_dp->DP |= DP_PLL_ENABLE; @@ -3802,7 +3802,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp) } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { signal_levels = ivb_cpu_edp_signal_levels(train_set); mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; - } else if (IS_GEN6(dev_priv) && port == PORT_A) { + } else if (IS_GEN(dev_priv, 6) && port == PORT_A) { signal_levels = snb_cpu_edp_signal_levels(train_set); mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; } else { @@ -5040,17 +5040,17 @@ bool intel_digital_port_connected(struct intel_encoder *encoder) if (INTEL_GEN(dev_priv) >= 11) return icl_digital_port_connected(encoder); - else if (IS_GEN10(dev_priv) || IS_GEN9_BC(dev_priv)) + else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) return spt_digital_port_connected(encoder); else if (IS_GEN9_LP(dev_priv)) return bxt_digital_port_connected(encoder); - else if (IS_GEN8(dev_priv)) + else if (IS_GEN(dev_priv, 8)) return bdw_digital_port_connected(encoder); - else if (IS_GEN7(dev_priv)) + else if (IS_GEN(dev_priv, 7)) return ivb_digital_port_connected(encoder); - else if (IS_GEN6(dev_priv)) + else if (IS_GEN(dev_priv, 6)) return snb_digital_port_connected(encoder); - else if (IS_GEN5(dev_priv)) + else if (IS_GEN(dev_priv, 5)) return ilk_digital_port_connected(encoder); MISSING_CASE(INTEL_GEN(dev_priv)); diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index bc147d9e6c92..7642f6634f7b 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -438,7 +438,7 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno) * the semaphore value, then when the seqno moves backwards all * future waits will complete instantly (causing rendering corruption). */ - if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { + if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) { I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); if (HAS_VEBOX(dev_priv)) @@ -812,7 +812,7 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv) u32 slice = fls(sseu->slice_mask); u32 subslice = fls(sseu->subslice_mask[slice]); - if (IS_GEN10(dev_priv)) + if (IS_GEN(dev_priv, 10)) mcr_s_ss_select = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); else if (INTEL_GEN(dev_priv) >= 11) diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 14cbaf4a0e93..92ecaa8cd672 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -84,7 +84,7 @@ static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv, int lines; intel_fbc_get_plane_source_size(cache, NULL, &lines); - if (IS_GEN7(dev_priv)) + if (IS_GEN(dev_priv, 7)) lines = min(lines, 2048); else if (INTEL_GEN(dev_priv) >= 8) lines = min(lines, 2560); @@ -127,7 +127,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) cfb_pitch = params->fb.stride; /* FBC_CTL wants 32B or 64B units */ - if (IS_GEN2(dev_priv)) + if (IS_GEN(dev_priv, 2)) cfb_pitch = (cfb_pitch / 32) - 1; else cfb_pitch = (cfb_pitch / 64) - 1; @@ -136,7 +136,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) I915_WRITE(FBC_TAG(i), 0); - if (IS_GEN4(dev_priv)) { + if (IS_GEN(dev_priv, 4)) { u32 fbc_ctl2; /* Set it up... */ @@ -233,9 +233,9 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv) if (params->flags & PLANE_HAS_FENCE) { dpfc_ctl |= DPFC_CTL_FENCE_EN; - if (IS_GEN5(dev_priv)) + if (IS_GEN(dev_priv, 5)) dpfc_ctl |= params->vma->fence->id; - if (IS_GEN6(dev_priv)) { + if (IS_GEN(dev_priv, 6)) { I915_WRITE(SNB_DPFC_CTL_SA, SNB_CPU_FENCE_ENABLE | params->vma->fence->id); @@ -243,7 +243,7 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv) params->crtc.fence_y_offset); } } else { - if (IS_GEN6(dev_priv)) { + if (IS_GEN(dev_priv, 6)) { I915_WRITE(SNB_DPFC_CTL_SA, 0); I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0); } @@ -282,7 +282,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) int threshold = dev_priv->fbc.threshold; /* Display WA #0529: skl, kbl, bxt. */ - if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) { + if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) { u32 val = I915_READ(CHICKEN_MISC_4); val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK); @@ -581,10 +581,10 @@ static bool stride_is_valid(struct drm_i915_private *dev_priv, if (stride < 512) return false; - if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv)) + if (IS_GEN(dev_priv, 2) || IS_GEN(dev_priv, 3)) return stride == 4096 || stride == 8192; - if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048) + if (IS_GEN(dev_priv, 4) && !IS_G4X(dev_priv) && stride < 2048) return false; if (stride > 16384) @@ -603,7 +603,7 @@ static bool pixel_format_is_valid(struct drm_i915_private *dev_priv, case DRM_FORMAT_XRGB1555: case DRM_FORMAT_RGB565: /* 16bpp not supported on gen2 */ - if (IS_GEN2(dev_priv)) + if (IS_GEN(dev_priv, 2)) return false; /* WaFbcOnly1to1Ratio:ctg */ if (IS_G4X(dev_priv)) @@ -839,7 +839,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc, params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache); - if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) + if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) params->gen9_wa_cfb_stride = DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->threshold) * 8; } diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c index 77c123cc8817..ff2743ccbece 100644 --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c @@ -260,9 +260,9 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, if (HAS_GMCH_DISPLAY(dev_priv)) i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); - else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) + else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) ironlake_set_fifo_underrun_reporting(dev, pipe, enable); - else if (IS_GEN7(dev_priv)) + else if (IS_GEN(dev_priv, 7)) ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); else if (INTEL_GEN(dev_priv) >= 8) broadwell_set_fifo_underrun_reporting(dev, pipe, enable); @@ -423,7 +423,7 @@ void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv) if (HAS_GMCH_DISPLAY(dev_priv)) i9xx_check_fifo_underruns(crtc); - else if (IS_GEN7(dev_priv)) + else if (IS_GEN(dev_priv, 7)) ivybridge_check_fifo_underruns(crtc); } diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c index ae8e103a2c4d..1d0bc1cf00e3 100644 --- a/drivers/gpu/drm/i915/intel_guc_fw.c +++ b/drivers/gpu/drm/i915/intel_guc_fw.c @@ -114,7 +114,7 @@ static void guc_prepare_xfer(struct intel_guc *guc) else I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE); - if (IS_GEN9(dev_priv)) { + if (IS_GEN(dev_priv, 9)) { /* DOP Clock Gating Enable for GuC clocks */ I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE | I915_READ(GEN7_MISCCPCTL))); diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c index e26d05a46451..10e4b7b03df0 100644 --- a/drivers/gpu/drm/i915/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/intel_hangcheck.c @@ -236,7 +236,7 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd) if (ha != ENGINE_DEAD) return ha; - if (IS_GEN2(dev_priv)) + if (IS_GEN(dev_priv, 2)) return ENGINE_DEAD; /* Is the chip hanging on a WAIT_FOR_EVENT? diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 22b57b8926fc..5f0e9ba780b7 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1990,7 +1990,7 @@ static int gen8_emit_flush_render(struct i915_request *request, * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL * pipe control. */ - if (IS_GEN9(request->i915)) + if (IS_GEN(request->i915, 9)) vf_flush_wa = true; /* WaForGAMHang:kbl */ @@ -2368,7 +2368,7 @@ make_rpcs(struct drm_i915_private *dev_priv) * subslices are enabled, or a count between one and four on the first * slice. */ - if (IS_GEN11(dev_priv) && slices == 1 && subslices >= 4) { + if (IS_GEN(dev_priv, 11) && slices == 1 && subslices >= 4) { GEM_BUG_ON(subslices & 1); subslice_pg = false; diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index e6c5d985ea0a..b85e195f7c8a 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -279,7 +279,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder, * special lvds dither control bit on pch-split platforms, dithering is * only controlled through the PIPECONF reg. */ - if (IS_GEN4(dev_priv)) { + if (IS_GEN(dev_priv, 4)) { /* * Bspec wording suggests that LVDS port dithering only exists * for 18bpp panels. @@ -919,7 +919,7 @@ void intel_lvds_init(struct drm_i915_private *dev_priv) intel_encoder->cloneable = 0; if (HAS_PCH_SPLIT(dev_priv)) intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); - else if (IS_GEN4(dev_priv)) + else if (IS_GEN(dev_priv, 4)) intel_encoder->crtc_mask = (1 << 0) | (1 << 1); else intel_encoder->crtc_mask = (1 << 1); diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c index 77e9871a8c9a..e976c5ce5479 100644 --- a/drivers/gpu/drm/i915/intel_mocs.c +++ b/drivers/gpu/drm/i915/intel_mocs.c @@ -193,7 +193,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv, } /* WaDisableSkipCaching:skl,bxt,kbl,glk */ - if (IS_GEN9(dev_priv)) { + if (IS_GEN(dev_priv, 9)) { int i; for (i = 0; i < table->size; i++) diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c index 72eb7e48e8bc..186969243845 100644 --- a/drivers/gpu/drm/i915/intel_overlay.c +++ b/drivers/gpu/drm/i915/intel_overlay.c @@ -541,7 +541,7 @@ static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 widt { u32 sw; - if (IS_GEN2(dev_priv)) + if (IS_GEN(dev_priv, 2)) sw = ALIGN((offset & 31) + width, 32); else sw = ALIGN((offset & 63) + width, 64); @@ -778,7 +778,7 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay, u32 oconfig; oconfig = OCONF_CC_OUT_8BIT; - if (IS_GEN4(dev_priv)) + if (IS_GEN(dev_priv, 4)) oconfig |= OCONF_CSC_MODE_BT709; oconfig |= pipe == 0 ? OCONF_PIPE_A : OCONF_PIPE_B; @@ -1012,7 +1012,7 @@ static int check_overlay_src(struct drm_i915_private *dev_priv, if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) return -EINVAL; - if (IS_GEN4(dev_priv) && rec->stride_Y < 512) + if (IS_GEN(dev_priv, 4) && rec->stride_Y < 512) return -EINVAL; tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? @@ -1246,7 +1246,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, attrs->contrast = overlay->contrast; attrs->saturation = overlay->saturation; - if (!IS_GEN2(dev_priv)) { + if (!IS_GEN(dev_priv, 2)) { attrs->gamma0 = I915_READ(OGAMC0); attrs->gamma1 = I915_READ(OGAMC1); attrs->gamma2 = I915_READ(OGAMC2); @@ -1270,7 +1270,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, update_reg_attrs(overlay, overlay->regs); if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { - if (IS_GEN2(dev_priv)) + if (IS_GEN(dev_priv, 2)) goto out_unlock; if (overlay->active) { diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index ad88008f8dd0..381f0eb7b984 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -563,7 +563,7 @@ static void i9xx_set_backlight(const struct drm_connector_state *conn_state, u32 pci_write_config_byte(dev_priv->drm.pdev, LBPC, lbpc); } - if (IS_GEN4(dev_priv)) { + if (IS_GEN(dev_priv, 4)) { mask = BACKLIGHT_DUTY_CYCLE_MASK; } else { level <<= 1; @@ -929,7 +929,7 @@ static void i9xx_enable_backlight(const struct intel_crtc_state *crtc_state, * 855gm only, but checking for gen2 is safe, as 855gm is the only gen2 * that has backlight. */ - if (IS_GEN2(dev_priv)) + if (IS_GEN(dev_priv, 2)) I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE); } @@ -1557,7 +1557,7 @@ static int i9xx_setup_backlight(struct intel_connector *connector, enum pipe unu ctl = I915_READ(BLC_PWM_CTL); - if (IS_GEN2(dev_priv) || IS_I915GM(dev_priv) || IS_I945GM(dev_priv)) + if (IS_GEN(dev_priv, 2) || IS_I915GM(dev_priv) || IS_I945GM(dev_priv)) panel->backlight.combination_mode = ctl & BLM_LEGACY_MODE; if (IS_PINEVIEW(dev_priv)) @@ -1886,7 +1886,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel) panel->backlight.get = vlv_get_backlight; panel->backlight.hz_to_pwm = vlv_hz_to_pwm; } - } else if (IS_GEN4(dev_priv)) { + } else if (IS_GEN(dev_priv, 4)) { panel->backlight.setup = i965_setup_backlight; panel->backlight.enable = i965_enable_backlight; panel->backlight.disable = i965_disable_backlight; diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c index f3c9010e332a..9e870caf8104 100644 --- a/drivers/gpu/drm/i915/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c @@ -427,13 +427,13 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv, enum intel_pipe_crc_source *source, u32 *val, bool set_wa) { - if (IS_GEN2(dev_priv)) + if (IS_GEN(dev_priv, 2)) return i8xx_pipe_crc_ctl_reg(source, val); else if (INTEL_GEN(dev_priv) < 5) return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val); else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val); - else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) + else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) return ilk_pipe_crc_ctl_reg(source, val); else return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa); @@ -544,13 +544,13 @@ static int intel_is_valid_crc_source(struct drm_i915_private *dev_priv, const enum intel_pipe_crc_source source) { - if (IS_GEN2(dev_priv)) + if (IS_GEN(dev_priv, 2)) return i8xx_crc_source_valid(dev_priv, source); else if (INTEL_GEN(dev_priv) < 5) return i9xx_crc_source_valid(dev_priv, source); else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) return vlv_crc_source_valid(dev_priv, source); - else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) + else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) return ilk_crc_source_valid(dev_priv, source); else return ivb_crc_source_valid(dev_priv, source); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 82c82e233154..c14de050bc07 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2273,7 +2273,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc) if (IS_I945GM(dev_priv)) wm_info = &i945_wm_info; - else if (!IS_GEN2(dev_priv)) + else if (!IS_GEN(dev_priv, 2)) wm_info = &i915_wm_info; else wm_info = &i830_a_wm_info; @@ -2287,7 +2287,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc) crtc->base.primary->state->fb; int cpp; - if (IS_GEN2(dev_priv)) + if (IS_GEN(dev_priv, 2)) cpp = 4; else cpp = fb->format->cpp[0]; @@ -2302,7 +2302,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc) planea_wm = wm_info->max_wm; } - if (IS_GEN2(dev_priv)) + if (IS_GEN(dev_priv, 2)) wm_info = &i830_bc_wm_info; fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B); @@ -2314,7 +2314,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc) crtc->base.primary->state->fb; int cpp; - if (IS_GEN2(dev_priv)) + if (IS_GEN(dev_priv, 2)) cpp = 4; else cpp = fb->format->cpp[0]; @@ -2917,7 +2917,7 @@ static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv, uint16_t wm[5]) { /* ILK sprite LP0 latency is 1300 ns */ - if (IS_GEN5(dev_priv)) + if (IS_GEN(dev_priv, 5)) wm[0] = 13; } @@ -2925,7 +2925,7 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv, uint16_t wm[5]) { /* ILK cursor LP0 latency is 1300 ns */ - if (IS_GEN5(dev_priv)) + if (IS_GEN(dev_priv, 5)) wm[0] = 13; } @@ -3024,7 +3024,7 @@ static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv) intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); - if (IS_GEN6(dev_priv)) + if (IS_GEN(dev_priv, 6)) snb_wm_latency_quirk(dev_priv); } @@ -3278,7 +3278,7 @@ static void ilk_wm_merge(struct drm_device *dev, * What we should check here is whether FBC can be * enabled sometime later. */ - if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled && + if (IS_GEN(dev_priv, 5) && !merged->fbc_wm_enabled && intel_fbc_is_active(dev_priv)) { for (level = 2; level <= max_level; level++) { struct intel_wm_level *wm = &merged->wm[level]; @@ -3716,9 +3716,9 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state) if (!intel_has_sagv(dev_priv)) return false; - if (IS_GEN9(dev_priv)) + if (IS_GEN(dev_priv, 9)) sagv_block_time_us = 30; - else if (IS_GEN10(dev_priv)) + else if (IS_GEN(dev_priv, 10)) sagv_block_time_us = 20; else sagv_block_time_us = 10; @@ -4666,7 +4666,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv, wp->plane_blocks_per_line = div_fixed16(interm_pbpl, wp->y_min_scanlines); - } else if (wp->x_tiled && IS_GEN9(dev_priv)) { + } else if (wp->x_tiled && IS_GEN(dev_priv, 9)) { interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, wp->dbuf_block_size); wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl); @@ -4734,13 +4734,13 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, selected_result = method2; } else if (ddb_allocation >= fixed16_to_u32_round_up(wp->plane_blocks_per_line)) { - if (IS_GEN9(dev_priv) && + if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) selected_result = min_fixed16(method1, method2); else selected_result = method2; } else if (latency >= wp->linetime_us) { - if (IS_GEN9(dev_priv) && + if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) selected_result = min_fixed16(method1, method2); else @@ -6990,7 +6990,7 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv) intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); /* Program defaults and thresholds for RPS */ - if (IS_GEN9(dev_priv)) + if (IS_GEN(dev_priv, 9)) I915_WRITE(GEN6_RC_VIDEO_FREQ, GEN9_FREQUENCY(dev_priv->gt_pm.rps.rp1_freq)); @@ -7226,9 +7226,9 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv) rc6vids = 0; ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); - if (IS_GEN6(dev_priv) && ret) { + if (IS_GEN(dev_priv, 6) && ret) { DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); - } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { + } else if (IS_GEN(dev_priv, 6) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); rc6vids &= 0xffff00; @@ -7928,7 +7928,7 @@ unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) { unsigned long val; - if (!IS_GEN5(dev_priv)) + if (!IS_GEN(dev_priv, 5)) return 0; spin_lock_irq(&mchdev_lock); @@ -8012,7 +8012,7 @@ static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) void i915_update_gfx_val(struct drm_i915_private *dev_priv) { - if (!IS_GEN5(dev_priv)) + if (!IS_GEN(dev_priv, 5)) return; spin_lock_irq(&mchdev_lock); @@ -8063,7 +8063,7 @@ unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) { unsigned long val; - if (!IS_GEN5(dev_priv)) + if (!IS_GEN(dev_priv, 5)) return 0; spin_lock_irq(&mchdev_lock); @@ -8351,7 +8351,7 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv) intel_freq_opcode(dev_priv, 450)); /* After setting max-softlimit, find the overclock max freq */ - if (IS_GEN6(dev_priv) || + if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { u32 params = 0; @@ -9417,9 +9417,9 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) dev_priv->display.init_clock_gating = ivb_init_clock_gating; else if (IS_VALLEYVIEW(dev_priv)) dev_priv->display.init_clock_gating = vlv_init_clock_gating; - else if (IS_GEN6(dev_priv)) + else if (IS_GEN(dev_priv, 6)) dev_priv->display.init_clock_gating = gen6_init_clock_gating; - else if (IS_GEN5(dev_priv)) + else if (IS_GEN(dev_priv, 5)) dev_priv->display.init_clock_gating = ilk_init_clock_gating; else if (IS_G4X(dev_priv)) dev_priv->display.init_clock_gating = g4x_init_clock_gating; @@ -9427,11 +9427,11 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) dev_priv->display.init_clock_gating = i965gm_init_clock_gating; else if (IS_I965G(dev_priv)) dev_priv->display.init_clock_gating = i965g_init_clock_gating; - else if (IS_GEN3(dev_priv)) + else if (IS_GEN(dev_priv, 3)) dev_priv->display.init_clock_gating = gen3_init_clock_gating; else if (IS_I85X(dev_priv) || IS_I865G(dev_priv)) dev_priv->display.init_clock_gating = i85x_init_clock_gating; - else if (IS_GEN2(dev_priv)) + else if (IS_GEN(dev_priv, 2)) dev_priv->display.init_clock_gating = i830_init_clock_gating; else { MISSING_CASE(INTEL_DEVID(dev_priv)); @@ -9447,7 +9447,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv) /* For cxsr */ if (IS_PINEVIEW(dev_priv)) i915_pineview_get_mem_freq(dev_priv); - else if (IS_GEN5(dev_priv)) + else if (IS_GEN(dev_priv, 5)) i915_ironlake_get_mem_freq(dev_priv); /* For FIFO watermark updates */ @@ -9459,9 +9459,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv) } else if (HAS_PCH_SPLIT(dev_priv)) { ilk_setup_wm_latency(dev_priv); - if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] && + if ((IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[1] && dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || - (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] && + (!IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[0] && dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm; dev_priv->display.compute_intermediate_wm = @@ -9502,12 +9502,12 @@ void intel_init_pm(struct drm_i915_private *dev_priv) dev_priv->display.update_wm = NULL; } else dev_priv->display.update_wm = pineview_update_wm; - } else if (IS_GEN4(dev_priv)) { + } else if (IS_GEN(dev_priv, 4)) { dev_priv->display.update_wm = i965_update_wm; - } else if (IS_GEN3(dev_priv)) { + } else if (IS_GEN(dev_priv, 3)) { dev_priv->display.update_wm = i9xx_update_wm; dev_priv->display.get_fifo_size = i9xx_get_fifo_size; - } else if (IS_GEN2(dev_priv)) { + } else if (IS_GEN(dev_priv, 2)) { if (INTEL_INFO(dev_priv)->num_pipes == 1) { dev_priv->display.update_wm = i845_update_wm; dev_priv->display.get_fifo_size = i845_get_fifo_size; diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index bc2d88313ed0..39afc8ed6533 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -466,7 +466,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { psr_max_h = 4096; psr_max_v = 2304; - } else if (IS_GEN9(dev_priv)) { + } else if (IS_GEN(dev_priv, 9)) { psr_max_h = 3640; psr_max_v = 2304; } @@ -574,7 +574,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, if (dev_priv->psr.psr2_enabled) { u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder)); - if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) + if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) chicken |= (PSR2_VSC_ENABLE_PROG_HEADER | PSR2_ADD_VERTICAL_LINE_COUNT); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index b8a7a014d46d..dc26929cecc3 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -123,7 +123,7 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode) cmd = MI_FLUSH; if (mode & EMIT_INVALIDATE) { cmd |= MI_EXE_FLUSH; - if (IS_G4X(rq->i915) || IS_GEN5(rq->i915)) + if (IS_G4X(rq->i915) || IS_GEN(rq->i915, 5)) cmd |= MI_INVALIDATE_ISP; } @@ -363,7 +363,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine) /* The ring status page addresses are no longer next to the rest of * the ring registers as of gen7. */ - if (IS_GEN7(dev_priv)) { + if (IS_GEN(dev_priv, 7)) { switch (engine->id) { /* * No more rings exist on Gen7. Default case is only to shut up @@ -384,7 +384,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine) mmio = VEBOX_HWS_PGA_GEN7; break; } - } else if (IS_GEN6(dev_priv)) { + } else if (IS_GEN(dev_priv, 6)) { mmio = RING_HWS_PGA_GEN6(engine->mmio_base); } else { mmio = RING_HWS_PGA(engine->mmio_base); @@ -643,17 +643,17 @@ static int init_render_ring(struct intel_engine_cs *engine) /* Required for the hardware to program scanline values for waiting */ /* WaEnableFlushTlbInvalidationMode:snb */ - if (IS_GEN6(dev_priv)) + if (IS_GEN(dev_priv, 6)) I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ - if (IS_GEN7(dev_priv)) + if (IS_GEN(dev_priv, 7)) I915_WRITE(GFX_MODE_GEN7, _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); - if (IS_GEN6(dev_priv)) { + if (IS_GEN(dev_priv, 6)) { /* From the Sandybridge PRM, volume 1 part 3, page 24: * "If this bit is set, STCunit will have LRA as replacement * policy. [...] This bit must be reset. LRA replacement @@ -1531,7 +1531,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) enum intel_engine_id id; const int num_rings = /* Use an extended w/a on gen7 if signalling from other rings */ - (HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ? + (HAS_LEGACY_SEMAPHORES(i915) && IS_GEN(i915, 7)) ? INTEL_INFO(i915)->num_rings - 1 : 0; bool force_restore = false; @@ -1546,7 +1546,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN; len = 4; - if (IS_GEN7(i915)) + if (IS_GEN(i915, 7)) len += 2 + (num_rings ? 4*num_rings + 6 : 0); if (flags & MI_FORCE_RESTORE) { GEM_BUG_ON(flags & MI_RESTORE_INHIBIT); @@ -1560,7 +1560,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) return PTR_ERR(cs); /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ - if (IS_GEN7(i915)) { + if (IS_GEN(i915, 7)) { *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; if (num_rings) { struct intel_engine_cs *signaller; @@ -1607,7 +1607,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) */ *cs++ = MI_NOOP; - if (IS_GEN7(i915)) { + if (IS_GEN(i915, 7)) { if (num_rings) { struct intel_engine_cs *signaller; i915_reg_t last_reg = {}; /* keep gcc quiet */ @@ -2230,9 +2230,9 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine) if (INTEL_GEN(dev_priv) >= 6) { engine->init_context = intel_rcs_ctx_init; engine->emit_flush = gen7_render_ring_flush; - if (IS_GEN6(dev_priv)) + if (IS_GEN(dev_priv, 6)) engine->emit_flush = gen6_render_ring_flush; - } else if (IS_GEN5(dev_priv)) { + } else if (IS_GEN(dev_priv, 5)) { engine->emit_flush = gen4_render_ring_flush; } else { if (INTEL_GEN(dev_priv) < 4) @@ -2262,13 +2262,13 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) if (INTEL_GEN(dev_priv) >= 6) { /* gen6 bsd needs a special wa for tail updates */ - if (IS_GEN6(dev_priv)) + if (IS_GEN(dev_priv, 6)) engine->set_default_submission = gen6_bsd_set_default_submission; engine->emit_flush = gen6_bsd_ring_flush; engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; } else { engine->emit_flush = bsd_ring_flush; - if (IS_GEN5(dev_priv)) + if (IS_GEN(dev_priv, 5)) engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; else engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 8a2270b209b0..fb973709cf5e 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -93,11 +93,11 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a) #define I915_MAX_SUBSLICES 8 #define instdone_slice_mask(dev_priv__) \ - (IS_GEN7(dev_priv__) ? \ + (IS_GEN(dev_priv__, 7) ? \ 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask) #define instdone_subslice_mask(dev_priv__) \ - (IS_GEN7(dev_priv__) ? \ + (IS_GEN(dev_priv__, 7) ? \ 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0]) #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \ diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index b1901a6c17be..62806feb90ef 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -2993,7 +2993,7 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv, * suspend/resume, so allow it unconditionally. */ mask = DC_STATE_EN_DC9; - } else if (IS_GEN10(dev_priv) || IS_GEN9_BC(dev_priv)) { + } else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) { max_dc = 2; mask = 0; } else if (IS_GEN9_LP(dev_priv)) { diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index e7c95ec879cc..9c7b73986121 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -976,7 +976,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state, dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE; - if (IS_GEN6(dev_priv)) + if (IS_GEN(dev_priv, 6)) dvscntr |= DVS_TRICKLE_FEED_DISABLE; switch (fb->format->format) { @@ -1871,7 +1871,7 @@ static bool skl_plane_has_planar(struct drm_i915_private *dev_priv, if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) return false; - if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C) + if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C) return false; if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0) @@ -2080,7 +2080,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->check_plane = g4x_sprite_check; modifiers = i9xx_plane_format_modifiers; - if (IS_GEN6(dev_priv)) { + if (IS_GEN(dev_priv, 6)) { formats = snb_plane_formats; num_formats = ARRAY_SIZE(snb_plane_formats); diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index b34c318b238d..447b1de77cc7 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -354,7 +354,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915) /* WaEnableuKernelHeaderValidFix:skl */ /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */ - if (IS_GEN9(i915)) + if (IS_GEN(i915, 9)) attempts = 3; else attempts = 1; diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 9289515108c3..c36453d66d93 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -528,7 +528,7 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) ret |= vlv_check_for_unclaimed_mmio(dev_priv); - if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) + if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) ret |= gen6_check_for_fifo_debug(dev_priv); return ret; @@ -556,7 +556,7 @@ static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, dev_priv->uncore.funcs.force_wake_get(dev_priv, restore_forcewake); - if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) + if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv); spin_unlock_irq(&dev_priv->uncore.lock); @@ -1398,7 +1398,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv)) return; - if (IS_GEN6(dev_priv)) { + if (IS_GEN(dev_priv, 6)) { dev_priv->uncore.fw_reset = 0; dev_priv->uncore.fw_set = FORCEWAKE_KERNEL; dev_priv->uncore.fw_clear = 0; @@ -1437,7 +1437,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) FORCEWAKE_MEDIA_VEBOX_GEN11(i), FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); } - } else if (IS_GEN10(dev_priv) || IS_GEN9(dev_priv)) { + } else if (IS_GEN(dev_priv, 10) || IS_GEN(dev_priv, 9)) { dev_priv->uncore.funcs.force_wake_get = fw_domains_get_with_fallback; dev_priv->uncore.funcs.force_wake_put = fw_domains_put; @@ -1503,7 +1503,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, FORCEWAKE, FORCEWAKE_ACK); } - } else if (IS_GEN6(dev_priv)) { + } else if (IS_GEN(dev_priv, 6)) { dev_priv->uncore.funcs.force_wake_get = fw_domains_get_with_thread_status; dev_priv->uncore.funcs.force_wake_put = fw_domains_put; @@ -1570,7 +1570,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) if (IS_GEN(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) { ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen2); ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen2); - } else if (IS_GEN5(dev_priv)) { + } else if (IS_GEN(dev_priv, 5)) { ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen5); ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen5); } else if (IS_GEN(dev_priv, 6, 7)) { @@ -1582,7 +1582,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) } else { ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6); } - } else if (IS_GEN8(dev_priv)) { + } else if (IS_GEN(dev_priv, 8)) { if (IS_CHERRYVIEW(dev_priv)) { ASSIGN_FW_DOMAINS_TABLE(__chv_fw_ranges); ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable); @@ -2173,7 +2173,7 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv) return gen8_reset_engines; else if (INTEL_GEN(dev_priv) >= 6) return gen6_reset_engines; - else if (IS_GEN5(dev_priv)) + else if (IS_GEN(dev_priv, 5)) return ironlake_do_reset; else if (IS_G4X(dev_priv)) return g4x_do_reset; @@ -2341,7 +2341,7 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv, fw_domains = __gen11_fwtable_reg_write_fw_domains(offset); } else if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) { fw_domains = __fwtable_reg_write_fw_domains(offset); - } else if (IS_GEN8(dev_priv)) { + } else if (IS_GEN(dev_priv, 8)) { fw_domains = __gen8_reg_write_fw_domains(offset); } else if (IS_GEN(dev_priv, 6, 7)) { fw_domains = FORCEWAKE_RENDER; diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c index 92cb82dd0c07..630c887682e8 100644 --- a/drivers/gpu/drm/i915/intel_wopcm.c +++ b/drivers/gpu/drm/i915/intel_wopcm.c @@ -130,11 +130,11 @@ static inline int check_hw_restriction(struct drm_i915_private *i915, { int err = 0; - if (IS_GEN9(i915)) + if (IS_GEN(i915, 9)) err = gen9_check_dword_gap(guc_wopcm_base, guc_wopcm_size); if (!err && - (IS_GEN9(i915) || IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0))) + (IS_GEN(i915, 9) || IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0))) err = gen9_check_huc_fw_fits(guc_wopcm_size, huc_fw_size); return err; -- 2.19.1.1.g56c4683e68 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 2/5] drm/i915: replace IS_GEN<N> with IS_GEN(..., N) 2018-11-01 8:35 ` [PATCH 2/5] drm/i915: replace IS_GEN<N> with IS_GEN(..., N) Lucas De Marchi @ 2018-11-01 11:17 ` Jani Nikula 2018-11-01 13:27 ` Ville Syrjälä 2018-11-01 11:35 ` Tvrtko Ursulin 1 sibling, 1 reply; 23+ messages in thread From: Jani Nikula @ 2018-11-01 11:17 UTC (permalink / raw) To: Lucas De Marchi, intel-gfx; +Cc: Rodrigo Vivi On Thu, 01 Nov 2018, Lucas De Marchi <lucas.demarchi@intel.com> wrote: > Now that IS_GEN can accept 1 or 2 parameters, replace the use > of IS_GEN<N> by passing N as argument. This was generated with: Ignoring the naming and all the contentious stuff about using the same macro for ranges and single gen, I think there's a useful discussion to be had here about defining IS_GEN<N> macros for every new generation vs. passing the gen to a macro. I do prefer one IS_GEN(i915, N) over N instances of IS_GEN<N>(i915). BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/5] drm/i915: replace IS_GEN<N> with IS_GEN(..., N) 2018-11-01 11:17 ` Jani Nikula @ 2018-11-01 13:27 ` Ville Syrjälä 0 siblings, 0 replies; 23+ messages in thread From: Ville Syrjälä @ 2018-11-01 13:27 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, Lucas De Marchi, Rodrigo Vivi On Thu, Nov 01, 2018 at 01:17:07PM +0200, Jani Nikula wrote: > On Thu, 01 Nov 2018, Lucas De Marchi <lucas.demarchi@intel.com> wrote: > > Now that IS_GEN can accept 1 or 2 parameters, replace the use > > of IS_GEN<N> by passing N as argument. This was generated with: > > Ignoring the naming and all the contentious stuff about using the same > macro for ranges and single gen, I think there's a useful discussion to > be had here about defining IS_GEN<N> macros for every new generation > vs. passing the gen to a macro. > > I do prefer one IS_GEN(i915, N) over N instances of IS_GEN<N>(i915). #define _IS_GEN(n) \ static inline bool IS_GEN ## n (... i915) { return IS_GEN(i915, n); } _IS_GEN(2) _IS_GEN(3) ... I guess that's not much better apart from making typos harder to make. -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/5] drm/i915: replace IS_GEN<N> with IS_GEN(..., N) 2018-11-01 8:35 ` [PATCH 2/5] drm/i915: replace IS_GEN<N> with IS_GEN(..., N) Lucas De Marchi 2018-11-01 11:17 ` Jani Nikula @ 2018-11-01 11:35 ` Tvrtko Ursulin 2018-11-01 17:00 ` Lucas De Marchi 1 sibling, 1 reply; 23+ messages in thread From: Tvrtko Ursulin @ 2018-11-01 11:35 UTC (permalink / raw) To: Lucas De Marchi, intel-gfx; +Cc: Rodrigo Vivi On 01/11/2018 08:35, Lucas De Marchi wrote: > Now that IS_GEN can accept 1 or 2 parameters, replace the use > of IS_GEN<N> by passing N as argument. This was generated with: [snip] > diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c > index c628be05fbfe..e1c860f80eb0 100644 > --- a/drivers/gpu/drm/i915/gvt/vgpu.c > +++ b/drivers/gpu/drm/i915/gvt/vgpu.c > @@ -148,10 +148,10 @@ int intel_gvt_init_vgpu_types(struct intel_gvt *gvt) > gvt->types[i].avail_instance = min(low_avail / vgpu_types[i].low_mm, > high_avail / vgpu_types[i].high_mm); > > - if (IS_GEN8(gvt->dev_priv)) > + if (IS_GEN(gvt->dev_priv, 8)) No strong feelings either way. Old way seems a bit more readable, but perhaps it is only familiarity. How are the churn/conflict considerations given the huge (more than normal I think) number of current unmerged features? Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/5] drm/i915: replace IS_GEN<N> with IS_GEN(..., N) 2018-11-01 11:35 ` Tvrtko Ursulin @ 2018-11-01 17:00 ` Lucas De Marchi 0 siblings, 0 replies; 23+ messages in thread From: Lucas De Marchi @ 2018-11-01 17:00 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: intel-gfx, Rodrigo Vivi On Thu, Nov 01, 2018 at 11:35:10AM +0000, Tvrtko Ursulin wrote: > > On 01/11/2018 08:35, Lucas De Marchi wrote: > > Now that IS_GEN can accept 1 or 2 parameters, replace the use > > of IS_GEN<N> by passing N as argument. This was generated with: > > [snip] > > > diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c > > index c628be05fbfe..e1c860f80eb0 100644 > > --- a/drivers/gpu/drm/i915/gvt/vgpu.c > > +++ b/drivers/gpu/drm/i915/gvt/vgpu.c > > @@ -148,10 +148,10 @@ int intel_gvt_init_vgpu_types(struct intel_gvt *gvt) > > gvt->types[i].avail_instance = min(low_avail / vgpu_types[i].low_mm, > > high_avail / vgpu_types[i].high_mm); > > - if (IS_GEN8(gvt->dev_priv)) > > + if (IS_GEN(gvt->dev_priv, 8)) > > No strong feelings either way. Old way seems a bit more readable, but > perhaps it is only familiarity. > > How are the churn/conflict considerations given the huge (more than normal I > think) number of current unmerged features? That's why I thought it was important to give a working spatch together with the patch, So it can be applied on the the in-flight changes. If we aren't converting the current usages then I think there's little value in the change since it would just add another way of doing the same thing. Lucas De Marchi > > Regards, > > Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 3/5] drm/i915: merge gen checks to use range 2018-11-01 8:35 [PATCH 0/5] Make GEN macros more similar Lucas De Marchi 2018-11-01 8:35 ` [PATCH 1/5] drm/i915: let IS_GEN receive 1 or 2 arguments Lucas De Marchi 2018-11-01 8:35 ` [PATCH 2/5] drm/i915: replace IS_GEN<N> with IS_GEN(..., N) Lucas De Marchi @ 2018-11-01 8:35 ` Lucas De Marchi 2018-11-01 11:18 ` Jani Nikula 2018-11-01 11:31 ` Tvrtko Ursulin 2018-11-01 8:35 ` [PATCH 4/5] drm/i915: add helper IS_GEN_* macros Lucas De Marchi ` (4 subsequent siblings) 7 siblings, 2 replies; 23+ messages in thread From: Lucas De Marchi @ 2018-11-01 8:35 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi Instead of using several IS_GEN(), it's possible to pass the range as argument. By code inspection these were the ranges deemed necessary for spatch: @@ expression e; @@ ( - IS_GEN(e, 3) || IS_GEN(e, 4) + IS_GEN(e, 3, 4) | - IS_GEN(e, 5) || IS_GEN(e, 6) + IS_GEN(e, 5, 6) | - IS_GEN(e, 6) || IS_GEN(e, 7) + IS_GEN(e, 6, 7) | - IS_GEN(e, 7) || IS_GEN(e, 8) + IS_GEN(e, 7, 8) | - IS_GEN(e, 8) || IS_GEN(e, 9) + IS_GEN(e, 8, 9) | - IS_GEN(e, 10) || IS_GEN(e, 9) + IS_GEN(e, 9, 10) | - IS_GEN(e, 9) || IS_GEN(e, 10) + IS_GEN(e, 9, 10) ) Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 6 +++--- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- drivers/gpu/drm/i915/i915_perf.c | 2 +- drivers/gpu/drm/i915/intel_crt.c | 2 +- drivers/gpu/drm/i915/intel_device_info.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 2 +- drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +- drivers/gpu/drm/i915/intel_pipe_crc.c | 4 ++-- drivers/gpu/drm/i915/intel_uncore.c | 6 +++--- 10 files changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 28d95f9d0b0e..f2fbc016bd7f 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2030,7 +2030,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", swizzle_string(dev_priv->mm.bit_6_swizzle_y)); - if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) { + if (IS_GEN(dev_priv, 3, 4)) { seq_printf(m, "DDC = 0x%08x\n", I915_READ(DCC)); seq_printf(m, "DDC2 = 0x%08x\n", @@ -4260,7 +4260,7 @@ i915_cache_sharing_get(void *data, u64 *val) struct drm_i915_private *dev_priv = data; u32 snpcr; - if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))) + if (!(IS_GEN(dev_priv, 6, 7))) return -ENODEV; intel_runtime_pm_get(dev_priv); @@ -4280,7 +4280,7 @@ i915_cache_sharing_set(void *data, u64 val) struct drm_i915_private *dev_priv = data; u32 snpcr; - if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))) + if (!(IS_GEN(dev_priv, 6, 7))) return -ENODEV; if (val > 3) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index c9f8aa47005a..969691e50c04 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1673,7 +1673,7 @@ static void capture_reg_state(struct i915_gpu_state *error) error->ccid = I915_READ(CCID); /* 3: Feature specific registers */ - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) { + if (IS_GEN(dev_priv, 6, 7)) { error->gam_ecochk = I915_READ(GAM_ECOCHK); error->gac_eco = I915_READ(GAC_ECO_BITS); } diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 92daddf79cb0..baaa7b70ffa0 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -3449,7 +3449,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.ops.read = gen8_oa_read; dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read; - if (IS_GEN(dev_priv, 8) || IS_GEN(dev_priv, 9)) { + if (IS_GEN(dev_priv, 8, 9)) { dev_priv->perf.oa.ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr; dev_priv->perf.oa.ops.is_valid_mux_reg = diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index bf4fd739b68c..1822dccb1914 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -322,7 +322,7 @@ intel_crt_mode_valid(struct drm_connector *connector, * DAC limit supposedly 355 MHz. */ max_clock = 270000; - else if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) + else if (IS_GEN(dev_priv, 3, 4)) max_clock = 400000; else max_clock = 350000; diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 873f37b7b796..a1b046c322d5 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -783,7 +783,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) DRM_INFO("Display disabled (module parameter)\n"); info->num_pipes = 0; } else if (info->num_pipes > 0 && - (IS_GEN(dev_priv, 7) || IS_GEN(dev_priv, 8)) && + (IS_GEN(dev_priv, 7, 8)) && HAS_PCH_SPLIT(dev_priv)) { u32 fuse_strap = I915_READ(FUSE_STRAP); u32 sfuse_strap = I915_READ(SFUSE_STRAP); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 84c432cbdf5b..02b338b1d8be 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10677,7 +10677,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat * the w/a on all three platforms. */ if (plane->id == PLANE_SPRITE0 && - (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6) || + (IS_GEN(dev_priv, 5, 6) || IS_IVYBRIDGE(dev_priv)) && (turn_on || (!needs_scaling(old_plane_state) && needs_scaling(to_intel_plane_state(plane_state))))) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 7642f6634f7b..779c683b48ab 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -438,7 +438,7 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno) * the semaphore value, then when the seqno moves backwards all * future waits will complete instantly (causing rendering corruption). */ - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) { + if (IS_GEN(dev_priv, 6, 7)) { I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); if (HAS_VEBOX(dev_priv)) diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c index ff2743ccbece..a16b463a527d 100644 --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c @@ -260,7 +260,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, if (HAS_GMCH_DISPLAY(dev_priv)) i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) + else if (IS_GEN(dev_priv, 5, 6)) ironlake_set_fifo_underrun_reporting(dev, pipe, enable); else if (IS_GEN(dev_priv, 7)) ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c index 9e870caf8104..3e06570337b6 100644 --- a/drivers/gpu/drm/i915/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c @@ -433,7 +433,7 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv, return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val); else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val); - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) + else if (IS_GEN(dev_priv, 5, 6)) return ilk_pipe_crc_ctl_reg(source, val); else return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa); @@ -550,7 +550,7 @@ intel_is_valid_crc_source(struct drm_i915_private *dev_priv, return i9xx_crc_source_valid(dev_priv, source); else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) return vlv_crc_source_valid(dev_priv, source); - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) + else if (IS_GEN(dev_priv, 5, 6)) return ilk_crc_source_valid(dev_priv, source); else return ivb_crc_source_valid(dev_priv, source); diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index c36453d66d93..88cbd32d6964 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -528,7 +528,7 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) ret |= vlv_check_for_unclaimed_mmio(dev_priv); - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) + if (IS_GEN(dev_priv, 6, 7)) ret |= gen6_check_for_fifo_debug(dev_priv); return ret; @@ -556,7 +556,7 @@ static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, dev_priv->uncore.funcs.force_wake_get(dev_priv, restore_forcewake); - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) + if (IS_GEN(dev_priv, 6, 7)) dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv); spin_unlock_irq(&dev_priv->uncore.lock); @@ -1437,7 +1437,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) FORCEWAKE_MEDIA_VEBOX_GEN11(i), FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); } - } else if (IS_GEN(dev_priv, 10) || IS_GEN(dev_priv, 9)) { + } else if (IS_GEN(dev_priv, 9, 10)) { dev_priv->uncore.funcs.force_wake_get = fw_domains_get_with_fallback; dev_priv->uncore.funcs.force_wake_put = fw_domains_put; -- 2.19.1.1.g56c4683e68 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 3/5] drm/i915: merge gen checks to use range 2018-11-01 8:35 ` [PATCH 3/5] drm/i915: merge gen checks to use range Lucas De Marchi @ 2018-11-01 11:18 ` Jani Nikula 2018-11-01 11:31 ` Tvrtko Ursulin 1 sibling, 0 replies; 23+ messages in thread From: Jani Nikula @ 2018-11-01 11:18 UTC (permalink / raw) To: Lucas De Marchi, intel-gfx; +Cc: Rodrigo Vivi On Thu, 01 Nov 2018, Lucas De Marchi <lucas.demarchi@intel.com> wrote: > Instead of using several IS_GEN(), it's possible to pass the > range as argument. By code inspection these were the ranges deemed > necessary for spatch: Again, ignoring the naming for now, I do like the idea here. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/5] drm/i915: merge gen checks to use range 2018-11-01 8:35 ` [PATCH 3/5] drm/i915: merge gen checks to use range Lucas De Marchi 2018-11-01 11:18 ` Jani Nikula @ 2018-11-01 11:31 ` Tvrtko Ursulin 2018-11-02 18:10 ` Lucas De Marchi 1 sibling, 1 reply; 23+ messages in thread From: Tvrtko Ursulin @ 2018-11-01 11:31 UTC (permalink / raw) To: Lucas De Marchi, intel-gfx; +Cc: Rodrigo Vivi On 01/11/2018 08:35, Lucas De Marchi wrote: > Instead of using several IS_GEN(), it's possible to pass the > range as argument. By code inspection these were the ranges deemed > necessary for spatch: > > @@ > expression e; > @@ > ( > - IS_GEN(e, 3) || IS_GEN(e, 4) > + IS_GEN(e, 3, 4) > | > - IS_GEN(e, 5) || IS_GEN(e, 6) > + IS_GEN(e, 5, 6) > | > - IS_GEN(e, 6) || IS_GEN(e, 7) > + IS_GEN(e, 6, 7) > | > - IS_GEN(e, 7) || IS_GEN(e, 8) > + IS_GEN(e, 7, 8) > | > - IS_GEN(e, 8) || IS_GEN(e, 9) > + IS_GEN(e, 8, 9) > | > - IS_GEN(e, 10) || IS_GEN(e, 9) > + IS_GEN(e, 9, 10) > | > - IS_GEN(e, 9) || IS_GEN(e, 10) > + IS_GEN(e, 9, 10) > ) > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 6 +++--- > drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- > drivers/gpu/drm/i915/i915_perf.c | 2 +- > drivers/gpu/drm/i915/intel_crt.c | 2 +- > drivers/gpu/drm/i915/intel_device_info.c | 2 +- > drivers/gpu/drm/i915/intel_display.c | 2 +- > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- > drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +- > drivers/gpu/drm/i915/intel_pipe_crc.c | 4 ++-- > drivers/gpu/drm/i915/intel_uncore.c | 6 +++--- > 10 files changed, 15 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index 28d95f9d0b0e..f2fbc016bd7f 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -2030,7 +2030,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) > seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", > swizzle_string(dev_priv->mm.bit_6_swizzle_y)); > > - if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) { > + if (IS_GEN(dev_priv, 3, 4)) { I can see value in it but think it would read better with IS_GEN_RANGE. Are there any cases of or-ed IS_GEN checks with something sandwiched in between then, which the above spatch would miss? How many non-consecutive IS_GEN gen checks are there? To give us some ideas if the usual pattern is range, or perhaps checks against a list of gens also exists? (Gut feeling says no.) Regards, Tvrtko > seq_printf(m, "DDC = 0x%08x\n", > I915_READ(DCC)); > seq_printf(m, "DDC2 = 0x%08x\n", > @@ -4260,7 +4260,7 @@ i915_cache_sharing_get(void *data, u64 *val) > struct drm_i915_private *dev_priv = data; > u32 snpcr; > > - if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))) > + if (!(IS_GEN(dev_priv, 6, 7))) > return -ENODEV; > > intel_runtime_pm_get(dev_priv); > @@ -4280,7 +4280,7 @@ i915_cache_sharing_set(void *data, u64 val) > struct drm_i915_private *dev_priv = data; > u32 snpcr; > > - if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))) > + if (!(IS_GEN(dev_priv, 6, 7))) > return -ENODEV; > > if (val > 3) > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > index c9f8aa47005a..969691e50c04 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -1673,7 +1673,7 @@ static void capture_reg_state(struct i915_gpu_state *error) > error->ccid = I915_READ(CCID); > > /* 3: Feature specific registers */ > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) { > + if (IS_GEN(dev_priv, 6, 7)) { > error->gam_ecochk = I915_READ(GAM_ECOCHK); > error->gac_eco = I915_READ(GAC_ECO_BITS); > } > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > index 92daddf79cb0..baaa7b70ffa0 100644 > --- a/drivers/gpu/drm/i915/i915_perf.c > +++ b/drivers/gpu/drm/i915/i915_perf.c > @@ -3449,7 +3449,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) > dev_priv->perf.oa.ops.read = gen8_oa_read; > dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read; > > - if (IS_GEN(dev_priv, 8) || IS_GEN(dev_priv, 9)) { > + if (IS_GEN(dev_priv, 8, 9)) { > dev_priv->perf.oa.ops.is_valid_b_counter_reg = > gen7_is_valid_b_counter_addr; > dev_priv->perf.oa.ops.is_valid_mux_reg = > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c > index bf4fd739b68c..1822dccb1914 100644 > --- a/drivers/gpu/drm/i915/intel_crt.c > +++ b/drivers/gpu/drm/i915/intel_crt.c > @@ -322,7 +322,7 @@ intel_crt_mode_valid(struct drm_connector *connector, > * DAC limit supposedly 355 MHz. > */ > max_clock = 270000; > - else if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) > + else if (IS_GEN(dev_priv, 3, 4)) > max_clock = 400000; > else > max_clock = 350000; > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index 873f37b7b796..a1b046c322d5 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -783,7 +783,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) > DRM_INFO("Display disabled (module parameter)\n"); > info->num_pipes = 0; > } else if (info->num_pipes > 0 && > - (IS_GEN(dev_priv, 7) || IS_GEN(dev_priv, 8)) && > + (IS_GEN(dev_priv, 7, 8)) && > HAS_PCH_SPLIT(dev_priv)) { > u32 fuse_strap = I915_READ(FUSE_STRAP); > u32 sfuse_strap = I915_READ(SFUSE_STRAP); > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 84c432cbdf5b..02b338b1d8be 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -10677,7 +10677,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat > * the w/a on all three platforms. > */ > if (plane->id == PLANE_SPRITE0 && > - (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6) || > + (IS_GEN(dev_priv, 5, 6) || > IS_IVYBRIDGE(dev_priv)) && > (turn_on || (!needs_scaling(old_plane_state) && > needs_scaling(to_intel_plane_state(plane_state))))) > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > index 7642f6634f7b..779c683b48ab 100644 > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > @@ -438,7 +438,7 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno) > * the semaphore value, then when the seqno moves backwards all > * future waits will complete instantly (causing rendering corruption). > */ > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) { > + if (IS_GEN(dev_priv, 6, 7)) { > I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); > I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); > if (HAS_VEBOX(dev_priv)) > diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c > index ff2743ccbece..a16b463a527d 100644 > --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c > +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c > @@ -260,7 +260,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, > > if (HAS_GMCH_DISPLAY(dev_priv)) > i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); > - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) > + else if (IS_GEN(dev_priv, 5, 6)) > ironlake_set_fifo_underrun_reporting(dev, pipe, enable); > else if (IS_GEN(dev_priv, 7)) > ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c > index 9e870caf8104..3e06570337b6 100644 > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c > @@ -433,7 +433,7 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv, > return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val); > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val); > - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) > + else if (IS_GEN(dev_priv, 5, 6)) > return ilk_pipe_crc_ctl_reg(source, val); > else > return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa); > @@ -550,7 +550,7 @@ intel_is_valid_crc_source(struct drm_i915_private *dev_priv, > return i9xx_crc_source_valid(dev_priv, source); > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > return vlv_crc_source_valid(dev_priv, source); > - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) > + else if (IS_GEN(dev_priv, 5, 6)) > return ilk_crc_source_valid(dev_priv, source); > else > return ivb_crc_source_valid(dev_priv, source); > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index c36453d66d93..88cbd32d6964 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -528,7 +528,7 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > ret |= vlv_check_for_unclaimed_mmio(dev_priv); > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) > + if (IS_GEN(dev_priv, 6, 7)) > ret |= gen6_check_for_fifo_debug(dev_priv); > > return ret; > @@ -556,7 +556,7 @@ static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, > dev_priv->uncore.funcs.force_wake_get(dev_priv, > restore_forcewake); > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) > + if (IS_GEN(dev_priv, 6, 7)) > dev_priv->uncore.fifo_count = > fifo_free_entries(dev_priv); > spin_unlock_irq(&dev_priv->uncore.lock); > @@ -1437,7 +1437,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) > FORCEWAKE_MEDIA_VEBOX_GEN11(i), > FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); > } > - } else if (IS_GEN(dev_priv, 10) || IS_GEN(dev_priv, 9)) { > + } else if (IS_GEN(dev_priv, 9, 10)) { > dev_priv->uncore.funcs.force_wake_get = > fw_domains_get_with_fallback; > dev_priv->uncore.funcs.force_wake_put = fw_domains_put; > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/5] drm/i915: merge gen checks to use range 2018-11-01 11:31 ` Tvrtko Ursulin @ 2018-11-02 18:10 ` Lucas De Marchi 2018-11-02 19:19 ` Rodrigo Vivi 0 siblings, 1 reply; 23+ messages in thread From: Lucas De Marchi @ 2018-11-02 18:10 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: intel-gfx, Lucas De Marchi, Rodrigo Vivi On Thu, Nov 01, 2018 at 11:31:25AM +0000, Tvrtko Ursulin wrote: > > On 01/11/2018 08:35, Lucas De Marchi wrote: > > Instead of using several IS_GEN(), it's possible to pass the > > range as argument. By code inspection these were the ranges deemed > > necessary for spatch: > > > > @@ > > expression e; > > @@ > > ( > > - IS_GEN(e, 3) || IS_GEN(e, 4) > > + IS_GEN(e, 3, 4) > > | > > - IS_GEN(e, 5) || IS_GEN(e, 6) > > + IS_GEN(e, 5, 6) > > | > > - IS_GEN(e, 6) || IS_GEN(e, 7) > > + IS_GEN(e, 6, 7) > > | > > - IS_GEN(e, 7) || IS_GEN(e, 8) > > + IS_GEN(e, 7, 8) > > | > > - IS_GEN(e, 8) || IS_GEN(e, 9) > > + IS_GEN(e, 8, 9) > > | > > - IS_GEN(e, 10) || IS_GEN(e, 9) > > + IS_GEN(e, 9, 10) > > | > > - IS_GEN(e, 9) || IS_GEN(e, 10) > > + IS_GEN(e, 9, 10) > > ) > > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > > --- > > drivers/gpu/drm/i915/i915_debugfs.c | 6 +++--- > > drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- > > drivers/gpu/drm/i915/i915_perf.c | 2 +- > > drivers/gpu/drm/i915/intel_crt.c | 2 +- > > drivers/gpu/drm/i915/intel_device_info.c | 2 +- > > drivers/gpu/drm/i915/intel_display.c | 2 +- > > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- > > drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +- > > drivers/gpu/drm/i915/intel_pipe_crc.c | 4 ++-- > > drivers/gpu/drm/i915/intel_uncore.c | 6 +++--- > > 10 files changed, 15 insertions(+), 15 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > > index 28d95f9d0b0e..f2fbc016bd7f 100644 > > --- a/drivers/gpu/drm/i915/i915_debugfs.c > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > > @@ -2030,7 +2030,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) > > seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", > > swizzle_string(dev_priv->mm.bit_6_swizzle_y)); > > - if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) { > > + if (IS_GEN(dev_priv, 3, 4)) { > > I can see value in it but think it would read better with IS_GEN_RANGE. Ok, it seems there's a rough consensus of s/IS_GEN/IS_GEN_RANGE/ an then bring the patches that make sense here. There was a recent patch from Rodrigo doing that. I'll include it in next version. > > Are there any cases of or-ed IS_GEN checks with something sandwiched in > between then, which the above spatch would miss? By manually inspecting the result of ``git grep -ne "IS_GEN(.*" -- drivers/gpu/drm/i915/`` I didn't find any. The only thing I found was a missed case for gen3 || gen2 that was not covered by the spatch. > > How many non-consecutive IS_GEN gen checks are there? To give us some ideas > if the usual pattern is range, or perhaps checks against a list of gens also > exists? (Gut feeling says no.) only cases of <=, <, >=, >. thanks Lucas De Marchi > > Regards, > > Tvrtko > > > seq_printf(m, "DDC = 0x%08x\n", > > I915_READ(DCC)); > > seq_printf(m, "DDC2 = 0x%08x\n", > > @@ -4260,7 +4260,7 @@ i915_cache_sharing_get(void *data, u64 *val) > > struct drm_i915_private *dev_priv = data; > > u32 snpcr; > > - if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))) > > + if (!(IS_GEN(dev_priv, 6, 7))) > > return -ENODEV; > > intel_runtime_pm_get(dev_priv); > > @@ -4280,7 +4280,7 @@ i915_cache_sharing_set(void *data, u64 val) > > struct drm_i915_private *dev_priv = data; > > u32 snpcr; > > - if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))) > > + if (!(IS_GEN(dev_priv, 6, 7))) > > return -ENODEV; > > if (val > 3) > > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > > index c9f8aa47005a..969691e50c04 100644 > > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > > @@ -1673,7 +1673,7 @@ static void capture_reg_state(struct i915_gpu_state *error) > > error->ccid = I915_READ(CCID); > > /* 3: Feature specific registers */ > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) { > > + if (IS_GEN(dev_priv, 6, 7)) { > > error->gam_ecochk = I915_READ(GAM_ECOCHK); > > error->gac_eco = I915_READ(GAC_ECO_BITS); > > } > > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > > index 92daddf79cb0..baaa7b70ffa0 100644 > > --- a/drivers/gpu/drm/i915/i915_perf.c > > +++ b/drivers/gpu/drm/i915/i915_perf.c > > @@ -3449,7 +3449,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) > > dev_priv->perf.oa.ops.read = gen8_oa_read; > > dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read; > > - if (IS_GEN(dev_priv, 8) || IS_GEN(dev_priv, 9)) { > > + if (IS_GEN(dev_priv, 8, 9)) { > > dev_priv->perf.oa.ops.is_valid_b_counter_reg = > > gen7_is_valid_b_counter_addr; > > dev_priv->perf.oa.ops.is_valid_mux_reg = > > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c > > index bf4fd739b68c..1822dccb1914 100644 > > --- a/drivers/gpu/drm/i915/intel_crt.c > > +++ b/drivers/gpu/drm/i915/intel_crt.c > > @@ -322,7 +322,7 @@ intel_crt_mode_valid(struct drm_connector *connector, > > * DAC limit supposedly 355 MHz. > > */ > > max_clock = 270000; > > - else if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) > > + else if (IS_GEN(dev_priv, 3, 4)) > > max_clock = 400000; > > else > > max_clock = 350000; > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > > index 873f37b7b796..a1b046c322d5 100644 > > --- a/drivers/gpu/drm/i915/intel_device_info.c > > +++ b/drivers/gpu/drm/i915/intel_device_info.c > > @@ -783,7 +783,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) > > DRM_INFO("Display disabled (module parameter)\n"); > > info->num_pipes = 0; > > } else if (info->num_pipes > 0 && > > - (IS_GEN(dev_priv, 7) || IS_GEN(dev_priv, 8)) && > > + (IS_GEN(dev_priv, 7, 8)) && > > HAS_PCH_SPLIT(dev_priv)) { > > u32 fuse_strap = I915_READ(FUSE_STRAP); > > u32 sfuse_strap = I915_READ(SFUSE_STRAP); > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > index 84c432cbdf5b..02b338b1d8be 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -10677,7 +10677,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat > > * the w/a on all three platforms. > > */ > > if (plane->id == PLANE_SPRITE0 && > > - (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6) || > > + (IS_GEN(dev_priv, 5, 6) || > > IS_IVYBRIDGE(dev_priv)) && > > (turn_on || (!needs_scaling(old_plane_state) && > > needs_scaling(to_intel_plane_state(plane_state))))) > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > > index 7642f6634f7b..779c683b48ab 100644 > > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > > @@ -438,7 +438,7 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno) > > * the semaphore value, then when the seqno moves backwards all > > * future waits will complete instantly (causing rendering corruption). > > */ > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) { > > + if (IS_GEN(dev_priv, 6, 7)) { > > I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); > > I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); > > if (HAS_VEBOX(dev_priv)) > > diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c > > index ff2743ccbece..a16b463a527d 100644 > > --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c > > +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c > > @@ -260,7 +260,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, > > if (HAS_GMCH_DISPLAY(dev_priv)) > > i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); > > - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) > > + else if (IS_GEN(dev_priv, 5, 6)) > > ironlake_set_fifo_underrun_reporting(dev, pipe, enable); > > else if (IS_GEN(dev_priv, 7)) > > ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); > > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c > > index 9e870caf8104..3e06570337b6 100644 > > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c > > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c > > @@ -433,7 +433,7 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv, > > return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val); > > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > > return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val); > > - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) > > + else if (IS_GEN(dev_priv, 5, 6)) > > return ilk_pipe_crc_ctl_reg(source, val); > > else > > return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa); > > @@ -550,7 +550,7 @@ intel_is_valid_crc_source(struct drm_i915_private *dev_priv, > > return i9xx_crc_source_valid(dev_priv, source); > > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > > return vlv_crc_source_valid(dev_priv, source); > > - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) > > + else if (IS_GEN(dev_priv, 5, 6)) > > return ilk_crc_source_valid(dev_priv, source); > > else > > return ivb_crc_source_valid(dev_priv, source); > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > > index c36453d66d93..88cbd32d6964 100644 > > --- a/drivers/gpu/drm/i915/intel_uncore.c > > +++ b/drivers/gpu/drm/i915/intel_uncore.c > > @@ -528,7 +528,7 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) > > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > > ret |= vlv_check_for_unclaimed_mmio(dev_priv); > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) > > + if (IS_GEN(dev_priv, 6, 7)) > > ret |= gen6_check_for_fifo_debug(dev_priv); > > return ret; > > @@ -556,7 +556,7 @@ static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, > > dev_priv->uncore.funcs.force_wake_get(dev_priv, > > restore_forcewake); > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) > > + if (IS_GEN(dev_priv, 6, 7)) > > dev_priv->uncore.fifo_count = > > fifo_free_entries(dev_priv); > > spin_unlock_irq(&dev_priv->uncore.lock); > > @@ -1437,7 +1437,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) > > FORCEWAKE_MEDIA_VEBOX_GEN11(i), > > FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); > > } > > - } else if (IS_GEN(dev_priv, 10) || IS_GEN(dev_priv, 9)) { > > + } else if (IS_GEN(dev_priv, 9, 10)) { > > dev_priv->uncore.funcs.force_wake_get = > > fw_domains_get_with_fallback; > > dev_priv->uncore.funcs.force_wake_put = fw_domains_put; > > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/5] drm/i915: merge gen checks to use range 2018-11-02 18:10 ` Lucas De Marchi @ 2018-11-02 19:19 ` Rodrigo Vivi 2018-11-02 19:47 ` Lucas De Marchi 0 siblings, 1 reply; 23+ messages in thread From: Rodrigo Vivi @ 2018-11-02 19:19 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx, Lucas De Marchi On Fri, Nov 02, 2018 at 11:10:10AM -0700, Lucas De Marchi wrote: > On Thu, Nov 01, 2018 at 11:31:25AM +0000, Tvrtko Ursulin wrote: > > > > On 01/11/2018 08:35, Lucas De Marchi wrote: > > > Instead of using several IS_GEN(), it's possible to pass the > > > range as argument. By code inspection these were the ranges deemed > > > necessary for spatch: > > > > > > @@ > > > expression e; > > > @@ > > > ( > > > - IS_GEN(e, 3) || IS_GEN(e, 4) > > > + IS_GEN(e, 3, 4) > > > | > > > - IS_GEN(e, 5) || IS_GEN(e, 6) > > > + IS_GEN(e, 5, 6) > > > | > > > - IS_GEN(e, 6) || IS_GEN(e, 7) > > > + IS_GEN(e, 6, 7) > > > | > > > - IS_GEN(e, 7) || IS_GEN(e, 8) > > > + IS_GEN(e, 7, 8) > > > | > > > - IS_GEN(e, 8) || IS_GEN(e, 9) > > > + IS_GEN(e, 8, 9) > > > | > > > - IS_GEN(e, 10) || IS_GEN(e, 9) > > > + IS_GEN(e, 9, 10) > > > | > > > - IS_GEN(e, 9) || IS_GEN(e, 10) > > > + IS_GEN(e, 9, 10) > > > ) > > > > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > > > --- > > > drivers/gpu/drm/i915/i915_debugfs.c | 6 +++--- > > > drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- > > > drivers/gpu/drm/i915/i915_perf.c | 2 +- > > > drivers/gpu/drm/i915/intel_crt.c | 2 +- > > > drivers/gpu/drm/i915/intel_device_info.c | 2 +- > > > drivers/gpu/drm/i915/intel_display.c | 2 +- > > > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- > > > drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +- > > > drivers/gpu/drm/i915/intel_pipe_crc.c | 4 ++-- > > > drivers/gpu/drm/i915/intel_uncore.c | 6 +++--- > > > 10 files changed, 15 insertions(+), 15 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > > > index 28d95f9d0b0e..f2fbc016bd7f 100644 > > > --- a/drivers/gpu/drm/i915/i915_debugfs.c > > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > > > @@ -2030,7 +2030,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) > > > seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", > > > swizzle_string(dev_priv->mm.bit_6_swizzle_y)); > > > - if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) { > > > + if (IS_GEN(dev_priv, 3, 4)) { > > > > I can see value in it but think it would read better with IS_GEN_RANGE. > > Ok, it seems there's a rough consensus of s/IS_GEN/IS_GEN_RANGE/ an then > bring the patches that make sense here. There was a recent patch from Rodrigo > doing that. I'll include it in next version. I liked the double args idea but after reading I believe it gets clear IS_GEN_RANGE. > > > > > Are there any cases of or-ed IS_GEN checks with something sandwiched in > > between then, which the above spatch would miss? > > By manually inspecting the result of ``git grep -ne "IS_GEN(.*" -- drivers/gpu/drm/i915/`` > I didn't find any. The only thing I found was a missed case for gen3 || gen2 > that was not covered by the spatch. > > > > > How many non-consecutive IS_GEN gen checks are there? To give us some ideas > > if the usual pattern is range, or perhaps checks against a list of gens also > > exists? (Gut feeling says no.) > > only cases of <=, <, >=, >. For these cases on patches 4 and 5:: What about converting all < n to <= n-1 and all > n to >= n + 1 get FORVER back and introduce IS_GEN_UNTIL ? IS_GEN_UNTIL(dev_priv, e) IS_GEN_RANGE(dev_priv, s, FOREVER) so we can also kill INTEL_GEN. Another different idea on top of that. What about removing all "IS_"? so end result could be something like that: INTEL_GEN(dev_priv, n) DISPLAY_GEN(dev_priv, n) INTEL_GEN_RANGE(dev_priv, s, e) #or e = FOREVER DISPLAY_GEN_RANGE(dev_priv, s, e) #or e = FOREVER INTEL_GEN_UNTIL(dev_priv, e) DISPLAY_GEN_UNTIL(dev_priv, e) (maybe s/INTEL/GT) and group all of these together, because today they are spreadded apart. Thanks, Rodrigo. > > > thanks > Lucas De Marchi > > > > > Regards, > > > > Tvrtko > > > > > seq_printf(m, "DDC = 0x%08x\n", > > > I915_READ(DCC)); > > > seq_printf(m, "DDC2 = 0x%08x\n", > > > @@ -4260,7 +4260,7 @@ i915_cache_sharing_get(void *data, u64 *val) > > > struct drm_i915_private *dev_priv = data; > > > u32 snpcr; > > > - if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))) > > > + if (!(IS_GEN(dev_priv, 6, 7))) > > > return -ENODEV; > > > intel_runtime_pm_get(dev_priv); > > > @@ -4280,7 +4280,7 @@ i915_cache_sharing_set(void *data, u64 val) > > > struct drm_i915_private *dev_priv = data; > > > u32 snpcr; > > > - if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))) > > > + if (!(IS_GEN(dev_priv, 6, 7))) > > > return -ENODEV; > > > if (val > 3) > > > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > > > index c9f8aa47005a..969691e50c04 100644 > > > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > > > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > > > @@ -1673,7 +1673,7 @@ static void capture_reg_state(struct i915_gpu_state *error) > > > error->ccid = I915_READ(CCID); > > > /* 3: Feature specific registers */ > > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) { > > > + if (IS_GEN(dev_priv, 6, 7)) { > > > error->gam_ecochk = I915_READ(GAM_ECOCHK); > > > error->gac_eco = I915_READ(GAC_ECO_BITS); > > > } > > > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > > > index 92daddf79cb0..baaa7b70ffa0 100644 > > > --- a/drivers/gpu/drm/i915/i915_perf.c > > > +++ b/drivers/gpu/drm/i915/i915_perf.c > > > @@ -3449,7 +3449,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) > > > dev_priv->perf.oa.ops.read = gen8_oa_read; > > > dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read; > > > - if (IS_GEN(dev_priv, 8) || IS_GEN(dev_priv, 9)) { > > > + if (IS_GEN(dev_priv, 8, 9)) { > > > dev_priv->perf.oa.ops.is_valid_b_counter_reg = > > > gen7_is_valid_b_counter_addr; > > > dev_priv->perf.oa.ops.is_valid_mux_reg = > > > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c > > > index bf4fd739b68c..1822dccb1914 100644 > > > --- a/drivers/gpu/drm/i915/intel_crt.c > > > +++ b/drivers/gpu/drm/i915/intel_crt.c > > > @@ -322,7 +322,7 @@ intel_crt_mode_valid(struct drm_connector *connector, > > > * DAC limit supposedly 355 MHz. > > > */ > > > max_clock = 270000; > > > - else if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) > > > + else if (IS_GEN(dev_priv, 3, 4)) > > > max_clock = 400000; > > > else > > > max_clock = 350000; > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > > > index 873f37b7b796..a1b046c322d5 100644 > > > --- a/drivers/gpu/drm/i915/intel_device_info.c > > > +++ b/drivers/gpu/drm/i915/intel_device_info.c > > > @@ -783,7 +783,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) > > > DRM_INFO("Display disabled (module parameter)\n"); > > > info->num_pipes = 0; > > > } else if (info->num_pipes > 0 && > > > - (IS_GEN(dev_priv, 7) || IS_GEN(dev_priv, 8)) && > > > + (IS_GEN(dev_priv, 7, 8)) && > > > HAS_PCH_SPLIT(dev_priv)) { > > > u32 fuse_strap = I915_READ(FUSE_STRAP); > > > u32 sfuse_strap = I915_READ(SFUSE_STRAP); > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > > index 84c432cbdf5b..02b338b1d8be 100644 > > > --- a/drivers/gpu/drm/i915/intel_display.c > > > +++ b/drivers/gpu/drm/i915/intel_display.c > > > @@ -10677,7 +10677,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat > > > * the w/a on all three platforms. > > > */ > > > if (plane->id == PLANE_SPRITE0 && > > > - (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6) || > > > + (IS_GEN(dev_priv, 5, 6) || > > > IS_IVYBRIDGE(dev_priv)) && > > > (turn_on || (!needs_scaling(old_plane_state) && > > > needs_scaling(to_intel_plane_state(plane_state))))) > > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > > > index 7642f6634f7b..779c683b48ab 100644 > > > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > > > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > > > @@ -438,7 +438,7 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno) > > > * the semaphore value, then when the seqno moves backwards all > > > * future waits will complete instantly (causing rendering corruption). > > > */ > > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) { > > > + if (IS_GEN(dev_priv, 6, 7)) { > > > I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); > > > I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); > > > if (HAS_VEBOX(dev_priv)) > > > diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c > > > index ff2743ccbece..a16b463a527d 100644 > > > --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c > > > +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c > > > @@ -260,7 +260,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, > > > if (HAS_GMCH_DISPLAY(dev_priv)) > > > i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); > > > - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) > > > + else if (IS_GEN(dev_priv, 5, 6)) > > > ironlake_set_fifo_underrun_reporting(dev, pipe, enable); > > > else if (IS_GEN(dev_priv, 7)) > > > ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); > > > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c > > > index 9e870caf8104..3e06570337b6 100644 > > > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c > > > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c > > > @@ -433,7 +433,7 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv, > > > return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val); > > > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > > > return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val); > > > - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) > > > + else if (IS_GEN(dev_priv, 5, 6)) > > > return ilk_pipe_crc_ctl_reg(source, val); > > > else > > > return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa); > > > @@ -550,7 +550,7 @@ intel_is_valid_crc_source(struct drm_i915_private *dev_priv, > > > return i9xx_crc_source_valid(dev_priv, source); > > > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > > > return vlv_crc_source_valid(dev_priv, source); > > > - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) > > > + else if (IS_GEN(dev_priv, 5, 6)) > > > return ilk_crc_source_valid(dev_priv, source); > > > else > > > return ivb_crc_source_valid(dev_priv, source); > > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > > > index c36453d66d93..88cbd32d6964 100644 > > > --- a/drivers/gpu/drm/i915/intel_uncore.c > > > +++ b/drivers/gpu/drm/i915/intel_uncore.c > > > @@ -528,7 +528,7 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) > > > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > > > ret |= vlv_check_for_unclaimed_mmio(dev_priv); > > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) > > > + if (IS_GEN(dev_priv, 6, 7)) > > > ret |= gen6_check_for_fifo_debug(dev_priv); > > > return ret; > > > @@ -556,7 +556,7 @@ static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, > > > dev_priv->uncore.funcs.force_wake_get(dev_priv, > > > restore_forcewake); > > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) > > > + if (IS_GEN(dev_priv, 6, 7)) > > > dev_priv->uncore.fifo_count = > > > fifo_free_entries(dev_priv); > > > spin_unlock_irq(&dev_priv->uncore.lock); > > > @@ -1437,7 +1437,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) > > > FORCEWAKE_MEDIA_VEBOX_GEN11(i), > > > FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); > > > } > > > - } else if (IS_GEN(dev_priv, 10) || IS_GEN(dev_priv, 9)) { > > > + } else if (IS_GEN(dev_priv, 9, 10)) { > > > dev_priv->uncore.funcs.force_wake_get = > > > fw_domains_get_with_fallback; > > > dev_priv->uncore.funcs.force_wake_put = fw_domains_put; > > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/5] drm/i915: merge gen checks to use range 2018-11-02 19:19 ` Rodrigo Vivi @ 2018-11-02 19:47 ` Lucas De Marchi 2018-11-02 22:12 ` Rodrigo Vivi 0 siblings, 1 reply; 23+ messages in thread From: Lucas De Marchi @ 2018-11-02 19:47 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: intel-gfx On Fri, Nov 02, 2018 at 12:19:13PM -0700, Rodrigo Vivi wrote: > On Fri, Nov 02, 2018 at 11:10:10AM -0700, Lucas De Marchi wrote: > > On Thu, Nov 01, 2018 at 11:31:25AM +0000, Tvrtko Ursulin wrote: > > > > > > On 01/11/2018 08:35, Lucas De Marchi wrote: > > > > Instead of using several IS_GEN(), it's possible to pass the > > > > range as argument. By code inspection these were the ranges deemed > > > > necessary for spatch: > > > > > > > > @@ > > > > expression e; > > > > @@ > > > > ( > > > > - IS_GEN(e, 3) || IS_GEN(e, 4) > > > > + IS_GEN(e, 3, 4) > > > > | > > > > - IS_GEN(e, 5) || IS_GEN(e, 6) > > > > + IS_GEN(e, 5, 6) > > > > | > > > > - IS_GEN(e, 6) || IS_GEN(e, 7) > > > > + IS_GEN(e, 6, 7) > > > > | > > > > - IS_GEN(e, 7) || IS_GEN(e, 8) > > > > + IS_GEN(e, 7, 8) > > > > | > > > > - IS_GEN(e, 8) || IS_GEN(e, 9) > > > > + IS_GEN(e, 8, 9) > > > > | > > > > - IS_GEN(e, 10) || IS_GEN(e, 9) > > > > + IS_GEN(e, 9, 10) > > > > | > > > > - IS_GEN(e, 9) || IS_GEN(e, 10) > > > > + IS_GEN(e, 9, 10) > > > > ) > > > > > > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > > > > --- > > > > drivers/gpu/drm/i915/i915_debugfs.c | 6 +++--- > > > > drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- > > > > drivers/gpu/drm/i915/i915_perf.c | 2 +- > > > > drivers/gpu/drm/i915/intel_crt.c | 2 +- > > > > drivers/gpu/drm/i915/intel_device_info.c | 2 +- > > > > drivers/gpu/drm/i915/intel_display.c | 2 +- > > > > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- > > > > drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +- > > > > drivers/gpu/drm/i915/intel_pipe_crc.c | 4 ++-- > > > > drivers/gpu/drm/i915/intel_uncore.c | 6 +++--- > > > > 10 files changed, 15 insertions(+), 15 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > > > > index 28d95f9d0b0e..f2fbc016bd7f 100644 > > > > --- a/drivers/gpu/drm/i915/i915_debugfs.c > > > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > > > > @@ -2030,7 +2030,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) > > > > seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", > > > > swizzle_string(dev_priv->mm.bit_6_swizzle_y)); > > > > - if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) { > > > > + if (IS_GEN(dev_priv, 3, 4)) { > > > > > > I can see value in it but think it would read better with IS_GEN_RANGE. > > > > Ok, it seems there's a rough consensus of s/IS_GEN/IS_GEN_RANGE/ an then > > bring the patches that make sense here. There was a recent patch from Rodrigo > > doing that. I'll include it in next version. > > I liked the double args idea but after reading I believe > it gets clear IS_GEN_RANGE. > > > > > > > > > Are there any cases of or-ed IS_GEN checks with something sandwiched in > > > between then, which the above spatch would miss? > > > > By manually inspecting the result of ``git grep -ne "IS_GEN(.*" -- drivers/gpu/drm/i915/`` > > I didn't find any. The only thing I found was a missed case for gen3 || gen2 > > that was not covered by the spatch. > > > > > > > > How many non-consecutive IS_GEN gen checks are there? To give us some ideas > > > if the usual pattern is range, or perhaps checks against a list of gens also > > > exists? (Gut feeling says no.) > > > > only cases of <=, <, >=, >. > > For these cases on patches 4 and 5:: > > What about converting all < n to <= n-1 and all > n to >= n + 1 > get FORVER back and introduce IS_GEN_UNTIL ? > > IS_GEN_UNTIL(dev_priv, e) > IS_GEN_RANGE(dev_priv, s, FOREVER) > > so we can also kill INTEL_GEN. > > Another different idea on top of that. > > What about removing all "IS_"? > > so end result could be something like that: > > INTEL_GEN(dev_priv, n) > DISPLAY_GEN(dev_priv, n) > INTEL_GEN_RANGE(dev_priv, s, e) #or e = FOREVER > DISPLAY_GEN_RANGE(dev_priv, s, e) #or e = FOREVER > INTEL_GEN_UNTIL(dev_priv, e) > DISPLAY_GEN_UNTIL(dev_priv, e) > > (maybe s/INTEL/GT) I like it. I'm just not sure about UNTIL, because I will always have doubts if it's inclusive or not. But I guess we have the same today with RANGE and we just get used to it. By making all of them inclusive, it will be easier. Anyway, my preference is: GT_GEN(dev_priv, n) GT_GEN_RANGE(dev_priv, s, e) and e can be GEN_FOREVER, aka -1. The macro has enough knowledge to work out the mask, e.g. s == 10, e == FOREVER => mask == ~(BIT(s) | (BIT(s) - 1)) And the DISPLAY_GEN* counterparts. IMO there's no need to have _UNTIL because it can also be expressed as GT_GEN_RANGE(dev_priv, GEN_FOREVER, 10). This way we can also kill the comparisons INTEL_GEN(dev_priv) == x, so we always work with the gen_mask field. Which means the compiler can do a single comparison (/me hoping it actually generates good code) There are corner cases though: What should we do with e.g. IS_GEN9_LP() and friends? Any conversion like these will create a lot of noise, not only for inflight patches, but also for stable backports. So IMO anything we do needs to be scriptable. Lucas De Marchi > > and group all of these together, because today > they are spreadded apart. > > Thanks, > Rodrigo. > > > > > > > thanks > > Lucas De Marchi > > > > > > > > Regards, > > > > > > Tvrtko > > > > > > > seq_printf(m, "DDC = 0x%08x\n", > > > > I915_READ(DCC)); > > > > seq_printf(m, "DDC2 = 0x%08x\n", > > > > @@ -4260,7 +4260,7 @@ i915_cache_sharing_get(void *data, u64 *val) > > > > struct drm_i915_private *dev_priv = data; > > > > u32 snpcr; > > > > - if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))) > > > > + if (!(IS_GEN(dev_priv, 6, 7))) > > > > return -ENODEV; > > > > intel_runtime_pm_get(dev_priv); > > > > @@ -4280,7 +4280,7 @@ i915_cache_sharing_set(void *data, u64 val) > > > > struct drm_i915_private *dev_priv = data; > > > > u32 snpcr; > > > > - if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))) > > > > + if (!(IS_GEN(dev_priv, 6, 7))) > > > > return -ENODEV; > > > > if (val > 3) > > > > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > > > > index c9f8aa47005a..969691e50c04 100644 > > > > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > > > > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > > > > @@ -1673,7 +1673,7 @@ static void capture_reg_state(struct i915_gpu_state *error) > > > > error->ccid = I915_READ(CCID); > > > > /* 3: Feature specific registers */ > > > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) { > > > > + if (IS_GEN(dev_priv, 6, 7)) { > > > > error->gam_ecochk = I915_READ(GAM_ECOCHK); > > > > error->gac_eco = I915_READ(GAC_ECO_BITS); > > > > } > > > > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > > > > index 92daddf79cb0..baaa7b70ffa0 100644 > > > > --- a/drivers/gpu/drm/i915/i915_perf.c > > > > +++ b/drivers/gpu/drm/i915/i915_perf.c > > > > @@ -3449,7 +3449,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) > > > > dev_priv->perf.oa.ops.read = gen8_oa_read; > > > > dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read; > > > > - if (IS_GEN(dev_priv, 8) || IS_GEN(dev_priv, 9)) { > > > > + if (IS_GEN(dev_priv, 8, 9)) { > > > > dev_priv->perf.oa.ops.is_valid_b_counter_reg = > > > > gen7_is_valid_b_counter_addr; > > > > dev_priv->perf.oa.ops.is_valid_mux_reg = > > > > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c > > > > index bf4fd739b68c..1822dccb1914 100644 > > > > --- a/drivers/gpu/drm/i915/intel_crt.c > > > > +++ b/drivers/gpu/drm/i915/intel_crt.c > > > > @@ -322,7 +322,7 @@ intel_crt_mode_valid(struct drm_connector *connector, > > > > * DAC limit supposedly 355 MHz. > > > > */ > > > > max_clock = 270000; > > > > - else if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) > > > > + else if (IS_GEN(dev_priv, 3, 4)) > > > > max_clock = 400000; > > > > else > > > > max_clock = 350000; > > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > > > > index 873f37b7b796..a1b046c322d5 100644 > > > > --- a/drivers/gpu/drm/i915/intel_device_info.c > > > > +++ b/drivers/gpu/drm/i915/intel_device_info.c > > > > @@ -783,7 +783,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) > > > > DRM_INFO("Display disabled (module parameter)\n"); > > > > info->num_pipes = 0; > > > > } else if (info->num_pipes > 0 && > > > > - (IS_GEN(dev_priv, 7) || IS_GEN(dev_priv, 8)) && > > > > + (IS_GEN(dev_priv, 7, 8)) && > > > > HAS_PCH_SPLIT(dev_priv)) { > > > > u32 fuse_strap = I915_READ(FUSE_STRAP); > > > > u32 sfuse_strap = I915_READ(SFUSE_STRAP); > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > > > index 84c432cbdf5b..02b338b1d8be 100644 > > > > --- a/drivers/gpu/drm/i915/intel_display.c > > > > +++ b/drivers/gpu/drm/i915/intel_display.c > > > > @@ -10677,7 +10677,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat > > > > * the w/a on all three platforms. > > > > */ > > > > if (plane->id == PLANE_SPRITE0 && > > > > - (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6) || > > > > + (IS_GEN(dev_priv, 5, 6) || > > > > IS_IVYBRIDGE(dev_priv)) && > > > > (turn_on || (!needs_scaling(old_plane_state) && > > > > needs_scaling(to_intel_plane_state(plane_state))))) > > > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > > > > index 7642f6634f7b..779c683b48ab 100644 > > > > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > > > > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > > > > @@ -438,7 +438,7 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno) > > > > * the semaphore value, then when the seqno moves backwards all > > > > * future waits will complete instantly (causing rendering corruption). > > > > */ > > > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) { > > > > + if (IS_GEN(dev_priv, 6, 7)) { > > > > I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); > > > > I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); > > > > if (HAS_VEBOX(dev_priv)) > > > > diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c > > > > index ff2743ccbece..a16b463a527d 100644 > > > > --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c > > > > +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c > > > > @@ -260,7 +260,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, > > > > if (HAS_GMCH_DISPLAY(dev_priv)) > > > > i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); > > > > - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) > > > > + else if (IS_GEN(dev_priv, 5, 6)) > > > > ironlake_set_fifo_underrun_reporting(dev, pipe, enable); > > > > else if (IS_GEN(dev_priv, 7)) > > > > ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); > > > > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c > > > > index 9e870caf8104..3e06570337b6 100644 > > > > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c > > > > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c > > > > @@ -433,7 +433,7 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv, > > > > return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val); > > > > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > > > > return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val); > > > > - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) > > > > + else if (IS_GEN(dev_priv, 5, 6)) > > > > return ilk_pipe_crc_ctl_reg(source, val); > > > > else > > > > return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa); > > > > @@ -550,7 +550,7 @@ intel_is_valid_crc_source(struct drm_i915_private *dev_priv, > > > > return i9xx_crc_source_valid(dev_priv, source); > > > > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > > > > return vlv_crc_source_valid(dev_priv, source); > > > > - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) > > > > + else if (IS_GEN(dev_priv, 5, 6)) > > > > return ilk_crc_source_valid(dev_priv, source); > > > > else > > > > return ivb_crc_source_valid(dev_priv, source); > > > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > > > > index c36453d66d93..88cbd32d6964 100644 > > > > --- a/drivers/gpu/drm/i915/intel_uncore.c > > > > +++ b/drivers/gpu/drm/i915/intel_uncore.c > > > > @@ -528,7 +528,7 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) > > > > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > > > > ret |= vlv_check_for_unclaimed_mmio(dev_priv); > > > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) > > > > + if (IS_GEN(dev_priv, 6, 7)) > > > > ret |= gen6_check_for_fifo_debug(dev_priv); > > > > return ret; > > > > @@ -556,7 +556,7 @@ static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, > > > > dev_priv->uncore.funcs.force_wake_get(dev_priv, > > > > restore_forcewake); > > > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) > > > > + if (IS_GEN(dev_priv, 6, 7)) > > > > dev_priv->uncore.fifo_count = > > > > fifo_free_entries(dev_priv); > > > > spin_unlock_irq(&dev_priv->uncore.lock); > > > > @@ -1437,7 +1437,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) > > > > FORCEWAKE_MEDIA_VEBOX_GEN11(i), > > > > FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); > > > > } > > > > - } else if (IS_GEN(dev_priv, 10) || IS_GEN(dev_priv, 9)) { > > > > + } else if (IS_GEN(dev_priv, 9, 10)) { > > > > dev_priv->uncore.funcs.force_wake_get = > > > > fw_domains_get_with_fallback; > > > > dev_priv->uncore.funcs.force_wake_put = fw_domains_put; > > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/5] drm/i915: merge gen checks to use range 2018-11-02 19:47 ` Lucas De Marchi @ 2018-11-02 22:12 ` Rodrigo Vivi 2018-11-02 22:28 ` Lucas De Marchi 0 siblings, 1 reply; 23+ messages in thread From: Rodrigo Vivi @ 2018-11-02 22:12 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx On Fri, Nov 02, 2018 at 12:47:28PM -0700, Lucas De Marchi wrote: > On Fri, Nov 02, 2018 at 12:19:13PM -0700, Rodrigo Vivi wrote: > > On Fri, Nov 02, 2018 at 11:10:10AM -0700, Lucas De Marchi wrote: > > > On Thu, Nov 01, 2018 at 11:31:25AM +0000, Tvrtko Ursulin wrote: > > > > > > > > On 01/11/2018 08:35, Lucas De Marchi wrote: > > > > > Instead of using several IS_GEN(), it's possible to pass the > > > > > range as argument. By code inspection these were the ranges deemed > > > > > necessary for spatch: > > > > > > > > > > @@ > > > > > expression e; > > > > > @@ > > > > > ( > > > > > - IS_GEN(e, 3) || IS_GEN(e, 4) > > > > > + IS_GEN(e, 3, 4) > > > > > | > > > > > - IS_GEN(e, 5) || IS_GEN(e, 6) > > > > > + IS_GEN(e, 5, 6) > > > > > | > > > > > - IS_GEN(e, 6) || IS_GEN(e, 7) > > > > > + IS_GEN(e, 6, 7) > > > > > | > > > > > - IS_GEN(e, 7) || IS_GEN(e, 8) > > > > > + IS_GEN(e, 7, 8) > > > > > | > > > > > - IS_GEN(e, 8) || IS_GEN(e, 9) > > > > > + IS_GEN(e, 8, 9) > > > > > | > > > > > - IS_GEN(e, 10) || IS_GEN(e, 9) > > > > > + IS_GEN(e, 9, 10) > > > > > | > > > > > - IS_GEN(e, 9) || IS_GEN(e, 10) > > > > > + IS_GEN(e, 9, 10) > > > > > ) > > > > > > > > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > > > > > --- > > > > > drivers/gpu/drm/i915/i915_debugfs.c | 6 +++--- > > > > > drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- > > > > > drivers/gpu/drm/i915/i915_perf.c | 2 +- > > > > > drivers/gpu/drm/i915/intel_crt.c | 2 +- > > > > > drivers/gpu/drm/i915/intel_device_info.c | 2 +- > > > > > drivers/gpu/drm/i915/intel_display.c | 2 +- > > > > > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- > > > > > drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +- > > > > > drivers/gpu/drm/i915/intel_pipe_crc.c | 4 ++-- > > > > > drivers/gpu/drm/i915/intel_uncore.c | 6 +++--- > > > > > 10 files changed, 15 insertions(+), 15 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > > > > > index 28d95f9d0b0e..f2fbc016bd7f 100644 > > > > > --- a/drivers/gpu/drm/i915/i915_debugfs.c > > > > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > > > > > @@ -2030,7 +2030,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) > > > > > seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", > > > > > swizzle_string(dev_priv->mm.bit_6_swizzle_y)); > > > > > - if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) { > > > > > + if (IS_GEN(dev_priv, 3, 4)) { > > > > > > > > I can see value in it but think it would read better with IS_GEN_RANGE. > > > > > > Ok, it seems there's a rough consensus of s/IS_GEN/IS_GEN_RANGE/ an then > > > bring the patches that make sense here. There was a recent patch from Rodrigo > > > doing that. I'll include it in next version. > > > > I liked the double args idea but after reading I believe > > it gets clear IS_GEN_RANGE. > > > > > > > > > > > > > Are there any cases of or-ed IS_GEN checks with something sandwiched in > > > > between then, which the above spatch would miss? > > > > > > By manually inspecting the result of ``git grep -ne "IS_GEN(.*" -- drivers/gpu/drm/i915/`` > > > I didn't find any. The only thing I found was a missed case for gen3 || gen2 > > > that was not covered by the spatch. > > > > > > > > > > > How many non-consecutive IS_GEN gen checks are there? To give us some ideas > > > > if the usual pattern is range, or perhaps checks against a list of gens also > > > > exists? (Gut feeling says no.) > > > > > > only cases of <=, <, >=, >. > > > > For these cases on patches 4 and 5:: > > > > What about converting all < n to <= n-1 and all > n to >= n + 1 > > get FORVER back and introduce IS_GEN_UNTIL ? > > > > IS_GEN_UNTIL(dev_priv, e) > > IS_GEN_RANGE(dev_priv, s, FOREVER) > > > > so we can also kill INTEL_GEN. > > > > Another different idea on top of that. > > > > What about removing all "IS_"? > > > > so end result could be something like that: > > > > INTEL_GEN(dev_priv, n) > > DISPLAY_GEN(dev_priv, n) > > INTEL_GEN_RANGE(dev_priv, s, e) #or e = FOREVER > > DISPLAY_GEN_RANGE(dev_priv, s, e) #or e = FOREVER > > INTEL_GEN_UNTIL(dev_priv, e) > > DISPLAY_GEN_UNTIL(dev_priv, e) > > > > (maybe s/INTEL/GT) > > I like it. I'm just not sure about UNTIL, because I will always have doubts if > it's inclusive or not. But I guess we have the same today with RANGE and we > just get used to it. By making all of them inclusive, it will be easier. > > Anyway, my preference is: > > GT_GEN(dev_priv, n) > GT_GEN_RANGE(dev_priv, s, e) > and e can be GEN_FOREVER, aka -1. The macro has enough knowledge to work out one niptik I prefer FOREVER alone than GEN_FOREVER because macro already has "GEN" > the mask, e.g. s == 10, e == FOREVER => mask == ~(BIT(s) | (BIT(s) - 1)) > > And the DISPLAY_GEN* counterparts. > > IMO there's no need to have _UNTIL because it can also be expressed as > GT_GEN_RANGE(dev_priv, GEN_FOREVER, 10). Yeap, the GEN_FOREVER I had just killed last week covered this case, but my brain refuses to use and accept FOREVER to something in the past. maybe GT_GEN_RANGE(dev_priv, 0, 10) instead of UNTIL ? or GT_GEN_RANGE(dev_priv, BEGIN, 10) ? > > This way we can also kill the comparisons INTEL_GEN(dev_priv) == x, so we always > work with the gen_mask field. Which means the compiler can do a single comparison > (/me hoping it actually generates good code) yeap! > > There are corner cases though: > > What should we do with e.g. IS_GEN9_LP() and friends? #define GT_GEN_LP(dev_priv, n) GT_GEN(dev_priv, n) && IS_LP(dev_priv) #define DISPLAY_GEN_LP(dev_priv, n) DISPLAY_GEN(dev_priv, n) && IS_LP(dev_priv) #define GT_GEN_BC(dev_priv, n) GT_GEN(dev_priv, n) && !IS_LP(dev_priv) #define DISPLAY_GEN_BC(dev_priv, n) DISPLAY_GEN(dev_priv, n) && !IS_LP(dev_priv) I think this would be useful to replace many IS_VALLEYVIEW || IS_CHERRYVIEW to DISPLAY_GEN_LP(dev_priv, 7) either this above or simply kill it in favor of a more verbose version everywhere GT_GEN(dev_priv, 9) && IS_LP(dev_priv) ?! :/ > > > Any conversion like these will create a lot of noise, not only for inflight patches, > but also for stable backports. So IMO anything we do needs to be scriptable. I fully agree. Thanks, Rodrigo. > > Lucas De Marchi > > > > > and group all of these together, because today > > they are spreadded apart. > > > > Thanks, > > Rodrigo. > > > > > > > > > > > thanks > > > Lucas De Marchi > > > > > > > > > > > Regards, > > > > > > > > Tvrtko > > > > > > > > > seq_printf(m, "DDC = 0x%08x\n", > > > > > I915_READ(DCC)); > > > > > seq_printf(m, "DDC2 = 0x%08x\n", > > > > > @@ -4260,7 +4260,7 @@ i915_cache_sharing_get(void *data, u64 *val) > > > > > struct drm_i915_private *dev_priv = data; > > > > > u32 snpcr; > > > > > - if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))) > > > > > + if (!(IS_GEN(dev_priv, 6, 7))) > > > > > return -ENODEV; > > > > > intel_runtime_pm_get(dev_priv); > > > > > @@ -4280,7 +4280,7 @@ i915_cache_sharing_set(void *data, u64 val) > > > > > struct drm_i915_private *dev_priv = data; > > > > > u32 snpcr; > > > > > - if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))) > > > > > + if (!(IS_GEN(dev_priv, 6, 7))) > > > > > return -ENODEV; > > > > > if (val > 3) > > > > > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > > > > > index c9f8aa47005a..969691e50c04 100644 > > > > > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > > > > > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > > > > > @@ -1673,7 +1673,7 @@ static void capture_reg_state(struct i915_gpu_state *error) > > > > > error->ccid = I915_READ(CCID); > > > > > /* 3: Feature specific registers */ > > > > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) { > > > > > + if (IS_GEN(dev_priv, 6, 7)) { > > > > > error->gam_ecochk = I915_READ(GAM_ECOCHK); > > > > > error->gac_eco = I915_READ(GAC_ECO_BITS); > > > > > } > > > > > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > > > > > index 92daddf79cb0..baaa7b70ffa0 100644 > > > > > --- a/drivers/gpu/drm/i915/i915_perf.c > > > > > +++ b/drivers/gpu/drm/i915/i915_perf.c > > > > > @@ -3449,7 +3449,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) > > > > > dev_priv->perf.oa.ops.read = gen8_oa_read; > > > > > dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read; > > > > > - if (IS_GEN(dev_priv, 8) || IS_GEN(dev_priv, 9)) { > > > > > + if (IS_GEN(dev_priv, 8, 9)) { > > > > > dev_priv->perf.oa.ops.is_valid_b_counter_reg = > > > > > gen7_is_valid_b_counter_addr; > > > > > dev_priv->perf.oa.ops.is_valid_mux_reg = > > > > > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c > > > > > index bf4fd739b68c..1822dccb1914 100644 > > > > > --- a/drivers/gpu/drm/i915/intel_crt.c > > > > > +++ b/drivers/gpu/drm/i915/intel_crt.c > > > > > @@ -322,7 +322,7 @@ intel_crt_mode_valid(struct drm_connector *connector, > > > > > * DAC limit supposedly 355 MHz. > > > > > */ > > > > > max_clock = 270000; > > > > > - else if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) > > > > > + else if (IS_GEN(dev_priv, 3, 4)) > > > > > max_clock = 400000; > > > > > else > > > > > max_clock = 350000; > > > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > > > > > index 873f37b7b796..a1b046c322d5 100644 > > > > > --- a/drivers/gpu/drm/i915/intel_device_info.c > > > > > +++ b/drivers/gpu/drm/i915/intel_device_info.c > > > > > @@ -783,7 +783,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) > > > > > DRM_INFO("Display disabled (module parameter)\n"); > > > > > info->num_pipes = 0; > > > > > } else if (info->num_pipes > 0 && > > > > > - (IS_GEN(dev_priv, 7) || IS_GEN(dev_priv, 8)) && > > > > > + (IS_GEN(dev_priv, 7, 8)) && > > > > > HAS_PCH_SPLIT(dev_priv)) { > > > > > u32 fuse_strap = I915_READ(FUSE_STRAP); > > > > > u32 sfuse_strap = I915_READ(SFUSE_STRAP); > > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > > > > index 84c432cbdf5b..02b338b1d8be 100644 > > > > > --- a/drivers/gpu/drm/i915/intel_display.c > > > > > +++ b/drivers/gpu/drm/i915/intel_display.c > > > > > @@ -10677,7 +10677,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat > > > > > * the w/a on all three platforms. > > > > > */ > > > > > if (plane->id == PLANE_SPRITE0 && > > > > > - (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6) || > > > > > + (IS_GEN(dev_priv, 5, 6) || > > > > > IS_IVYBRIDGE(dev_priv)) && > > > > > (turn_on || (!needs_scaling(old_plane_state) && > > > > > needs_scaling(to_intel_plane_state(plane_state))))) > > > > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > > > > > index 7642f6634f7b..779c683b48ab 100644 > > > > > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > > > > > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > > > > > @@ -438,7 +438,7 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno) > > > > > * the semaphore value, then when the seqno moves backwards all > > > > > * future waits will complete instantly (causing rendering corruption). > > > > > */ > > > > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) { > > > > > + if (IS_GEN(dev_priv, 6, 7)) { > > > > > I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); > > > > > I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); > > > > > if (HAS_VEBOX(dev_priv)) > > > > > diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c > > > > > index ff2743ccbece..a16b463a527d 100644 > > > > > --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c > > > > > +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c > > > > > @@ -260,7 +260,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, > > > > > if (HAS_GMCH_DISPLAY(dev_priv)) > > > > > i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); > > > > > - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) > > > > > + else if (IS_GEN(dev_priv, 5, 6)) > > > > > ironlake_set_fifo_underrun_reporting(dev, pipe, enable); > > > > > else if (IS_GEN(dev_priv, 7)) > > > > > ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); > > > > > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c > > > > > index 9e870caf8104..3e06570337b6 100644 > > > > > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c > > > > > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c > > > > > @@ -433,7 +433,7 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv, > > > > > return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val); > > > > > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > > > > > return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val); > > > > > - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) > > > > > + else if (IS_GEN(dev_priv, 5, 6)) > > > > > return ilk_pipe_crc_ctl_reg(source, val); > > > > > else > > > > > return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa); > > > > > @@ -550,7 +550,7 @@ intel_is_valid_crc_source(struct drm_i915_private *dev_priv, > > > > > return i9xx_crc_source_valid(dev_priv, source); > > > > > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > > > > > return vlv_crc_source_valid(dev_priv, source); > > > > > - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) > > > > > + else if (IS_GEN(dev_priv, 5, 6)) > > > > > return ilk_crc_source_valid(dev_priv, source); > > > > > else > > > > > return ivb_crc_source_valid(dev_priv, source); > > > > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > > > > > index c36453d66d93..88cbd32d6964 100644 > > > > > --- a/drivers/gpu/drm/i915/intel_uncore.c > > > > > +++ b/drivers/gpu/drm/i915/intel_uncore.c > > > > > @@ -528,7 +528,7 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) > > > > > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > > > > > ret |= vlv_check_for_unclaimed_mmio(dev_priv); > > > > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) > > > > > + if (IS_GEN(dev_priv, 6, 7)) > > > > > ret |= gen6_check_for_fifo_debug(dev_priv); > > > > > return ret; > > > > > @@ -556,7 +556,7 @@ static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, > > > > > dev_priv->uncore.funcs.force_wake_get(dev_priv, > > > > > restore_forcewake); > > > > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) > > > > > + if (IS_GEN(dev_priv, 6, 7)) > > > > > dev_priv->uncore.fifo_count = > > > > > fifo_free_entries(dev_priv); > > > > > spin_unlock_irq(&dev_priv->uncore.lock); > > > > > @@ -1437,7 +1437,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) > > > > > FORCEWAKE_MEDIA_VEBOX_GEN11(i), > > > > > FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); > > > > > } > > > > > - } else if (IS_GEN(dev_priv, 10) || IS_GEN(dev_priv, 9)) { > > > > > + } else if (IS_GEN(dev_priv, 9, 10)) { > > > > > dev_priv->uncore.funcs.force_wake_get = > > > > > fw_domains_get_with_fallback; > > > > > dev_priv->uncore.funcs.force_wake_put = fw_domains_put; > > > > > > > > > _______________________________________________ > > > > Intel-gfx mailing list > > > > Intel-gfx@lists.freedesktop.org > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/5] drm/i915: merge gen checks to use range 2018-11-02 22:12 ` Rodrigo Vivi @ 2018-11-02 22:28 ` Lucas De Marchi 2018-11-02 22:47 ` Rodrigo Vivi 0 siblings, 1 reply; 23+ messages in thread From: Lucas De Marchi @ 2018-11-02 22:28 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: intel-gfx, Lucas De Marchi On Fri, Nov 02, 2018 at 03:12:18PM -0700, Rodrigo Vivi wrote: > On Fri, Nov 02, 2018 at 12:47:28PM -0700, Lucas De Marchi wrote: > > On Fri, Nov 02, 2018 at 12:19:13PM -0700, Rodrigo Vivi wrote: > > > On Fri, Nov 02, 2018 at 11:10:10AM -0700, Lucas De Marchi wrote: > > > > On Thu, Nov 01, 2018 at 11:31:25AM +0000, Tvrtko Ursulin wrote: > > > > > > > > > > On 01/11/2018 08:35, Lucas De Marchi wrote: > > > > > > Instead of using several IS_GEN(), it's possible to pass the > > > > > > range as argument. By code inspection these were the ranges deemed > > > > > > necessary for spatch: > > > > > > > > > > > > @@ > > > > > > expression e; > > > > > > @@ > > > > > > ( > > > > > > - IS_GEN(e, 3) || IS_GEN(e, 4) > > > > > > + IS_GEN(e, 3, 4) > > > > > > | > > > > > > - IS_GEN(e, 5) || IS_GEN(e, 6) > > > > > > + IS_GEN(e, 5, 6) > > > > > > | > > > > > > - IS_GEN(e, 6) || IS_GEN(e, 7) > > > > > > + IS_GEN(e, 6, 7) > > > > > > | > > > > > > - IS_GEN(e, 7) || IS_GEN(e, 8) > > > > > > + IS_GEN(e, 7, 8) > > > > > > | > > > > > > - IS_GEN(e, 8) || IS_GEN(e, 9) > > > > > > + IS_GEN(e, 8, 9) > > > > > > | > > > > > > - IS_GEN(e, 10) || IS_GEN(e, 9) > > > > > > + IS_GEN(e, 9, 10) > > > > > > | > > > > > > - IS_GEN(e, 9) || IS_GEN(e, 10) > > > > > > + IS_GEN(e, 9, 10) > > > > > > ) > > > > > > > > > > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > > > > > > --- > > > > > > drivers/gpu/drm/i915/i915_debugfs.c | 6 +++--- > > > > > > drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- > > > > > > drivers/gpu/drm/i915/i915_perf.c | 2 +- > > > > > > drivers/gpu/drm/i915/intel_crt.c | 2 +- > > > > > > drivers/gpu/drm/i915/intel_device_info.c | 2 +- > > > > > > drivers/gpu/drm/i915/intel_display.c | 2 +- > > > > > > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- > > > > > > drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +- > > > > > > drivers/gpu/drm/i915/intel_pipe_crc.c | 4 ++-- > > > > > > drivers/gpu/drm/i915/intel_uncore.c | 6 +++--- > > > > > > 10 files changed, 15 insertions(+), 15 deletions(-) > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > > > > > > index 28d95f9d0b0e..f2fbc016bd7f 100644 > > > > > > --- a/drivers/gpu/drm/i915/i915_debugfs.c > > > > > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > > > > > > @@ -2030,7 +2030,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) > > > > > > seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", > > > > > > swizzle_string(dev_priv->mm.bit_6_swizzle_y)); > > > > > > - if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) { > > > > > > + if (IS_GEN(dev_priv, 3, 4)) { > > > > > > > > > > I can see value in it but think it would read better with IS_GEN_RANGE. > > > > > > > > Ok, it seems there's a rough consensus of s/IS_GEN/IS_GEN_RANGE/ an then > > > > bring the patches that make sense here. There was a recent patch from Rodrigo > > > > doing that. I'll include it in next version. > > > > > > I liked the double args idea but after reading I believe > > > it gets clear IS_GEN_RANGE. > > > > > > > > > > > > > > > > > Are there any cases of or-ed IS_GEN checks with something sandwiched in > > > > > between then, which the above spatch would miss? > > > > > > > > By manually inspecting the result of ``git grep -ne "IS_GEN(.*" -- drivers/gpu/drm/i915/`` > > > > I didn't find any. The only thing I found was a missed case for gen3 || gen2 > > > > that was not covered by the spatch. > > > > > > > > > > > > > > How many non-consecutive IS_GEN gen checks are there? To give us some ideas > > > > > if the usual pattern is range, or perhaps checks against a list of gens also > > > > > exists? (Gut feeling says no.) > > > > > > > > only cases of <=, <, >=, >. > > > > > > For these cases on patches 4 and 5:: > > > > > > What about converting all < n to <= n-1 and all > n to >= n + 1 > > > get FORVER back and introduce IS_GEN_UNTIL ? > > > > > > IS_GEN_UNTIL(dev_priv, e) > > > IS_GEN_RANGE(dev_priv, s, FOREVER) > > > > > > so we can also kill INTEL_GEN. > > > > > > Another different idea on top of that. > > > > > > What about removing all "IS_"? > > > > > > so end result could be something like that: > > > > > > INTEL_GEN(dev_priv, n) > > > DISPLAY_GEN(dev_priv, n) > > > INTEL_GEN_RANGE(dev_priv, s, e) #or e = FOREVER > > > DISPLAY_GEN_RANGE(dev_priv, s, e) #or e = FOREVER > > > INTEL_GEN_UNTIL(dev_priv, e) > > > DISPLAY_GEN_UNTIL(dev_priv, e) > > > > > > (maybe s/INTEL/GT) > > > > I like it. I'm just not sure about UNTIL, because I will always have doubts if > > it's inclusive or not. But I guess we have the same today with RANGE and we > > just get used to it. By making all of them inclusive, it will be easier. > > > > Anyway, my preference is: > > > > GT_GEN(dev_priv, n) > > GT_GEN_RANGE(dev_priv, s, e) > > and e can be GEN_FOREVER, aka -1. The macro has enough knowledge to work out > > one niptik > I prefer FOREVER alone than GEN_FOREVER because macro already has "GEN" humn... but then the macro loses context and may conflict with other use cases (not only present ones, but when we decide to add something and will need to rename FOREVER so it doesn't clutter the namespace. Today we already have REVID_FOREVER properly namespaced. > > > the mask, e.g. s == 10, e == FOREVER => mask == ~(BIT(s) | (BIT(s) - 1)) > > > > And the DISPLAY_GEN* counterparts. > > > > IMO there's no need to have _UNTIL because it can also be expressed as > > GT_GEN_RANGE(dev_priv, GEN_FOREVER, 10). > > Yeap, the GEN_FOREVER I had just killed last week covered this case, > but my brain refuses to use and accept FOREVER to something in the past. > > maybe GT_GEN_RANGE(dev_priv, 0, 10) instead of UNTIL ? yeah, that's a great idea, very clear and easy to implement. > > or GT_GEN_RANGE(dev_priv, BEGIN, 10) ? > > > > > This way we can also kill the comparisons INTEL_GEN(dev_priv) == x, so we always > > work with the gen_mask field. Which means the compiler can do a single comparison > > (/me hoping it actually generates good code) > > yeap! > > > > > There are corner cases though: > > > > What should we do with e.g. IS_GEN9_LP() and friends? > > #define GT_GEN_LP(dev_priv, n) GT_GEN(dev_priv, n) && IS_LP(dev_priv) > #define DISPLAY_GEN_LP(dev_priv, n) DISPLAY_GEN(dev_priv, n) && IS_LP(dev_priv) > #define GT_GEN_BC(dev_priv, n) GT_GEN(dev_priv, n) && !IS_LP(dev_priv) > #define DISPLAY_GEN_BC(dev_priv, n) DISPLAY_GEN(dev_priv, n) && !IS_LP(dev_priv) > > I think this would be useful to replace many IS_VALLEYVIEW || IS_CHERRYVIEW > to DISPLAY_GEN_LP(dev_priv, 7) that works for me, too. So this means in the end we have: GT_GEN(dev_priv, n) DISPLAY_GEN(dev_priv, n) GT_GEN_RANGE(dev_priv, s, e) DISPLAY_GEN_RANGE(dev_priv, s, e) With these macros implementing the special case for s == 0 and e == GEN_FOREVER GT_GEN_LP(dev_priv, n) DISPLAY_GEN_LP(dev_priv, n) thanks Lucas De Marchi > > either this above or simply kill it in favor of a more verbose version everywhere > GT_GEN(dev_priv, 9) && IS_LP(dev_priv) ?! :/ > > > > > > > Any conversion like these will create a lot of noise, not only for inflight patches, > > but also for stable backports. So IMO anything we do needs to be scriptable. > > I fully agree. > > Thanks, > Rodrigo. > > > > > Lucas De Marchi > > > > > > > > and group all of these together, because today > > > they are spreadded apart. > > > > > > Thanks, > > > Rodrigo. > > > > > > > > > > > > > > > thanks > > > > Lucas De Marchi > > > > > > > > > > > > > > Regards, > > > > > > > > > > Tvrtko > > > > > > > > > > > seq_printf(m, "DDC = 0x%08x\n", > > > > > > I915_READ(DCC)); > > > > > > seq_printf(m, "DDC2 = 0x%08x\n", > > > > > > @@ -4260,7 +4260,7 @@ i915_cache_sharing_get(void *data, u64 *val) > > > > > > struct drm_i915_private *dev_priv = data; > > > > > > u32 snpcr; > > > > > > - if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))) > > > > > > + if (!(IS_GEN(dev_priv, 6, 7))) > > > > > > return -ENODEV; > > > > > > intel_runtime_pm_get(dev_priv); > > > > > > @@ -4280,7 +4280,7 @@ i915_cache_sharing_set(void *data, u64 val) > > > > > > struct drm_i915_private *dev_priv = data; > > > > > > u32 snpcr; > > > > > > - if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))) > > > > > > + if (!(IS_GEN(dev_priv, 6, 7))) > > > > > > return -ENODEV; > > > > > > if (val > 3) > > > > > > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > > > > > > index c9f8aa47005a..969691e50c04 100644 > > > > > > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > > > > > > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > > > > > > @@ -1673,7 +1673,7 @@ static void capture_reg_state(struct i915_gpu_state *error) > > > > > > error->ccid = I915_READ(CCID); > > > > > > /* 3: Feature specific registers */ > > > > > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) { > > > > > > + if (IS_GEN(dev_priv, 6, 7)) { > > > > > > error->gam_ecochk = I915_READ(GAM_ECOCHK); > > > > > > error->gac_eco = I915_READ(GAC_ECO_BITS); > > > > > > } > > > > > > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > > > > > > index 92daddf79cb0..baaa7b70ffa0 100644 > > > > > > --- a/drivers/gpu/drm/i915/i915_perf.c > > > > > > +++ b/drivers/gpu/drm/i915/i915_perf.c > > > > > > @@ -3449,7 +3449,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) > > > > > > dev_priv->perf.oa.ops.read = gen8_oa_read; > > > > > > dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read; > > > > > > - if (IS_GEN(dev_priv, 8) || IS_GEN(dev_priv, 9)) { > > > > > > + if (IS_GEN(dev_priv, 8, 9)) { > > > > > > dev_priv->perf.oa.ops.is_valid_b_counter_reg = > > > > > > gen7_is_valid_b_counter_addr; > > > > > > dev_priv->perf.oa.ops.is_valid_mux_reg = > > > > > > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c > > > > > > index bf4fd739b68c..1822dccb1914 100644 > > > > > > --- a/drivers/gpu/drm/i915/intel_crt.c > > > > > > +++ b/drivers/gpu/drm/i915/intel_crt.c > > > > > > @@ -322,7 +322,7 @@ intel_crt_mode_valid(struct drm_connector *connector, > > > > > > * DAC limit supposedly 355 MHz. > > > > > > */ > > > > > > max_clock = 270000; > > > > > > - else if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) > > > > > > + else if (IS_GEN(dev_priv, 3, 4)) > > > > > > max_clock = 400000; > > > > > > else > > > > > > max_clock = 350000; > > > > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > > > > > > index 873f37b7b796..a1b046c322d5 100644 > > > > > > --- a/drivers/gpu/drm/i915/intel_device_info.c > > > > > > +++ b/drivers/gpu/drm/i915/intel_device_info.c > > > > > > @@ -783,7 +783,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) > > > > > > DRM_INFO("Display disabled (module parameter)\n"); > > > > > > info->num_pipes = 0; > > > > > > } else if (info->num_pipes > 0 && > > > > > > - (IS_GEN(dev_priv, 7) || IS_GEN(dev_priv, 8)) && > > > > > > + (IS_GEN(dev_priv, 7, 8)) && > > > > > > HAS_PCH_SPLIT(dev_priv)) { > > > > > > u32 fuse_strap = I915_READ(FUSE_STRAP); > > > > > > u32 sfuse_strap = I915_READ(SFUSE_STRAP); > > > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > > > > > index 84c432cbdf5b..02b338b1d8be 100644 > > > > > > --- a/drivers/gpu/drm/i915/intel_display.c > > > > > > +++ b/drivers/gpu/drm/i915/intel_display.c > > > > > > @@ -10677,7 +10677,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat > > > > > > * the w/a on all three platforms. > > > > > > */ > > > > > > if (plane->id == PLANE_SPRITE0 && > > > > > > - (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6) || > > > > > > + (IS_GEN(dev_priv, 5, 6) || > > > > > > IS_IVYBRIDGE(dev_priv)) && > > > > > > (turn_on || (!needs_scaling(old_plane_state) && > > > > > > needs_scaling(to_intel_plane_state(plane_state))))) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > > > > > > index 7642f6634f7b..779c683b48ab 100644 > > > > > > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > > > > > > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > > > > > > @@ -438,7 +438,7 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno) > > > > > > * the semaphore value, then when the seqno moves backwards all > > > > > > * future waits will complete instantly (causing rendering corruption). > > > > > > */ > > > > > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) { > > > > > > + if (IS_GEN(dev_priv, 6, 7)) { > > > > > > I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); > > > > > > I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); > > > > > > if (HAS_VEBOX(dev_priv)) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c > > > > > > index ff2743ccbece..a16b463a527d 100644 > > > > > > --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c > > > > > > +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c > > > > > > @@ -260,7 +260,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, > > > > > > if (HAS_GMCH_DISPLAY(dev_priv)) > > > > > > i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); > > > > > > - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) > > > > > > + else if (IS_GEN(dev_priv, 5, 6)) > > > > > > ironlake_set_fifo_underrun_reporting(dev, pipe, enable); > > > > > > else if (IS_GEN(dev_priv, 7)) > > > > > > ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); > > > > > > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c > > > > > > index 9e870caf8104..3e06570337b6 100644 > > > > > > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c > > > > > > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c > > > > > > @@ -433,7 +433,7 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv, > > > > > > return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val); > > > > > > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > > > > > > return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val); > > > > > > - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) > > > > > > + else if (IS_GEN(dev_priv, 5, 6)) > > > > > > return ilk_pipe_crc_ctl_reg(source, val); > > > > > > else > > > > > > return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa); > > > > > > @@ -550,7 +550,7 @@ intel_is_valid_crc_source(struct drm_i915_private *dev_priv, > > > > > > return i9xx_crc_source_valid(dev_priv, source); > > > > > > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > > > > > > return vlv_crc_source_valid(dev_priv, source); > > > > > > - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) > > > > > > + else if (IS_GEN(dev_priv, 5, 6)) > > > > > > return ilk_crc_source_valid(dev_priv, source); > > > > > > else > > > > > > return ivb_crc_source_valid(dev_priv, source); > > > > > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > > > > > > index c36453d66d93..88cbd32d6964 100644 > > > > > > --- a/drivers/gpu/drm/i915/intel_uncore.c > > > > > > +++ b/drivers/gpu/drm/i915/intel_uncore.c > > > > > > @@ -528,7 +528,7 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) > > > > > > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > > > > > > ret |= vlv_check_for_unclaimed_mmio(dev_priv); > > > > > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) > > > > > > + if (IS_GEN(dev_priv, 6, 7)) > > > > > > ret |= gen6_check_for_fifo_debug(dev_priv); > > > > > > return ret; > > > > > > @@ -556,7 +556,7 @@ static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, > > > > > > dev_priv->uncore.funcs.force_wake_get(dev_priv, > > > > > > restore_forcewake); > > > > > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) > > > > > > + if (IS_GEN(dev_priv, 6, 7)) > > > > > > dev_priv->uncore.fifo_count = > > > > > > fifo_free_entries(dev_priv); > > > > > > spin_unlock_irq(&dev_priv->uncore.lock); > > > > > > @@ -1437,7 +1437,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) > > > > > > FORCEWAKE_MEDIA_VEBOX_GEN11(i), > > > > > > FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); > > > > > > } > > > > > > - } else if (IS_GEN(dev_priv, 10) || IS_GEN(dev_priv, 9)) { > > > > > > + } else if (IS_GEN(dev_priv, 9, 10)) { > > > > > > dev_priv->uncore.funcs.force_wake_get = > > > > > > fw_domains_get_with_fallback; > > > > > > dev_priv->uncore.funcs.force_wake_put = fw_domains_put; > > > > > > > > > > > _______________________________________________ > > > > > Intel-gfx mailing list > > > > > Intel-gfx@lists.freedesktop.org > > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/5] drm/i915: merge gen checks to use range 2018-11-02 22:28 ` Lucas De Marchi @ 2018-11-02 22:47 ` Rodrigo Vivi 0 siblings, 0 replies; 23+ messages in thread From: Rodrigo Vivi @ 2018-11-02 22:47 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx, Lucas De Marchi On Fri, Nov 02, 2018 at 03:28:00PM -0700, Lucas De Marchi wrote: > On Fri, Nov 02, 2018 at 03:12:18PM -0700, Rodrigo Vivi wrote: > > On Fri, Nov 02, 2018 at 12:47:28PM -0700, Lucas De Marchi wrote: > > > On Fri, Nov 02, 2018 at 12:19:13PM -0700, Rodrigo Vivi wrote: > > > > On Fri, Nov 02, 2018 at 11:10:10AM -0700, Lucas De Marchi wrote: > > > > > On Thu, Nov 01, 2018 at 11:31:25AM +0000, Tvrtko Ursulin wrote: > > > > > > > > > > > > On 01/11/2018 08:35, Lucas De Marchi wrote: > > > > > > > Instead of using several IS_GEN(), it's possible to pass the > > > > > > > range as argument. By code inspection these were the ranges deemed > > > > > > > necessary for spatch: > > > > > > > > > > > > > > @@ > > > > > > > expression e; > > > > > > > @@ > > > > > > > ( > > > > > > > - IS_GEN(e, 3) || IS_GEN(e, 4) > > > > > > > + IS_GEN(e, 3, 4) > > > > > > > | > > > > > > > - IS_GEN(e, 5) || IS_GEN(e, 6) > > > > > > > + IS_GEN(e, 5, 6) > > > > > > > | > > > > > > > - IS_GEN(e, 6) || IS_GEN(e, 7) > > > > > > > + IS_GEN(e, 6, 7) > > > > > > > | > > > > > > > - IS_GEN(e, 7) || IS_GEN(e, 8) > > > > > > > + IS_GEN(e, 7, 8) > > > > > > > | > > > > > > > - IS_GEN(e, 8) || IS_GEN(e, 9) > > > > > > > + IS_GEN(e, 8, 9) > > > > > > > | > > > > > > > - IS_GEN(e, 10) || IS_GEN(e, 9) > > > > > > > + IS_GEN(e, 9, 10) > > > > > > > | > > > > > > > - IS_GEN(e, 9) || IS_GEN(e, 10) > > > > > > > + IS_GEN(e, 9, 10) > > > > > > > ) > > > > > > > > > > > > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > > > > > > > --- > > > > > > > drivers/gpu/drm/i915/i915_debugfs.c | 6 +++--- > > > > > > > drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- > > > > > > > drivers/gpu/drm/i915/i915_perf.c | 2 +- > > > > > > > drivers/gpu/drm/i915/intel_crt.c | 2 +- > > > > > > > drivers/gpu/drm/i915/intel_device_info.c | 2 +- > > > > > > > drivers/gpu/drm/i915/intel_display.c | 2 +- > > > > > > > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- > > > > > > > drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +- > > > > > > > drivers/gpu/drm/i915/intel_pipe_crc.c | 4 ++-- > > > > > > > drivers/gpu/drm/i915/intel_uncore.c | 6 +++--- > > > > > > > 10 files changed, 15 insertions(+), 15 deletions(-) > > > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > > > > > > > index 28d95f9d0b0e..f2fbc016bd7f 100644 > > > > > > > --- a/drivers/gpu/drm/i915/i915_debugfs.c > > > > > > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > > > > > > > @@ -2030,7 +2030,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) > > > > > > > seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", > > > > > > > swizzle_string(dev_priv->mm.bit_6_swizzle_y)); > > > > > > > - if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) { > > > > > > > + if (IS_GEN(dev_priv, 3, 4)) { > > > > > > > > > > > > I can see value in it but think it would read better with IS_GEN_RANGE. > > > > > > > > > > Ok, it seems there's a rough consensus of s/IS_GEN/IS_GEN_RANGE/ an then > > > > > bring the patches that make sense here. There was a recent patch from Rodrigo > > > > > doing that. I'll include it in next version. > > > > > > > > I liked the double args idea but after reading I believe > > > > it gets clear IS_GEN_RANGE. > > > > > > > > > > > > > > > > > > > > > Are there any cases of or-ed IS_GEN checks with something sandwiched in > > > > > > between then, which the above spatch would miss? > > > > > > > > > > By manually inspecting the result of ``git grep -ne "IS_GEN(.*" -- drivers/gpu/drm/i915/`` > > > > > I didn't find any. The only thing I found was a missed case for gen3 || gen2 > > > > > that was not covered by the spatch. > > > > > > > > > > > > > > > > > How many non-consecutive IS_GEN gen checks are there? To give us some ideas > > > > > > if the usual pattern is range, or perhaps checks against a list of gens also > > > > > > exists? (Gut feeling says no.) > > > > > > > > > > only cases of <=, <, >=, >. > > > > > > > > For these cases on patches 4 and 5:: > > > > > > > > What about converting all < n to <= n-1 and all > n to >= n + 1 > > > > get FORVER back and introduce IS_GEN_UNTIL ? > > > > > > > > IS_GEN_UNTIL(dev_priv, e) > > > > IS_GEN_RANGE(dev_priv, s, FOREVER) > > > > > > > > so we can also kill INTEL_GEN. > > > > > > > > Another different idea on top of that. > > > > > > > > What about removing all "IS_"? > > > > > > > > so end result could be something like that: > > > > > > > > INTEL_GEN(dev_priv, n) > > > > DISPLAY_GEN(dev_priv, n) > > > > INTEL_GEN_RANGE(dev_priv, s, e) #or e = FOREVER > > > > DISPLAY_GEN_RANGE(dev_priv, s, e) #or e = FOREVER > > > > INTEL_GEN_UNTIL(dev_priv, e) > > > > DISPLAY_GEN_UNTIL(dev_priv, e) > > > > > > > > (maybe s/INTEL/GT) > > > > > > I like it. I'm just not sure about UNTIL, because I will always have doubts if > > > it's inclusive or not. But I guess we have the same today with RANGE and we > > > just get used to it. By making all of them inclusive, it will be easier. > > > > > > Anyway, my preference is: > > > > > > GT_GEN(dev_priv, n) > > > GT_GEN_RANGE(dev_priv, s, e) > > > and e can be GEN_FOREVER, aka -1. The macro has enough knowledge to work out > > > > one niptik > > I prefer FOREVER alone than GEN_FOREVER because macro already has "GEN" > > humn... but then the macro loses context and may conflict with other use cases > (not only present ones, but when we decide to add something and will need to > rename FOREVER so it doesn't clutter the namespace. Today we already have > REVID_FOREVER properly namespaced. dam... you are right.... so just revert my patch? git revert 5bc0e89ff1be # ("drm/i915: Kill GEN_FOREVER") (stupid Rodrigo rushed this in without much discussion :P) > > > > > > > the mask, e.g. s == 10, e == FOREVER => mask == ~(BIT(s) | (BIT(s) - 1)) > > > > > > And the DISPLAY_GEN* counterparts. > > > > > > IMO there's no need to have _UNTIL because it can also be expressed as > > > GT_GEN_RANGE(dev_priv, GEN_FOREVER, 10). > > > > Yeap, the GEN_FOREVER I had just killed last week covered this case, > > but my brain refuses to use and accept FOREVER to something in the past. > > > > maybe GT_GEN_RANGE(dev_priv, 0, 10) instead of UNTIL ? > > yeah, that's a great idea, very clear and easy to implement. > > > > > or GT_GEN_RANGE(dev_priv, BEGIN, 10) ? > > > > > > > > This way we can also kill the comparisons INTEL_GEN(dev_priv) == x, so we always > > > work with the gen_mask field. Which means the compiler can do a single comparison > > > (/me hoping it actually generates good code) > > > > yeap! > > > > > > > > There are corner cases though: > > > > > > What should we do with e.g. IS_GEN9_LP() and friends? > > > > #define GT_GEN_LP(dev_priv, n) GT_GEN(dev_priv, n) && IS_LP(dev_priv) > > #define DISPLAY_GEN_LP(dev_priv, n) DISPLAY_GEN(dev_priv, n) && IS_LP(dev_priv) > > #define GT_GEN_BC(dev_priv, n) GT_GEN(dev_priv, n) && !IS_LP(dev_priv) > > #define DISPLAY_GEN_BC(dev_priv, n) DISPLAY_GEN(dev_priv, n) && !IS_LP(dev_priv) > > > > I think this would be useful to replace many IS_VALLEYVIEW || IS_CHERRYVIEW > > to DISPLAY_GEN_LP(dev_priv, 7) > > that works for me, too. So this means in the end we have: > > GT_GEN(dev_priv, n) > DISPLAY_GEN(dev_priv, n) > > GT_GEN_RANGE(dev_priv, s, e) > DISPLAY_GEN_RANGE(dev_priv, s, e) > > With these macros implementing the special case for s == 0 and e == GEN_FOREVER > > GT_GEN_LP(dev_priv, n) > DISPLAY_GEN_LP(dev_priv, n) > > thanks > Lucas De Marchi > > > > > either this above or simply kill it in favor of a more verbose version everywhere > > GT_GEN(dev_priv, 9) && IS_LP(dev_priv) ?! :/ > > > > > > > > > > > Any conversion like these will create a lot of noise, not only for inflight patches, > > > but also for stable backports. So IMO anything we do needs to be scriptable. > > > > I fully agree. > > > > Thanks, > > Rodrigo. > > > > > > > > Lucas De Marchi > > > > > > > > > > > and group all of these together, because today > > > > they are spreadded apart. > > > > > > > > Thanks, > > > > Rodrigo. > > > > > > > > > > > > > > > > > > > thanks > > > > > Lucas De Marchi > > > > > > > > > > > > > > > > > Regards, > > > > > > > > > > > > Tvrtko > > > > > > > > > > > > > seq_printf(m, "DDC = 0x%08x\n", > > > > > > > I915_READ(DCC)); > > > > > > > seq_printf(m, "DDC2 = 0x%08x\n", > > > > > > > @@ -4260,7 +4260,7 @@ i915_cache_sharing_get(void *data, u64 *val) > > > > > > > struct drm_i915_private *dev_priv = data; > > > > > > > u32 snpcr; > > > > > > > - if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))) > > > > > > > + if (!(IS_GEN(dev_priv, 6, 7))) > > > > > > > return -ENODEV; > > > > > > > intel_runtime_pm_get(dev_priv); > > > > > > > @@ -4280,7 +4280,7 @@ i915_cache_sharing_set(void *data, u64 val) > > > > > > > struct drm_i915_private *dev_priv = data; > > > > > > > u32 snpcr; > > > > > > > - if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))) > > > > > > > + if (!(IS_GEN(dev_priv, 6, 7))) > > > > > > > return -ENODEV; > > > > > > > if (val > 3) > > > > > > > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > > > > > > > index c9f8aa47005a..969691e50c04 100644 > > > > > > > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > > > > > > > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > > > > > > > @@ -1673,7 +1673,7 @@ static void capture_reg_state(struct i915_gpu_state *error) > > > > > > > error->ccid = I915_READ(CCID); > > > > > > > /* 3: Feature specific registers */ > > > > > > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) { > > > > > > > + if (IS_GEN(dev_priv, 6, 7)) { > > > > > > > error->gam_ecochk = I915_READ(GAM_ECOCHK); > > > > > > > error->gac_eco = I915_READ(GAC_ECO_BITS); > > > > > > > } > > > > > > > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > > > > > > > index 92daddf79cb0..baaa7b70ffa0 100644 > > > > > > > --- a/drivers/gpu/drm/i915/i915_perf.c > > > > > > > +++ b/drivers/gpu/drm/i915/i915_perf.c > > > > > > > @@ -3449,7 +3449,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) > > > > > > > dev_priv->perf.oa.ops.read = gen8_oa_read; > > > > > > > dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read; > > > > > > > - if (IS_GEN(dev_priv, 8) || IS_GEN(dev_priv, 9)) { > > > > > > > + if (IS_GEN(dev_priv, 8, 9)) { > > > > > > > dev_priv->perf.oa.ops.is_valid_b_counter_reg = > > > > > > > gen7_is_valid_b_counter_addr; > > > > > > > dev_priv->perf.oa.ops.is_valid_mux_reg = > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c > > > > > > > index bf4fd739b68c..1822dccb1914 100644 > > > > > > > --- a/drivers/gpu/drm/i915/intel_crt.c > > > > > > > +++ b/drivers/gpu/drm/i915/intel_crt.c > > > > > > > @@ -322,7 +322,7 @@ intel_crt_mode_valid(struct drm_connector *connector, > > > > > > > * DAC limit supposedly 355 MHz. > > > > > > > */ > > > > > > > max_clock = 270000; > > > > > > > - else if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) > > > > > > > + else if (IS_GEN(dev_priv, 3, 4)) > > > > > > > max_clock = 400000; > > > > > > > else > > > > > > > max_clock = 350000; > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > > > > > > > index 873f37b7b796..a1b046c322d5 100644 > > > > > > > --- a/drivers/gpu/drm/i915/intel_device_info.c > > > > > > > +++ b/drivers/gpu/drm/i915/intel_device_info.c > > > > > > > @@ -783,7 +783,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) > > > > > > > DRM_INFO("Display disabled (module parameter)\n"); > > > > > > > info->num_pipes = 0; > > > > > > > } else if (info->num_pipes > 0 && > > > > > > > - (IS_GEN(dev_priv, 7) || IS_GEN(dev_priv, 8)) && > > > > > > > + (IS_GEN(dev_priv, 7, 8)) && > > > > > > > HAS_PCH_SPLIT(dev_priv)) { > > > > > > > u32 fuse_strap = I915_READ(FUSE_STRAP); > > > > > > > u32 sfuse_strap = I915_READ(SFUSE_STRAP); > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > > > > > > index 84c432cbdf5b..02b338b1d8be 100644 > > > > > > > --- a/drivers/gpu/drm/i915/intel_display.c > > > > > > > +++ b/drivers/gpu/drm/i915/intel_display.c > > > > > > > @@ -10677,7 +10677,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat > > > > > > > * the w/a on all three platforms. > > > > > > > */ > > > > > > > if (plane->id == PLANE_SPRITE0 && > > > > > > > - (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6) || > > > > > > > + (IS_GEN(dev_priv, 5, 6) || > > > > > > > IS_IVYBRIDGE(dev_priv)) && > > > > > > > (turn_on || (!needs_scaling(old_plane_state) && > > > > > > > needs_scaling(to_intel_plane_state(plane_state))))) > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > > > > > > > index 7642f6634f7b..779c683b48ab 100644 > > > > > > > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > > > > > > > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > > > > > > > @@ -438,7 +438,7 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno) > > > > > > > * the semaphore value, then when the seqno moves backwards all > > > > > > > * future waits will complete instantly (causing rendering corruption). > > > > > > > */ > > > > > > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) { > > > > > > > + if (IS_GEN(dev_priv, 6, 7)) { > > > > > > > I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); > > > > > > > I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); > > > > > > > if (HAS_VEBOX(dev_priv)) > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c > > > > > > > index ff2743ccbece..a16b463a527d 100644 > > > > > > > --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c > > > > > > > +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c > > > > > > > @@ -260,7 +260,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, > > > > > > > if (HAS_GMCH_DISPLAY(dev_priv)) > > > > > > > i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); > > > > > > > - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) > > > > > > > + else if (IS_GEN(dev_priv, 5, 6)) > > > > > > > ironlake_set_fifo_underrun_reporting(dev, pipe, enable); > > > > > > > else if (IS_GEN(dev_priv, 7)) > > > > > > > ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c > > > > > > > index 9e870caf8104..3e06570337b6 100644 > > > > > > > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c > > > > > > > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c > > > > > > > @@ -433,7 +433,7 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv, > > > > > > > return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val); > > > > > > > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > > > > > > > return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val); > > > > > > > - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) > > > > > > > + else if (IS_GEN(dev_priv, 5, 6)) > > > > > > > return ilk_pipe_crc_ctl_reg(source, val); > > > > > > > else > > > > > > > return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa); > > > > > > > @@ -550,7 +550,7 @@ intel_is_valid_crc_source(struct drm_i915_private *dev_priv, > > > > > > > return i9xx_crc_source_valid(dev_priv, source); > > > > > > > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > > > > > > > return vlv_crc_source_valid(dev_priv, source); > > > > > > > - else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6)) > > > > > > > + else if (IS_GEN(dev_priv, 5, 6)) > > > > > > > return ilk_crc_source_valid(dev_priv, source); > > > > > > > else > > > > > > > return ivb_crc_source_valid(dev_priv, source); > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > > > > > > > index c36453d66d93..88cbd32d6964 100644 > > > > > > > --- a/drivers/gpu/drm/i915/intel_uncore.c > > > > > > > +++ b/drivers/gpu/drm/i915/intel_uncore.c > > > > > > > @@ -528,7 +528,7 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) > > > > > > > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > > > > > > > ret |= vlv_check_for_unclaimed_mmio(dev_priv); > > > > > > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) > > > > > > > + if (IS_GEN(dev_priv, 6, 7)) > > > > > > > ret |= gen6_check_for_fifo_debug(dev_priv); > > > > > > > return ret; > > > > > > > @@ -556,7 +556,7 @@ static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, > > > > > > > dev_priv->uncore.funcs.force_wake_get(dev_priv, > > > > > > > restore_forcewake); > > > > > > > - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) > > > > > > > + if (IS_GEN(dev_priv, 6, 7)) > > > > > > > dev_priv->uncore.fifo_count = > > > > > > > fifo_free_entries(dev_priv); > > > > > > > spin_unlock_irq(&dev_priv->uncore.lock); > > > > > > > @@ -1437,7 +1437,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) > > > > > > > FORCEWAKE_MEDIA_VEBOX_GEN11(i), > > > > > > > FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); > > > > > > > } > > > > > > > - } else if (IS_GEN(dev_priv, 10) || IS_GEN(dev_priv, 9)) { > > > > > > > + } else if (IS_GEN(dev_priv, 9, 10)) { > > > > > > > dev_priv->uncore.funcs.force_wake_get = > > > > > > > fw_domains_get_with_fallback; > > > > > > > dev_priv->uncore.funcs.force_wake_put = fw_domains_put; > > > > > > > > > > > > > _______________________________________________ > > > > > > Intel-gfx mailing list > > > > > > Intel-gfx@lists.freedesktop.org > > > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 4/5] drm/i915: add helper IS_GEN_* macros 2018-11-01 8:35 [PATCH 0/5] Make GEN macros more similar Lucas De Marchi ` (2 preceding siblings ...) 2018-11-01 8:35 ` [PATCH 3/5] drm/i915: merge gen checks to use range Lucas De Marchi @ 2018-11-01 8:35 ` Lucas De Marchi 2018-11-01 11:04 ` Tvrtko Ursulin 2018-11-01 8:35 ` [PATCH 5/5] RFC: drm/i915: convert a few cases to the " Lucas De Marchi ` (3 subsequent siblings) 7 siblings, 1 reply; 23+ messages in thread From: Lucas De Marchi @ 2018-11-01 8:35 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi This will allow us to make all gen comparisons simple gen comparisons with the same kind of macro rather than resorting to a mix of IS_GEN(), INTEL_GEN() >=, >, <=, <. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 8d22353a3da6..eb636dfe5228 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2370,6 +2370,11 @@ intel_info(const struct drm_i915_private *dev_priv) #define IS_GEN(dev_priv, ...) \ CONCATENATE(_IS_GEN_ARG, COUNT_ARGS(__VA_ARGS__))((dev_priv), ##__VA_ARGS__) +#define IS_GEN_GT(dev_priv, g) (g > (dev_priv)->info.gen) +#define IS_GEN_GE(dev_priv, g) (g >= (dev_priv)->info.gen) +#define IS_GEN_LT(dev_priv, g) (g < (dev_priv)->info.gen) +#define IS_GEN_LE(dev_priv, g) (g <= (dev_priv)->info.gen) + /* * Return true if revision is in range [since,until] inclusive. * -- 2.19.1.1.g56c4683e68 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 4/5] drm/i915: add helper IS_GEN_* macros 2018-11-01 8:35 ` [PATCH 4/5] drm/i915: add helper IS_GEN_* macros Lucas De Marchi @ 2018-11-01 11:04 ` Tvrtko Ursulin 2018-11-01 11:29 ` Jani Nikula 0 siblings, 1 reply; 23+ messages in thread From: Tvrtko Ursulin @ 2018-11-01 11:04 UTC (permalink / raw) To: Lucas De Marchi, intel-gfx; +Cc: Rodrigo Vivi On 01/11/2018 08:35, Lucas De Marchi wrote: > This will allow us to make all gen comparisons simple gen comparisons > with the same kind of macro rather than resorting to a mix of IS_GEN(), > INTEL_GEN() >=, >, <=, <. > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 8d22353a3da6..eb636dfe5228 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2370,6 +2370,11 @@ intel_info(const struct drm_i915_private *dev_priv) > #define IS_GEN(dev_priv, ...) \ > CONCATENATE(_IS_GEN_ARG, COUNT_ARGS(__VA_ARGS__))((dev_priv), ##__VA_ARGS__) > > +#define IS_GEN_GT(dev_priv, g) (g > (dev_priv)->info.gen) Interesting :), I have at some point floated a similar patch and there was overwhelming dislike of the GT suffix, since we have GT2 GT3 etc.. as established acronyms for GPU configurations. Furthermore, I am pretty sure I've done it using the gen bitmask so hypothetical checks like IS_GEN_LT(5) || IS_GEN_RANGE(8, 9) could still be compile time optimized to a single conditional. That would also now become more difficult due removal of GEN_FOREVER. To summarise, I don't see a advantage of hiding this in macros if we are not getting the above benefit. Regards, Tvrtko > +#define IS_GEN_GE(dev_priv, g) (g >= (dev_priv)->info.gen) > +#define IS_GEN_LT(dev_priv, g) (g < (dev_priv)->info.gen) > +#define IS_GEN_LE(dev_priv, g) (g <= (dev_priv)->info.gen) > + > /* > * Return true if revision is in range [since,until] inclusive. > * > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 4/5] drm/i915: add helper IS_GEN_* macros 2018-11-01 11:04 ` Tvrtko Ursulin @ 2018-11-01 11:29 ` Jani Nikula 0 siblings, 0 replies; 23+ messages in thread From: Jani Nikula @ 2018-11-01 11:29 UTC (permalink / raw) To: Tvrtko Ursulin, Lucas De Marchi, intel-gfx; +Cc: Rodrigo Vivi On Thu, 01 Nov 2018, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote: > On 01/11/2018 08:35, Lucas De Marchi wrote: >> This will allow us to make all gen comparisons simple gen comparisons >> with the same kind of macro rather than resorting to a mix of IS_GEN(), >> INTEL_GEN() >=, >, <=, <. >> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> >> --- >> drivers/gpu/drm/i915/i915_drv.h | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h >> index 8d22353a3da6..eb636dfe5228 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.h >> +++ b/drivers/gpu/drm/i915/i915_drv.h >> @@ -2370,6 +2370,11 @@ intel_info(const struct drm_i915_private *dev_priv) >> #define IS_GEN(dev_priv, ...) \ >> CONCATENATE(_IS_GEN_ARG, COUNT_ARGS(__VA_ARGS__))((dev_priv), ##__VA_ARGS__) >> >> +#define IS_GEN_GT(dev_priv, g) (g > (dev_priv)->info.gen) > > Interesting :), I have at some point floated a similar patch and there > was overwhelming dislike of the GT suffix, since we have GT2 GT3 etc.. > as established acronyms for GPU configurations. To be honest even *without* the GPU GT clash, I think GT/GE/LT/LE are a cognitive burden. Not a big one, but still less natural than >/>=/</<=. Feels like assembly. Not that I have better alternatives. IS_GEN_AFTER for GT, IS_GEN_OR_LATER for GE? Feels a bit contrived? > Furthermore, I am pretty sure I've done it using the gen bitmask so > hypothetical checks like IS_GEN_LT(5) || IS_GEN_RANGE(8, 9) could still > be compile time optimized to a single conditional. That would also now > become more difficult due removal of GEN_FOREVER. > > To summarise, I don't see a advantage of hiding this in macros if we are > not getting the above benefit. Agreed. I didn't realize the GEN_FOREVER removal was merged already, I wish you'd chimed in there. Of course, we can bring it back. BR, Jani. > > Regards, > > Tvrtko > >> +#define IS_GEN_GE(dev_priv, g) (g >= (dev_priv)->info.gen) >> +#define IS_GEN_LT(dev_priv, g) (g < (dev_priv)->info.gen) >> +#define IS_GEN_LE(dev_priv, g) (g <= (dev_priv)->info.gen) >> + >> /* >> * Return true if revision is in range [since,until] inclusive. >> * >> -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 5/5] RFC: drm/i915: convert a few cases to the helper IS_GEN_* macros 2018-11-01 8:35 [PATCH 0/5] Make GEN macros more similar Lucas De Marchi ` (3 preceding siblings ...) 2018-11-01 8:35 ` [PATCH 4/5] drm/i915: add helper IS_GEN_* macros Lucas De Marchi @ 2018-11-01 8:35 ` Lucas De Marchi 2018-11-01 9:30 ` ✗ Fi.CI.CHECKPATCH: warning for Make GEN macros more similar Patchwork ` (2 subsequent siblings) 7 siblings, 0 replies; 23+ messages in thread From: Lucas De Marchi @ 2018-11-01 8:35 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi Just for checking the final result, convert the >= 9 cases. @@ expression E; @@ - INTEL_GEN(dev_priv) >= 9 + IS_GEN_GE(dev_priv, 9) Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 26 ++++++++--------- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- drivers/gpu/drm/i915/i915_irq.c | 6 ++-- drivers/gpu/drm/i915/i915_reg.h | 4 +-- drivers/gpu/drm/i915/intel_cdclk.c | 2 +- drivers/gpu/drm/i915/intel_ddi.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 42 ++++++++++++++-------------- drivers/gpu/drm/i915/intel_dp.c | 8 +++--- drivers/gpu/drm/i915/intel_fbc.c | 2 +- drivers/gpu/drm/i915/intel_i2c.c | 2 +- drivers/gpu/drm/i915/intel_lrc.c | 2 +- drivers/gpu/drm/i915/intel_mocs.c | 2 +- drivers/gpu/drm/i915/intel_pm.c | 26 ++++++++--------- drivers/gpu/drm/i915/intel_psr.c | 6 ++-- drivers/gpu/drm/i915/intel_sprite.c | 8 +++--- drivers/gpu/drm/i915/intel_uncore.c | 4 +-- 17 files changed, 73 insertions(+), 73 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index f2fbc016bd7f..75a587c57e7d 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1135,7 +1135,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); reqf = I915_READ(GEN6_RPNSWREQ); - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) reqf >>= 23; else { reqf &= ~GEN6_TURBO_DISABLE; @@ -1201,7 +1201,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) rps->pm_intrmsk_mbz); seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); seq_printf(m, "Render p-state ratio: %d\n", - (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8); + (gt_perf_status & (IS_GEN_GE(dev_priv, 9) ? 0x1ff00 : 0xff00)) >> 8); seq_printf(m, "Render p-state VID: %d\n", gt_perf_status & 0xff); seq_printf(m, "Render p-state limit: %d\n", @@ -1535,7 +1535,7 @@ static int gen6_drpc_info(struct seq_file *m) trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); rcctl1 = I915_READ(GEN6_RC_CONTROL); - if (INTEL_GEN(dev_priv) >= 9) { + if (IS_GEN_GE(dev_priv, 9)) { gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); } @@ -1551,7 +1551,7 @@ static int gen6_drpc_info(struct seq_file *m) yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); seq_printf(m, "RC6 Enabled: %s\n", yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); - if (INTEL_GEN(dev_priv) >= 9) { + if (IS_GEN_GE(dev_priv, 9)) { seq_printf(m, "Render Well Gating Enabled: %s\n", yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); seq_printf(m, "Media Well Gating Enabled: %s\n", @@ -1585,7 +1585,7 @@ static int gen6_drpc_info(struct seq_file *m) seq_printf(m, "Core Power Down: %s\n", yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); - if (INTEL_GEN(dev_priv) >= 9) { + if (IS_GEN_GE(dev_priv, 9)) { seq_printf(m, "Render Power Well: %s\n", (gen9_powergate_status & GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); @@ -1756,7 +1756,7 @@ static int i915_sr_status(struct seq_file *m, void *unused) intel_runtime_pm_get(dev_priv); intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) /* no global SR status; inspect per-plane WM */; else if (HAS_PCH_SPLIT(dev_priv)) sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; @@ -3810,7 +3810,7 @@ static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) * - WM1+ latency values in 0.5us units * - latencies are in us on gen9/vlv/chv */ - if (INTEL_GEN(dev_priv) >= 9 || + if (IS_GEN_GE(dev_priv, 9) || IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || IS_G4X(dev_priv)) @@ -3830,7 +3830,7 @@ static int pri_wm_latency_show(struct seq_file *m, void *data) struct drm_i915_private *dev_priv = m->private; const uint16_t *latencies; - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) latencies = dev_priv->wm.skl_latency; else latencies = dev_priv->wm.pri_latency; @@ -3845,7 +3845,7 @@ static int spr_wm_latency_show(struct seq_file *m, void *data) struct drm_i915_private *dev_priv = m->private; const uint16_t *latencies; - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) latencies = dev_priv->wm.skl_latency; else latencies = dev_priv->wm.spr_latency; @@ -3860,7 +3860,7 @@ static int cur_wm_latency_show(struct seq_file *m, void *data) struct drm_i915_private *dev_priv = m->private; const uint16_t *latencies; - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) latencies = dev_priv->wm.skl_latency; else latencies = dev_priv->wm.cur_latency; @@ -3953,7 +3953,7 @@ static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, struct drm_i915_private *dev_priv = m->private; uint16_t *latencies; - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) latencies = dev_priv->wm.skl_latency; else latencies = dev_priv->wm.pri_latency; @@ -3968,7 +3968,7 @@ static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, struct drm_i915_private *dev_priv = m->private; uint16_t *latencies; - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) latencies = dev_priv->wm.skl_latency; else latencies = dev_priv->wm.spr_latency; @@ -3983,7 +3983,7 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, struct drm_i915_private *dev_priv = m->private; uint16_t *latencies; - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) latencies = dev_priv->wm.skl_latency; else latencies = dev_priv->wm.cur_latency; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index eb636dfe5228..ce1cd3e6a27f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2708,7 +2708,7 @@ intel_info(const struct drm_i915_private *dev_priv) #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display) -#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) +#define HAS_LSPCON(dev_priv) (IS_GEN_GE(dev_priv, 9)) /* DPF == dynamic parity feature */ #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index b887fa51f801..9b8972d8a2d0 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2170,7 +2170,7 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); else if (IS_GEN9_LP(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); - else if (INTEL_GEN(dev_priv) >= 9) + else if (IS_GEN_GE(dev_priv, 9)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); /* diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 068cccb3aba8..2724f092c5f0 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2774,7 +2774,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) ret = IRQ_HANDLED; tmp_mask = GEN8_AUX_CHANNEL_A; - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) tmp_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | GEN9_AUX_CHANNEL_D; @@ -2844,7 +2844,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); fault_errors = iir; - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS; else fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS; @@ -4207,7 +4207,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) if (INTEL_GEN(dev_priv) <= 10) de_misc_masked |= GEN8_DE_MISC_GSE; - if (INTEL_GEN(dev_priv) >= 9) { + if (IS_GEN_GE(dev_priv, 9)) { de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS; de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | GEN9_AUX_CHANNEL_D; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8d089ef848b2..723dd92d556f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3787,7 +3787,7 @@ enum i915_power_well_id { #define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25) #define INTERVAL_1_33_US(us) (((us) * 3) >> 2) #define INTERVAL_0_833_US(us) (((us) * 6) / 5) -#define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \ +#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN_GE(dev_priv, 9) ? \ (IS_GEN9_LP(dev_priv) ? \ INTERVAL_0_833_US(us) : \ INTERVAL_1_33_US(us)) : \ @@ -3796,7 +3796,7 @@ enum i915_power_well_id { #define INTERVAL_1_28_TO_US(interval) (((interval) << 7) / 100) #define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3) #define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6) -#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \ +#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN_GE(dev_priv, 9) ? \ (IS_GEN9_LP(dev_priv) ? \ INTERVAL_0_833_TO_US(interval) : \ INTERVAL_1_33_TO_US(interval)) : \ diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index b9a3a2312686..e99582a91d37 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -2197,7 +2197,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) * at probe time. If we probe without displays, we'll still end up using * the platform minimum CDCLK, failing audio probe. */ - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) min_cdclk = max(2 * 96000, min_cdclk); /* diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index e40a8c97d34b..b563028f4120 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2931,7 +2931,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, if (!is_mst) intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); intel_dp_start_link_train(intel_dp); - if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) + if (port != PORT_A || IS_GEN_GE(dev_priv, 9)) intel_dp_stop_link_train(intel_dp); icl_enable_phy_clock_gating(dig_port); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 02b338b1d8be..a4ed8c37eedc 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1983,7 +1983,7 @@ static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_pr static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) { - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) return 256 * 1024; else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) || IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) @@ -2007,7 +2007,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, case DRM_FORMAT_MOD_LINEAR: return intel_linear_alignment(dev_priv); case I915_FORMAT_MOD_X_TILED: - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) return 256 * 1024; return 0; case I915_FORMAT_MOD_Y_TILED_CCS: @@ -3870,7 +3870,7 @@ static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta (new_crtc_state->pipe_src_h - 1)); /* on skylake this is done by detaching scalers */ - if (INTEL_GEN(dev_priv) >= 9) { + if (IS_GEN_GE(dev_priv, 9)) { skl_detach_scalers(new_crtc_state); if (new_crtc_state->pch_pfit.enabled) @@ -4835,7 +4835,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, * Once NV12 is enabled, handle it here while allocating scaler * for NV12. */ - if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable && + if (IS_GEN_GE(dev_priv, 9) && crtc_state->base.enable && need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n"); return -EINVAL; @@ -5709,7 +5709,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, if (psl_clkgate_wa) glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) skylake_pfit_enable(pipe_config); else ironlake_pfit_enable(pipe_config); @@ -5867,7 +5867,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, if (!transcoder_is_dsi(cpu_transcoder)) intel_ddi_disable_transcoder_func(old_crtc_state); - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) skylake_scaler_disable(intel_crtc); else ironlake_pfit_disable(old_crtc_state); @@ -7820,7 +7820,7 @@ static void intel_get_crtc_ycbcr_config(struct intel_crtc *crtc, pipe_config->lspcon_downsampling = false; - if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) { + if (IS_BROADWELL(dev_priv) || IS_GEN_GE(dev_priv, 9)) { u32 tmp = I915_READ(PIPEMISC(crtc->pipe)); if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) { @@ -8465,7 +8465,7 @@ static void haswell_set_pipemisc(const struct intel_crtc_state *crtc_state) struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); - if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) { + if (IS_BROADWELL(dev_priv) || IS_GEN_GE(dev_priv, 9)) { u32 val = 0; switch (crtc_state->pipe_bpp) { @@ -9546,7 +9546,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { power_domain_mask |= BIT_ULL(power_domain); - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) skylake_get_pfit_config(crtc, pipe_config); else ironlake_get_pfit_config(crtc, pipe_config); @@ -10573,7 +10573,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat struct drm_framebuffer *fb = plane_state->fb; int ret; - if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { + if (IS_GEN_GE(dev_priv, 9) && plane->id != PLANE_CURSOR) { ret = skl_update_scaler_plane( to_intel_crtc_state(crtc_state), to_intel_plane_state(plane_state)); @@ -10875,7 +10875,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; } - if (INTEL_GEN(dev_priv) >= 9) { + if (IS_GEN_GE(dev_priv, 9)) { if (mode_changed) ret = skl_update_scaler_crtc(pipe_config); @@ -11119,7 +11119,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, pipe_config->pipe_src_w, pipe_config->pipe_src_h, pipe_config->pixel_rate); - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", crtc->num_scalers, pipe_config->scaler_state.scaler_users, @@ -11160,7 +11160,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, plane->base.id, plane->name, fb->base.id, fb->width, fb->height, drm_get_format_name(fb->format->format, &format_name)); - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", state->scaler_id, state->base.src.x1 >> 16, @@ -12829,7 +12829,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) * * No clue what this is supposed to achieve. */ - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) dev_priv->display.initial_watermarks(intel_state, new_intel_crtc_state); } @@ -13413,7 +13413,7 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc, if (intel_cstate->update_pipe) intel_update_pipe_config(old_intel_cstate, intel_cstate); - else if (INTEL_GEN(dev_priv) >= 9) + else if (IS_GEN_GE(dev_priv, 9)) skl_detach_scalers(intel_cstate); out: @@ -13719,7 +13719,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) int num_formats; int ret; - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) return skl_universal_plane_create(dev_priv, pipe, PLANE_PRIMARY); @@ -14042,7 +14042,7 @@ static bool has_edp_a(struct drm_i915_private *dev_priv) static bool intel_crt_present(struct drm_i915_private *dev_priv) { - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) return false; if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) @@ -14666,7 +14666,7 @@ intel_mode_valid(struct drm_device *dev, DRM_MODE_FLAG_CLKDIV2)) return MODE_BAD; - if (INTEL_GEN(dev_priv) >= 9 || + if (IS_GEN_GE(dev_priv, 9) || IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ vdisplay_max = 4096; @@ -14719,7 +14719,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) { intel_init_cdclk_hooks(dev_priv); - if (INTEL_GEN(dev_priv) >= 9) { + if (IS_GEN_GE(dev_priv, 9)) { dev_priv->display.get_pipe_config = haswell_get_pipe_config; dev_priv->display.get_initial_plane_config = skylake_get_initial_plane_config; @@ -14798,7 +14798,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) dev_priv->display.fdi_link_train = hsw_fdi_link_train; } - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) dev_priv->display.update_crtcs = skl_update_crtcs; else dev_priv->display.update_crtcs = intel_update_crtcs; @@ -15716,7 +15716,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev, } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { vlv_wm_get_hw_state(dev); vlv_wm_sanitize(dev_priv); - } else if (INTEL_GEN(dev_priv) >= 9) { + } else if (IS_GEN_GE(dev_priv, 9)) { skl_wm_get_hw_state(dev); } else if (HAS_PCH_SPLIT(dev_priv)) { ilk_wm_get_hw_state(dev); diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 0de05dda4705..082e49a9e3d9 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1694,7 +1694,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp) intel_dp->aux_ch = intel_aux_ch(intel_dp); intel_dp->aux_power_domain = intel_aux_power_domain(intel_dp); - if (INTEL_GEN(dev_priv) >= 9) { + if (IS_GEN_GE(dev_priv, 9)) { intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; intel_dp->aux_ch_data_reg = skl_aux_data_reg; } else if (HAS_PCH_SPLIT(dev_priv)) { @@ -1705,7 +1705,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp) intel_dp->aux_ch_data_reg = g4x_aux_data_reg; } - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; @@ -1714,7 +1714,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp) else intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; else intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; @@ -2102,7 +2102,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, intel_fixed_panel_mode(intel_connector->panel.fixed_mode, adjusted_mode); - if (INTEL_GEN(dev_priv) >= 9) { + if (IS_GEN_GE(dev_priv, 9)) { int ret; ret = skl_update_scaler_crtc(pipe_config); diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 92ecaa8cd672..e769a1dba2a0 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -1275,7 +1275,7 @@ static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv) if (!HAS_FBC(dev_priv)) return 0; - if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) + if (IS_BROADWELL(dev_priv) || IS_GEN_GE(dev_priv, 9)) return 1; return 0; diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 33d87ab93fdd..20f12aeefcda 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -362,7 +362,7 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv) static inline unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv) { - return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : + return IS_GEN_GE(dev_priv, 9) ? GEN9_GMBUS_BYTE_COUNT_MAX : GMBUS_BYTE_COUNT_MAX; } diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 5f0e9ba780b7..28db71b97d28 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -2286,7 +2286,7 @@ int logical_render_ring_init(struct intel_engine_cs *engine) engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; /* Override some for render ring. */ - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) engine->init_hw = gen9_init_render_ring; else engine->init_hw = gen8_init_render_ring; diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c index e976c5ce5479..7205c1cd8675 100644 --- a/drivers/gpu/drm/i915/intel_mocs.c +++ b/drivers/gpu/drm/i915/intel_mocs.c @@ -188,7 +188,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv, table->table = broxton_mocs_table; result = true; } else { - WARN_ONCE(INTEL_GEN(dev_priv) >= 9, + WARN_ONCE(IS_GEN_GE(dev_priv, 9), "Platform that should have a MOCS table does not.\n"); } diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index c14de050bc07..07ab966fc39d 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2800,7 +2800,7 @@ hsw_compute_linetime_wm(const struct intel_crtc_state *cstate) static void intel_read_wm_latency(struct drm_i915_private *dev_priv, uint16_t wm[8]) { - if (INTEL_GEN(dev_priv) >= 9) { + if (IS_GEN_GE(dev_priv, 9)) { uint32_t val; int ret, i; int level, max_level = ilk_wm_max_level(dev_priv); @@ -2932,7 +2932,7 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv, int ilk_wm_max_level(const struct drm_i915_private *dev_priv) { /* how many WM levels are we expecting */ - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) return 7; else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) return 4; @@ -2961,7 +2961,7 @@ static void intel_print_wm_latency(struct drm_i915_private *dev_priv, * - latencies are in us on gen9. * - before then, WM1+ latency values are in 0.5us units */ - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) latency *= 10; else if (level > 0) latency *= 5; @@ -6417,7 +6417,7 @@ static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val) * the hw runs at the minimal clock before selecting the desired * frequency, if the down threshold expires in that window we will not * receive a down interrupt. */ - if (INTEL_GEN(dev_priv) >= 9) { + if (IS_GEN_GE(dev_priv, 9)) { limits = (rps->max_freq_softlimit) << 23; if (val <= rps->min_freq_softlimit) limits |= (rps->min_freq_softlimit) << 14; @@ -6594,7 +6594,7 @@ static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val) if (val != rps->cur_freq) { gen6_set_rps_thresholds(dev_priv, val); - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) I915_WRITE(GEN6_RPNSWREQ, GEN9_FREQUENCY(val)); else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) @@ -8426,7 +8426,7 @@ static void intel_disable_rc6(struct drm_i915_private *dev_priv) if (!dev_priv->gt_pm.rc6.enabled) return; - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) gen9_disable_rc6(dev_priv); else if (IS_CHERRYVIEW(dev_priv)) cherryview_disable_rc6(dev_priv); @@ -8445,7 +8445,7 @@ static void intel_disable_rps(struct drm_i915_private *dev_priv) if (!dev_priv->gt_pm.rps.enabled) return; - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) gen9_disable_rps(dev_priv); else if (IS_CHERRYVIEW(dev_priv)) cherryview_disable_rps(dev_priv); @@ -8494,7 +8494,7 @@ static void intel_enable_rc6(struct drm_i915_private *dev_priv) cherryview_enable_rc6(dev_priv); else if (IS_VALLEYVIEW(dev_priv)) valleyview_enable_rc6(dev_priv); - else if (INTEL_GEN(dev_priv) >= 9) + else if (IS_GEN_GE(dev_priv, 9)) gen9_enable_rc6(dev_priv); else if (IS_BROADWELL(dev_priv)) gen8_enable_rc6(dev_priv); @@ -8517,7 +8517,7 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv) cherryview_enable_rps(dev_priv); } else if (IS_VALLEYVIEW(dev_priv)) { valleyview_enable_rps(dev_priv); - } else if (INTEL_GEN(dev_priv) >= 9) { + } else if (IS_GEN_GE(dev_priv, 9)) { gen9_enable_rps(dev_priv); } else if (IS_BROADWELL(dev_priv)) { gen8_enable_rps(dev_priv); @@ -9451,7 +9451,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv) i915_ironlake_get_mem_freq(dev_priv); /* For FIFO watermark updates */ - if (INTEL_GEN(dev_priv) >= 9) { + if (IS_GEN_GE(dev_priv, 9)) { skl_setup_wm_latency(dev_priv); dev_priv->display.initial_watermarks = skl_initial_wm; dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm; @@ -9774,7 +9774,7 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) { - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER); else if (IS_CHERRYVIEW(dev_priv)) @@ -9787,7 +9787,7 @@ int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) { - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER, GT_FREQUENCY_MULTIPLIER); else if (IS_CHERRYVIEW(dev_priv)) @@ -9933,7 +9933,7 @@ u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat) { u32 cagf; - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 39afc8ed6533..f56b39c6a5d2 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -175,7 +175,7 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir) DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n", transcoder_name(cpu_transcoder)); - if (INTEL_GEN(dev_priv) >= 9) { + if (IS_GEN_GE(dev_priv, 9)) { u32 val = I915_READ(PSR_EVENT(cpu_transcoder)); bool psr2_enabled = dev_priv->psr.psr2_enabled; @@ -242,7 +242,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) WARN_ON(dev_priv->psr.dp); dev_priv->psr.dp = intel_dp; - if (INTEL_GEN(dev_priv) >= 9 && + if (IS_GEN_GE(dev_priv, 9) && (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { bool y_req = intel_dp->psr_dpcd[1] & DP_PSR2_SU_Y_COORDINATE_REQUIRED; @@ -543,7 +543,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE); WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); WARN_ON(dev_priv->psr.active); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 9c7b73986121..bcae43d8212d 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1472,7 +1472,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state, static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv) { - return INTEL_GEN(dev_priv) >= 9; + return IS_GEN_GE(dev_priv, 9); } static void intel_plane_set_ckey(struct intel_plane_state *plane_state, @@ -1496,7 +1496,7 @@ static void intel_plane_set_ckey(struct intel_plane_state *plane_state, * On SKL+ we want dst key enabled on * the primary and not on the sprite. */ - if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_PRIMARY && + if (IS_GEN_GE(dev_priv, 9) && plane->id != PLANE_PRIMARY && set->flags & I915_SET_COLORKEY_DESTINATION) key->flags = 0; } @@ -1535,7 +1535,7 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data, * Also multiple planes can't do destination keying on the same * pipe simultaneously. */ - if (INTEL_GEN(dev_priv) >= 9 && + if (IS_GEN_GE(dev_priv, 9) && to_intel_plane(plane)->id >= PLANE_SPRITE1 && set->flags & I915_SET_COLORKEY_DESTINATION) return -EINVAL; @@ -2040,7 +2040,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, int num_formats; int ret; - if (INTEL_GEN(dev_priv) >= 9) + if (IS_GEN_GE(dev_priv, 9)) return skl_universal_plane_create(dev_priv, pipe, PLANE_SPRITE0 + sprite); diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 88cbd32d6964..b98a9d3da5b0 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -459,7 +459,7 @@ static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv) { if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) || - INTEL_GEN(dev_priv) >= 9) { + IS_GEN_GE(dev_priv, 9)) { dev_priv->edram_cap = __raw_i915_read32(dev_priv, HSW_EDRAM_CAP); @@ -877,7 +877,7 @@ find_fw_domain(struct drm_i915_private *dev_priv, u32 offset) { .start = (s), .end = (e), .domains = (d) } #define HAS_FWTABLE(dev_priv) \ - (INTEL_GEN(dev_priv) >= 9 || \ + (IS_GEN_GE(dev_priv, 9) || \ IS_CHERRYVIEW(dev_priv) || \ IS_VALLEYVIEW(dev_priv)) -- 2.19.1.1.g56c4683e68 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 23+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Make GEN macros more similar 2018-11-01 8:35 [PATCH 0/5] Make GEN macros more similar Lucas De Marchi ` (4 preceding siblings ...) 2018-11-01 8:35 ` [PATCH 5/5] RFC: drm/i915: convert a few cases to the " Lucas De Marchi @ 2018-11-01 9:30 ` Patchwork 2018-11-01 9:32 ` ✗ Fi.CI.SPARSE: " Patchwork 2018-11-01 9:57 ` ✗ Fi.CI.BAT: failure " Patchwork 7 siblings, 0 replies; 23+ messages in thread From: Patchwork @ 2018-11-01 9:30 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx == Series Details == Series: Make GEN macros more similar URL : https://patchwork.freedesktop.org/series/51860/ State : warning == Summary == $ dim checkpatch origin/drm-tip 84d61579c8b9 drm/i915: let IS_GEN receive 1 or 2 arguments 51b9316b0b74 drm/i915: replace IS_GEN<N> with IS_GEN(..., N) -:230: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #230: FILE: drivers/gpu/drm/i915/i915_drv.h:2542: +#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) -:231: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #231: FILE: drivers/gpu/drm/i915/i915_drv.h:2543: +#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) -:249: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #249: FILE: drivers/gpu/drm/i915/i915_drv.h:2616: +#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \ !(IS_I915G(dev_priv) || \ IS_I915GM(dev_priv))) -:409: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!r" #409: FILE: drivers/gpu/drm/i915/i915_gem_stolen.c:159: + if (r == NULL && !IS_GEN(dev_priv, 3)) { -:1094: CHECK:CAMELCASE: Avoid CamelCase: <ILK_eDP_A_DISABLE> #1094: FILE: drivers/gpu/drm/i915/intel_display.c:14037: + if (IS_GEN(dev_priv, 5) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) total: 0 errors, 0 warnings, 5 checks, 1759 lines checked 8ddcd15d8033 drm/i915: merge gen checks to use range d7cce02ca89e drm/i915: add helper IS_GEN_* macros -:20: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'g' may be better as '(g)' to avoid precedence issues #20: FILE: drivers/gpu/drm/i915/i915_drv.h:2373: +#define IS_GEN_GT(dev_priv, g) (g > (dev_priv)->info.gen) -:21: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'g' may be better as '(g)' to avoid precedence issues #21: FILE: drivers/gpu/drm/i915/i915_drv.h:2374: +#define IS_GEN_GE(dev_priv, g) (g >= (dev_priv)->info.gen) -:22: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'g' may be better as '(g)' to avoid precedence issues #22: FILE: drivers/gpu/drm/i915/i915_drv.h:2375: +#define IS_GEN_LT(dev_priv, g) (g < (dev_priv)->info.gen) -:23: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'g' may be better as '(g)' to avoid precedence issues #23: FILE: drivers/gpu/drm/i915/i915_drv.h:2376: +#define IS_GEN_LE(dev_priv, g) (g <= (dev_priv)->info.gen) total: 0 errors, 0 warnings, 4 checks, 11 lines checked b4c18b9f7af8 RFC: drm/i915: convert a few cases to the helper IS_GEN_* macros -:71: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 63) #71: FILE: drivers/gpu/drm/i915/i915_debugfs.c:1759: + if (IS_GEN_GE(dev_priv, 9)) /* no global SR status; inspect per-plane WM */; -:204: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #204: FILE: drivers/gpu/drm/i915/i915_reg.h:3794: +#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN_GE(dev_priv, 9) ? \ (IS_GEN9_LP(dev_priv) ? \ INTERVAL_0_833_US(us) : \ INTERVAL_1_33_US(us)) : \ -:204: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #204: FILE: drivers/gpu/drm/i915/i915_reg.h:3794: +#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN_GE(dev_priv, 9) ? \ (IS_GEN9_LP(dev_priv) ? \ INTERVAL_0_833_US(us) : \ INTERVAL_1_33_US(us)) : \ -:204: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'us' - possible side-effects? #204: FILE: drivers/gpu/drm/i915/i915_reg.h:3794: +#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN_GE(dev_priv, 9) ? \ (IS_GEN9_LP(dev_priv) ? \ INTERVAL_0_833_US(us) : \ INTERVAL_1_33_US(us)) : \ -:213: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #213: FILE: drivers/gpu/drm/i915/i915_reg.h:3803: +#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN_GE(dev_priv, 9) ? \ (IS_GEN9_LP(dev_priv) ? \ INTERVAL_0_833_TO_US(interval) : \ INTERVAL_1_33_TO_US(interval)) : \ -:213: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #213: FILE: drivers/gpu/drm/i915/i915_reg.h:3803: +#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN_GE(dev_priv, 9) ? \ (IS_GEN9_LP(dev_priv) ? \ INTERVAL_0_833_TO_US(interval) : \ INTERVAL_1_33_TO_US(interval)) : \ -:213: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'interval' - possible side-effects? #213: FILE: drivers/gpu/drm/i915/i915_reg.h:3803: +#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN_GE(dev_priv, 9) ? \ (IS_GEN9_LP(dev_priv) ? \ INTERVAL_0_833_TO_US(interval) : \ INTERVAL_1_33_TO_US(interval)) : \ -:667: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED' #667: FILE: drivers/gpu/drm/i915/intel_psr.c:245: + if (IS_GEN_GE(dev_priv, 9) && (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { total: 2 errors, 1 warnings, 5 checks, 584 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* ✗ Fi.CI.SPARSE: warning for Make GEN macros more similar 2018-11-01 8:35 [PATCH 0/5] Make GEN macros more similar Lucas De Marchi ` (5 preceding siblings ...) 2018-11-01 9:30 ` ✗ Fi.CI.CHECKPATCH: warning for Make GEN macros more similar Patchwork @ 2018-11-01 9:32 ` Patchwork 2018-11-01 9:57 ` ✗ Fi.CI.BAT: failure " Patchwork 7 siblings, 0 replies; 23+ messages in thread From: Patchwork @ 2018-11-01 9:32 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx == Series Details == Series: Make GEN macros more similar URL : https://patchwork.freedesktop.org/series/51860/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: let IS_GEN receive 1 or 2 arguments -drivers/gpu/drm/i915/selftests/../i915_drv.h:3699:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3705:16: warning: expression using sizeof(void) Commit: drm/i915: replace IS_GEN<N> with IS_GEN(..., N) -O:drivers/gpu/drm/i915/intel_cdclk.c:2178:37: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_cdclk.c:2181:37: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_cdclk.c:2178:37: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_cdclk.c:2181:37: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_fbc.c:88:25: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_fbc.c:90:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_fbc.c:88:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_fbc.c:90:25: warning: expression using sizeof(void) Commit: drm/i915: merge gen checks to use range Okay! Commit: drm/i915: add helper IS_GEN_* macros -drivers/gpu/drm/i915/selftests/../i915_drv.h:3705:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3710:16: warning: expression using sizeof(void) Commit: RFC: drm/i915: convert a few cases to the helper IS_GEN_* macros -O:drivers/gpu/drm/i915/intel_cdclk.c:2201:29: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_cdclk.c:2201:29: warning: expression using sizeof(void) _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* ✗ Fi.CI.BAT: failure for Make GEN macros more similar 2018-11-01 8:35 [PATCH 0/5] Make GEN macros more similar Lucas De Marchi ` (6 preceding siblings ...) 2018-11-01 9:32 ` ✗ Fi.CI.SPARSE: " Patchwork @ 2018-11-01 9:57 ` Patchwork 7 siblings, 0 replies; 23+ messages in thread From: Patchwork @ 2018-11-01 9:57 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx == Series Details == Series: Make GEN macros more similar URL : https://patchwork.freedesktop.org/series/51860/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5064 -> Patchwork_10685 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10685 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10685, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/51860/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10685: === IGT changes === ==== Possible regressions ==== igt@gem_exec_suspend@basic-s4-devices: fi-icl-u: NOTRUN -> DMESG-WARN fi-icl-u2: PASS -> DMESG-WARN ==== Warnings ==== igt@drv_selftest@live_guc: fi-apl-guc: SKIP -> PASS fi-skl-iommu: SKIP -> PASS +1 igt@gem_exec_suspend@basic-s3: fi-icl-u: INCOMPLETE (fdo#107713) -> DMESG-WARN igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: SKIP -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: fi-icl-u2: PASS -> SKIP +40 == Known issues == Here are the changes found in Patchwork_10685 that come from known issues: === IGT changes === ==== Issues hit ==== igt@drv_module_reload@basic-no-display: fi-icl-u2: PASS -> DMESG-WARN (fdo#107732) +1 igt@drv_module_reload@basic-reload: fi-icl-u: NOTRUN -> INCOMPLETE (fdo#108567) igt@drv_module_reload@basic-reload-inject: fi-icl-u2: PASS -> INCOMPLETE (fdo#108567) ==== Possible fixes ==== igt@drv_selftest@live_execlists: fi-apl-guc: INCOMPLETE (fdo#106693) -> PASS igt@drv_selftest@live_hangcheck: fi-skl-iommu: INCOMPLETE (fdo#108602) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106693 https://bugs.freedesktop.org/show_bug.cgi?id=106693 fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713 fdo#107732 https://bugs.freedesktop.org/show_bug.cgi?id=107732 fdo#108567 https://bugs.freedesktop.org/show_bug.cgi?id=108567 fdo#108602 https://bugs.freedesktop.org/show_bug.cgi?id=108602 == Participating hosts (47 -> 26) == Missing (21): fi-cnl-u fi-bdw-gvtdvm fi-pnv-d510 fi-blb-e6850 fi-snb-2600 fi-hsw-4770r fi-bdw-5557u fi-bsw-n3050 fi-byt-j1900 fi-bwr-2160 fi-ctg-p8600 fi-hsw-4770 fi-gdg-551 fi-ivb-3770 fi-ivb-3520m fi-ilk-m540 fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-bsw-kefka fi-byt-clapper == Build changes == * Linux: CI_DRM_5064 -> Patchwork_10685 CI_DRM_5064: 9458f0c67b519ddf1c2b4eec9110e826c4e7d2f3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4703: f882a542a3eb24e78e51aa6410a3a67c0efb4e97 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10685: b4c18b9f7af84cb8a39ab49d2c9383001b2133ff @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b4c18b9f7af8 RFC: drm/i915: convert a few cases to the helper IS_GEN_* macros d7cce02ca89e drm/i915: add helper IS_GEN_* macros 8ddcd15d8033 drm/i915: merge gen checks to use range 51b9316b0b74 drm/i915: replace IS_GEN<N> with IS_GEN(..., N) 84d61579c8b9 drm/i915: let IS_GEN receive 1 or 2 arguments == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10685/issues.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2018-11-02 22:47 UTC | newest] Thread overview: 23+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2018-11-01 8:35 [PATCH 0/5] Make GEN macros more similar Lucas De Marchi 2018-11-01 8:35 ` [PATCH 1/5] drm/i915: let IS_GEN receive 1 or 2 arguments Lucas De Marchi 2018-11-01 8:35 ` [PATCH 2/5] drm/i915: replace IS_GEN<N> with IS_GEN(..., N) Lucas De Marchi 2018-11-01 11:17 ` Jani Nikula 2018-11-01 13:27 ` Ville Syrjälä 2018-11-01 11:35 ` Tvrtko Ursulin 2018-11-01 17:00 ` Lucas De Marchi 2018-11-01 8:35 ` [PATCH 3/5] drm/i915: merge gen checks to use range Lucas De Marchi 2018-11-01 11:18 ` Jani Nikula 2018-11-01 11:31 ` Tvrtko Ursulin 2018-11-02 18:10 ` Lucas De Marchi 2018-11-02 19:19 ` Rodrigo Vivi 2018-11-02 19:47 ` Lucas De Marchi 2018-11-02 22:12 ` Rodrigo Vivi 2018-11-02 22:28 ` Lucas De Marchi 2018-11-02 22:47 ` Rodrigo Vivi 2018-11-01 8:35 ` [PATCH 4/5] drm/i915: add helper IS_GEN_* macros Lucas De Marchi 2018-11-01 11:04 ` Tvrtko Ursulin 2018-11-01 11:29 ` Jani Nikula 2018-11-01 8:35 ` [PATCH 5/5] RFC: drm/i915: convert a few cases to the " Lucas De Marchi 2018-11-01 9:30 ` ✗ Fi.CI.CHECKPATCH: warning for Make GEN macros more similar Patchwork 2018-11-01 9:32 ` ✗ Fi.CI.SPARSE: " Patchwork 2018-11-01 9:57 ` ✗ Fi.CI.BAT: failure " Patchwork
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