From: sudeep.holla@arm.com (Sudeep Holla)
To: linux-riscv@lists.infradead.org
Subject: [RFC 0/2] Add RISC-V cpu topology
Date: Tue, 6 Nov 2018 14:13:49 +0000 [thread overview]
Message-ID: <20181106141331.GA28458@e107155-lin> (raw)
In-Reply-To: <866dedbc78ab4fa0e3b040697e112106@mailhost.ics.forth.gr>
On Fri, Nov 02, 2018 at 08:58:39PM +0200, Nick Kossifidis wrote:
> Hello All,
>
> ???? 2018-11-02 01:04, Atish Patra ??????:
> > This patch series adds the cpu topology for RISC-V. It contains
> > both the DT binding and actual source code. It has been tested on
> > QEMU & Unleashed board.
> >
> > The idea is based on cpu-map in ARM with changes related to how
> > we define SMT systems. The reason for adopting a similar approach
> > to ARM as I feel it provides a very clear way of defining the
> > topology compared to parsing cache nodes to figure out which cpus
> > share the same package or core. I am open to any other idea to
> > implement cpu-topology as well.
> >
>
> I was also about to start a discussion about CPU topology on RISC-V
> after the last swtools group meeting. The goal is to provide the
> scheduler with hints on how to distribute tasks more efficiently
> between harts, by populating the scheduling domain topology levels
> (https://elixir.bootlin.com/linux/v4.19/ident/sched_domain_topology_level).
> What we want to do is define cpu groups and assign them to
> scheduling domains with the appropriate SD_ flags
> (https://github.com/torvalds/linux/blob/master/include/linux/sched/topology.h#L16).
>
OK are we defining a CPU topology binding for Linux scheduler ?
NACK for all the approaches that assumes any knowledge of OS scheduler.
> So the cores that belong to a scheduling domain may share:
> CPU capacity (SD_SHARE_CPUCAPACITY / SD_ASYM_CPUCAPACITY)
> Package resources -e.g. caches, units etc- (SD_SHARE_PKG_RESOURCES)
> Power domain (SD_SHARE_POWERDOMAIN)
>
Too Linux kernel/scheduler specific to be part of $subject
> In this context I believe using words like "core", "package",
> "socket" etc can be misleading. For example the sample topology you
> use on the documentation says that there are 4 cores that are part
> of a package, however "package" has a different meaning to the
> scheduler. Also we don't say anything in case they share a power
> domain or if they have the same capacity or not. This mapping deals
> only with cache hierarchy or other shared resources.
>
{Un,}fortunately those are terms used by hardware people.
> How about defining a dt scheme to describe the scheduler domain
> topology levels instead ? e.g:
>
NACK as already mentioned above.
--
Regards,
Sudeep
WARNING: multiple messages have this Message-ID (diff)
From: Sudeep Holla <sudeep.holla@arm.com>
To: Nick Kossifidis <mick@ics.forth.gr>
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
Damien.LeMoal@wdc.com, alankao@andestech.com, hch@infradead.org,
anup@brainfault.org, palmer@sifive.com,
linux-kernel@vger.kernel.org, zong@andestech.com,
Atish Patra <atish.patra@wdc.com>,
robh+dt@kernel.org, Sudeep Holla <sudeep.holla@arm.com>,
linux-riscv@lists.infradead.org, tglx@linutronix.de
Subject: Re: [RFC 0/2] Add RISC-V cpu topology
Date: Tue, 6 Nov 2018 14:13:49 +0000 [thread overview]
Message-ID: <20181106141331.GA28458@e107155-lin> (raw)
Message-ID: <20181106141349.ERBh93_k2R35OOIptlKgOOBgdouLZGw4iufq1gt72KA@z> (raw)
In-Reply-To: <866dedbc78ab4fa0e3b040697e112106@mailhost.ics.forth.gr>
On Fri, Nov 02, 2018 at 08:58:39PM +0200, Nick Kossifidis wrote:
> Hello All,
>
> Στις 2018-11-02 01:04, Atish Patra έγραψε:
> > This patch series adds the cpu topology for RISC-V. It contains
> > both the DT binding and actual source code. It has been tested on
> > QEMU & Unleashed board.
> >
> > The idea is based on cpu-map in ARM with changes related to how
> > we define SMT systems. The reason for adopting a similar approach
> > to ARM as I feel it provides a very clear way of defining the
> > topology compared to parsing cache nodes to figure out which cpus
> > share the same package or core. I am open to any other idea to
> > implement cpu-topology as well.
> >
>
> I was also about to start a discussion about CPU topology on RISC-V
> after the last swtools group meeting. The goal is to provide the
> scheduler with hints on how to distribute tasks more efficiently
> between harts, by populating the scheduling domain topology levels
> (https://elixir.bootlin.com/linux/v4.19/ident/sched_domain_topology_level).
> What we want to do is define cpu groups and assign them to
> scheduling domains with the appropriate SD_ flags
> (https://github.com/torvalds/linux/blob/master/include/linux/sched/topology.h#L16).
>
OK are we defining a CPU topology binding for Linux scheduler ?
NACK for all the approaches that assumes any knowledge of OS scheduler.
> So the cores that belong to a scheduling domain may share:
> CPU capacity (SD_SHARE_CPUCAPACITY / SD_ASYM_CPUCAPACITY)
> Package resources -e.g. caches, units etc- (SD_SHARE_PKG_RESOURCES)
> Power domain (SD_SHARE_POWERDOMAIN)
>
Too Linux kernel/scheduler specific to be part of $subject
> In this context I believe using words like "core", "package",
> "socket" etc can be misleading. For example the sample topology you
> use on the documentation says that there are 4 cores that are part
> of a package, however "package" has a different meaning to the
> scheduler. Also we don't say anything in case they share a power
> domain or if they have the same capacity or not. This mapping deals
> only with cache hierarchy or other shared resources.
>
{Un,}fortunately those are terms used by hardware people.
> How about defining a dt scheme to describe the scheduler domain
> topology levels instead ? e.g:
>
NACK as already mentioned above.
--
Regards,
Sudeep
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Sudeep Holla <sudeep.holla@arm.com>
To: Nick Kossifidis <mick@ics.forth.gr>
Cc: Atish Patra <atish.patra@wdc.com>,
linux-riscv@lists.infradead.org, mark.rutland@arm.com,
devicetree@vger.kernel.org, Damien.LeMoal@wdc.com,
alankao@andestech.com, zong@andestech.com, anup@brainfault.org,
palmer@sifive.com, linux-kernel@vger.kernel.org,
hch@infradead.org, robh+dt@kernel.org, tglx@linutronix.de,
Sudeep Holla <sudeep.holla@arm.com>
Subject: Re: [RFC 0/2] Add RISC-V cpu topology
Date: Tue, 6 Nov 2018 14:13:49 +0000 [thread overview]
Message-ID: <20181106141331.GA28458@e107155-lin> (raw)
In-Reply-To: <866dedbc78ab4fa0e3b040697e112106@mailhost.ics.forth.gr>
On Fri, Nov 02, 2018 at 08:58:39PM +0200, Nick Kossifidis wrote:
> Hello All,
>
> Στις 2018-11-02 01:04, Atish Patra έγραψε:
> > This patch series adds the cpu topology for RISC-V. It contains
> > both the DT binding and actual source code. It has been tested on
> > QEMU & Unleashed board.
> >
> > The idea is based on cpu-map in ARM with changes related to how
> > we define SMT systems. The reason for adopting a similar approach
> > to ARM as I feel it provides a very clear way of defining the
> > topology compared to parsing cache nodes to figure out which cpus
> > share the same package or core. I am open to any other idea to
> > implement cpu-topology as well.
> >
>
> I was also about to start a discussion about CPU topology on RISC-V
> after the last swtools group meeting. The goal is to provide the
> scheduler with hints on how to distribute tasks more efficiently
> between harts, by populating the scheduling domain topology levels
> (https://elixir.bootlin.com/linux/v4.19/ident/sched_domain_topology_level).
> What we want to do is define cpu groups and assign them to
> scheduling domains with the appropriate SD_ flags
> (https://github.com/torvalds/linux/blob/master/include/linux/sched/topology.h#L16).
>
OK are we defining a CPU topology binding for Linux scheduler ?
NACK for all the approaches that assumes any knowledge of OS scheduler.
> So the cores that belong to a scheduling domain may share:
> CPU capacity (SD_SHARE_CPUCAPACITY / SD_ASYM_CPUCAPACITY)
> Package resources -e.g. caches, units etc- (SD_SHARE_PKG_RESOURCES)
> Power domain (SD_SHARE_POWERDOMAIN)
>
Too Linux kernel/scheduler specific to be part of $subject
> In this context I believe using words like "core", "package",
> "socket" etc can be misleading. For example the sample topology you
> use on the documentation says that there are 4 cores that are part
> of a package, however "package" has a different meaning to the
> scheduler. Also we don't say anything in case they share a power
> domain or if they have the same capacity or not. This mapping deals
> only with cache hierarchy or other shared resources.
>
{Un,}fortunately those are terms used by hardware people.
> How about defining a dt scheme to describe the scheduler domain
> topology levels instead ? e.g:
>
NACK as already mentioned above.
--
Regards,
Sudeep
next prev parent reply other threads:[~2018-11-06 14:13 UTC|newest]
Thread overview: 96+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-01 23:04 [RFC 0/2] Add RISC-V cpu topology Atish Patra
2018-11-01 23:04 ` Atish Patra
2018-11-01 23:04 ` Atish Patra
2018-11-01 23:04 ` [RFC 1/2] dt-bindings: topology: " Atish Patra
2018-11-01 23:04 ` Atish Patra
2018-11-01 23:04 ` Atish Patra
2018-11-02 13:09 ` Rob Herring
2018-11-02 13:09 ` Rob Herring
2018-11-02 13:09 ` Rob Herring
2018-11-02 13:31 ` Sudeep Holla
2018-11-02 13:31 ` Sudeep Holla
2018-11-02 13:31 ` Sudeep Holla
2018-11-02 15:11 ` Rob Herring
2018-11-02 15:11 ` Rob Herring
2018-11-02 15:11 ` Rob Herring
2018-11-02 15:50 ` Sudeep Holla
2018-11-02 15:50 ` Sudeep Holla
2018-11-02 15:50 ` Sudeep Holla
2018-11-02 20:53 ` Atish Patra
2018-11-02 20:53 ` Atish Patra
2018-11-02 20:53 ` Atish Patra
2018-11-02 21:08 ` Rob Herring
2018-11-02 21:08 ` Rob Herring
2018-11-02 21:08 ` Rob Herring
2018-11-02 20:34 ` Atish Patra
2018-11-02 20:34 ` Atish Patra
2018-11-02 20:34 ` Atish Patra
2018-11-05 19:38 ` Palmer Dabbelt
2018-11-05 19:38 ` Palmer Dabbelt
2018-11-05 19:38 ` Palmer Dabbelt
2018-11-05 20:10 ` Rob Herring
2018-11-05 20:10 ` Rob Herring
2018-11-05 20:10 ` Rob Herring
2018-11-06 0:12 ` Atish Patra
2018-11-06 0:12 ` Atish Patra
2018-11-06 0:12 ` Atish Patra
2018-11-06 10:03 ` Nick Kossifidis
2018-11-06 10:03 ` Nick Kossifidis
2018-11-06 10:03 ` Nick Kossifidis
2018-11-06 11:37 ` Mark Rutland
2018-11-06 11:37 ` Mark Rutland
2018-11-06 11:37 ` Mark Rutland
2018-11-01 23:04 ` [RFC 2/2] RISC-V: Introduce " Atish Patra
2018-11-01 23:04 ` Atish Patra
2018-11-01 23:04 ` Atish Patra
2018-11-02 18:58 ` [RFC 0/2] Add RISC-V " Nick Kossifidis
2018-11-02 18:58 ` Nick Kossifidis
2018-11-02 18:58 ` Nick Kossifidis
2018-11-02 21:14 ` Atish Patra
2018-11-02 21:14 ` Atish Patra
2018-11-02 21:14 ` Atish Patra
2018-11-02 22:18 ` Nick Kossifidis
2018-11-02 22:18 ` Nick Kossifidis
2018-11-02 22:18 ` Nick Kossifidis
2018-11-06 14:13 ` Sudeep Holla [this message]
2018-11-06 14:13 ` Sudeep Holla
2018-11-06 14:13 ` Sudeep Holla
2018-11-06 15:26 ` Nick Kossifidis
2018-11-06 15:26 ` Nick Kossifidis
2018-11-06 15:26 ` Nick Kossifidis
2018-11-06 15:50 ` Sudeep Holla
2018-11-06 15:50 ` Sudeep Holla
2018-11-06 15:50 ` Sudeep Holla
2018-11-06 16:20 ` Mark Rutland
2018-11-06 16:20 ` Mark Rutland
2018-11-06 16:20 ` Mark Rutland
2018-11-07 2:31 ` Nick Kossifidis
2018-11-07 2:31 ` Nick Kossifidis
2018-11-07 2:31 ` Nick Kossifidis
2018-11-07 12:06 ` Mark Rutland
2018-11-07 12:06 ` Mark Rutland
2018-11-07 12:06 ` Mark Rutland
2018-11-08 13:45 ` Nick Kossifidis
2018-11-08 13:45 ` Nick Kossifidis
2018-11-08 13:45 ` Nick Kossifidis
2018-11-08 15:54 ` Mark Rutland
2018-11-08 15:54 ` Mark Rutland
2018-11-08 15:54 ` Mark Rutland
2018-11-09 3:55 ` Nick Kossifidis
2018-11-09 3:55 ` Nick Kossifidis
2018-11-09 3:55 ` Nick Kossifidis
2018-11-07 12:28 ` Sudeep Holla
2018-11-07 12:28 ` Sudeep Holla
2018-11-07 12:28 ` Sudeep Holla
2018-11-08 14:52 ` Nick Kossifidis
2018-11-08 14:52 ` Nick Kossifidis
2018-11-08 14:52 ` Nick Kossifidis
2018-11-08 16:48 ` Sudeep Holla
2018-11-08 16:48 ` Sudeep Holla
2018-11-08 16:48 ` Sudeep Holla
2018-11-09 2:36 ` Nick Kossifidis
2018-11-09 2:36 ` Nick Kossifidis
2018-11-09 2:36 ` Nick Kossifidis
2018-11-09 12:33 ` Sudeep Holla
2018-11-09 12:33 ` Sudeep Holla
2018-11-09 12:33 ` Sudeep Holla
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