From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915: Program SKL+ watermarks/ddb more carefully (rev7)
Date: Thu, 15 Nov 2018 17:23:11 +0200 [thread overview]
Message-ID: <20181115152311.GZ9144@intel.com> (raw)
In-Reply-To: <20181115142346.GY9144@intel.com>
On Thu, Nov 15, 2018 at 04:23:46PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 15, 2018 at 05:21:46AM -0000, Patchwork wrote:
> > == Series Details ==
> >
> > Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev7)
> > URL : https://patchwork.freedesktop.org/series/51878/
> > State : failure
> >
> > == Summary ==
> >
> > = CI Bug Log - changes from CI_DRM_5140_full -> Patchwork_10827_full =
> >
> > == Summary - FAILURE ==
> >
> > Serious unknown changes coming with Patchwork_10827_full absolutely need to be
> > verified manually.
> >
> > If you think the reported changes have nothing to do with the changes
> > introduced in Patchwork_10827_full, please notify your bug team to allow them
> > to document this new failure mode, which will reduce false positives in CI.
> >
> >
> >
> > == Possible new issues ==
> >
> > Here are the unknown changes that may have been introduced in Patchwork_10827_full:
> >
> > === IGT changes ===
> >
> > ==== Possible regressions ====
> >
> > igt@prime_vgem@basic-fence-flip:
> > shard-apl: PASS -> DMESG-WARN
> > shard-kbl: PASS -> DMESG-WARN
>
>
> <3> [72.612353] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 0 (expected e=0 b=0 l=0, got e=1 b=3 l=1)
> <3> [72.612661] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 1 (expected e=0 b=0 l=0, got e=1 b=4 l=1)
> <3> [72.612784] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 2 (expected e=0 b=0 l=0, got e=1 b=4 l=1)
> <3> [72.612905] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 3 (expected e=0 b=0 l=0, got e=1 b=6 l=2)
> <3> [72.613026] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 4 (expected e=0 b=0 l=0, got e=1 b=6 l=2)
> <3> [72.613147] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 5 (expected e=0 b=0 l=0, got e=1 b=6 l=2)
> <3> [72.613267] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 6 (expected e=0 b=0 l=0, got e=1 b=6 l=2)
> <3> [72.613388] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 7 (expected e=0 b=0 l=0, got e=1 b=6 l=2)
>
> I suspect this would be caused by the cursor becoming fully clipped
> but still logically enabled (fb != NULL) during the previous test
> (kms_chv_cursor_fail). And then when it comes time to turn off the
> pipe we won't reprogram the cursor because its visibility didn't
> change and thus we won't clear its watermarks either. I think I'm
> going to write a targeted test for that just to make sure my
> analysis is correct.
Actually that can't be it I think. There was no complaint about a
non-zero DDB allocation left behind, so somehow we've got non-zero
watermarks with no DDB allocated. That doesn't quite make sense.
--
Ville Syrjälä
Intel
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next prev parent reply other threads:[~2018-11-15 15:23 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-14 21:07 [PATCH v2 00/13] drm/i915: Program SKL+ watermarks/ddb more carefully Ville Syrjala
2018-11-14 21:07 ` [PATCH v2 01/13] drm/i915: Reorganize plane register writes to make them more atomic Ville Syrjala
2018-11-19 23:14 ` Matt Roper
2018-11-14 21:07 ` [PATCH v2 02/13] drm/i915: Move single buffered plane register writes to the end Ville Syrjala
2018-11-19 23:14 ` Matt Roper
2018-11-14 21:07 ` [PATCH v2 03/13] drm/i915: Introduce crtc_state->update_planes bitmask Ville Syrjala
2018-11-19 23:14 ` Matt Roper
2018-11-21 19:10 ` Ville Syrjälä
2018-11-27 16:37 ` [PATCH v3 " Ville Syrjala
2018-11-14 21:07 ` [PATCH v2 04/13] drm/i915: Pass the new crtc_state to ->disable_plane() Ville Syrjala
2018-11-19 23:14 ` Matt Roper
2018-11-14 21:07 ` [PATCH v2 05/13] drm/i915: Fix latency==0 handling for level 0 watermark on skl+ Ville Syrjala
2018-11-19 23:14 ` Matt Roper
2018-11-21 19:09 ` Ville Syrjälä
2018-11-14 21:07 ` [PATCH v2 06/13] drm/i915: Remove some useless zeroing on skl+ wm calculations Ville Syrjala
2018-11-19 23:14 ` Matt Roper
2018-11-14 21:07 ` [PATCH v2 07/13] drm/i915: Pass the entire skl_plane_wm to skl_compute_transition_wm() Ville Syrjala
2018-11-19 23:14 ` Matt Roper
2018-11-14 21:07 ` [PATCH v2 08/13] drm/i915: Clean up skl+ vs. icl+ watermark computation Ville Syrjala
2018-11-20 22:44 ` Matt Roper
2018-11-21 19:05 ` Ville Syrjälä
2018-11-21 21:05 ` Matt Roper
2018-11-27 16:57 ` [PATCH v3 " Ville Syrjala
2018-11-14 21:07 ` [PATCH v2 09/13] drm/i915: Don't pass dev_priv around so much Ville Syrjala
2018-11-20 22:45 ` Matt Roper
2018-11-14 21:07 ` [PATCH v2 10/13] drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+ Ville Syrjala
2018-11-19 18:23 ` [PATCH v4 " Ville Syrjala
2018-11-21 0:48 ` [PATCH v2 " Matt Roper
2018-11-21 19:01 ` Ville Syrjälä
2018-11-27 16:59 ` [PATCH v5 " Ville Syrjala
2018-11-14 21:07 ` [PATCH v2 11/13] drm/i915: Commit skl+ planes in an order that avoids ddb overlaps Ville Syrjala
2018-11-26 23:28 ` Matt Roper
2018-11-14 21:07 ` [PATCH v2 12/13] drm/i915: Rename the confusing 'plane_id' to 'color_plane' Ville Syrjala
2018-11-26 23:30 ` Matt Roper
2018-11-14 21:07 ` [PATCH v2 13/13] drm/i915: Pass the plane to icl_program_input_csc_coeff() Ville Syrjala
2018-11-15 11:18 ` Shankar, Uma
2018-11-15 12:37 ` Maarten Lankhorst
2018-11-26 23:38 ` Matt Roper
2018-11-14 21:15 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Program SKL+ watermarks/ddb more carefully (rev7) Patchwork
2018-11-14 21:19 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-11-14 21:36 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-15 5:21 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-11-15 14:23 ` Ville Syrjälä
2018-11-15 15:23 ` Ville Syrjälä [this message]
2018-11-19 18:48 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Program SKL+ watermarks/ddb more carefully (rev8) Patchwork
2018-11-19 18:53 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-11-19 19:07 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-20 1:52 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-11-20 18:55 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-21 6:05 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-11-21 19:19 ` Ville Syrjälä
2018-11-23 15:07 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-23 17:45 ` ✓ Fi.CI.IGT: " Patchwork
2018-11-27 17:44 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Program SKL+ watermarks/ddb more carefully (rev11) Patchwork
2018-11-27 17:48 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-11-27 18:05 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-28 0:11 ` ✓ Fi.CI.IGT: " Patchwork
2018-11-28 20:18 ` [PATCH v2 00/13] drm/i915: Program SKL+ watermarks/ddb more carefully Ville Syrjälä
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