[PATCH v2 00/13] drm/i915: Program SKL+ watermarks/ddb more carefully

[PATCH v2 00/13] drm/i915: Program SKL+ watermarks/ddb more carefully

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Here's the remainder of the skl+ ddb/wm programming series. I tried to
split up the ugly monster patch into a few chunks, and I tossed in
a few extra nuggets on top. I also tried to improve the commit
messages a bit based on the previous review feedback.

Entire series available here:
git://github.com/vsyrjala/linux.git skl_plane_ddb_wm_update_3

Ville Syrjälä (13):
  drm/i915: Reorganize plane register writes to make them more atomic
  drm/i915: Move single buffered plane register writes to the end
  drm/i915: Introduce crtc_state->update_planes bitmask
  drm/i915: Pass the new crtc_state to ->disable_plane()
  drm/i915: Fix latency==0 handling for level 0 watermark on skl+
  drm/i915: Remove some useless zeroing on skl+ wm calculations
  drm/i915: Pass the entire skl_plane_wm to skl_compute_transition_wm()
  drm/i915: Clean up skl+ vs. icl+ watermark computation
  drm/i915: Don't pass dev_priv around so much
  drm/i915: Move ddb/wm programming into plane update/disable hooks on
    skl+
  drm/i915: Commit skl+ planes in an order that avoids ddb overlaps
  drm/i915: Rename the confusing 'plane_id' to 'color_plane'
  drm/i915: Pass the plane to icl_program_input_csc_coeff()

 drivers/gpu/drm/i915/i915_debugfs.c       |  21 +-
 drivers/gpu/drm/i915/i915_drv.h           |   3 -
 drivers/gpu/drm/i915/intel_atomic.c       |   1 +
 drivers/gpu/drm/i915/intel_atomic_plane.c | 102 ++++-
 drivers/gpu/drm/i915/intel_display.c      | 119 +++--
 drivers/gpu/drm/i915/intel_display.h      |  19 +-
 drivers/gpu/drm/i915/intel_drv.h          |  22 +-
 drivers/gpu/drm/i915/intel_pm.c           | 500 ++++++++++------------
 drivers/gpu/drm/i915/intel_sprite.c       | 148 ++++---
 9 files changed, 523 insertions(+), 412 deletions(-)

-- 
2.18.1

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[PATCH v2 01/13] drm/i915: Reorganize plane register writes to make them more atomic

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Some observations about the plane registers:
- the control register will self-arm if the plane is not already
  enabled, thus we want to write it as close to (or ideally after)
  the surface register
- tileoff/linoff/offset/aux_offset are self-arming as well so we want
  them close to the surface register as well
- color keying registers we maybe self arming before SKL. Not 100%
  sure but we can try to keep them near to the surface register
  as well
- chv pipe b csc register are double buffered but self arming so
  moving them down a bit
- the rest should be mostly armed by the surface register so we can
  safely write them first, and to just for some consistency let's try
  to follow keep them in order based on the register offset

None of this will have any effect of course unless the vblank evasion
fails (which it still does sometimes). Another potential future benefit
might be pulling the non-self armings registers outside the vblank
evasion since they won't latch until the arming register has been
written. This would make the critical section a bit lighter and thus
less likely to exceed the deadline.

v2: Rebase due to input CSC
v3: Swap LINOFF/TILEOFF and KEYMSK/KEYMAX to actually follow
    the last rule above (Matt)
    Add a bit more rationale to the commit message (Matt)

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |  52 ++++++------
 drivers/gpu/drm/i915/intel_sprite.c  | 118 ++++++++++++++++-----------
 2 files changed, 97 insertions(+), 73 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 132e978227fb..3c760a2eacc8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3314,7 +3314,6 @@ static void i9xx_update_plane(struct intel_plane *plane,
 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
 	u32 linear_offset;
 	u32 dspcntr = plane_state->ctl;
-	i915_reg_t reg = DSPCNTR(i9xx_plane);
 	int x = plane_state->color_plane[0].x;
 	int y = plane_state->color_plane[0].y;
 	unsigned long irqflags;
@@ -3329,41 +3328,45 @@ static void i9xx_update_plane(struct intel_plane *plane,
 
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
+	I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
+
 	if (INTEL_GEN(dev_priv) < 4) {
 		/* pipesrc and dspsize control the size that is scaled from,
 		 * which should always be the user's requested size.
 		 */
-		I915_WRITE_FW(DSPSIZE(i9xx_plane),
-			      ((crtc_state->pipe_src_h - 1) << 16) |
-			      (crtc_state->pipe_src_w - 1));
 		I915_WRITE_FW(DSPPOS(i9xx_plane), 0);
+		I915_WRITE_FW(DSPSIZE(i9xx_plane),
+			      ((crtc_state->pipe_src_h - 1) << 16) |
+			      (crtc_state->pipe_src_w - 1));
 	} else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
-		I915_WRITE_FW(PRIMSIZE(i9xx_plane),
-			      ((crtc_state->pipe_src_h - 1) << 16) |
-			      (crtc_state->pipe_src_w - 1));
 		I915_WRITE_FW(PRIMPOS(i9xx_plane), 0);
+		I915_WRITE_FW(PRIMSIZE(i9xx_plane),
+			      ((crtc_state->pipe_src_h - 1) << 16) |
+			      (crtc_state->pipe_src_w - 1));
 		I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
 	}
 
-	I915_WRITE_FW(reg, dspcntr);
-
-	I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-		I915_WRITE_FW(DSPSURF(i9xx_plane),
-			      intel_plane_ggtt_offset(plane_state) +
-			      dspaddr_offset);
 		I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
 	} else if (INTEL_GEN(dev_priv) >= 4) {
-		I915_WRITE_FW(DSPSURF(i9xx_plane),
-			      intel_plane_ggtt_offset(plane_state) +
-			      dspaddr_offset);
-		I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
 		I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset);
-	} else {
+		I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
+	}
+
+	/*
+	 * The control register self-arms if the plane was previously
+	 * disabled. Try to make the plane enable atomic by writing
+	 * the control register just before the surface register.
+	 */
+	I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
+	if (INTEL_GEN(dev_priv) >= 4)
+		I915_WRITE_FW(DSPSURF(i9xx_plane),
+			      intel_plane_ggtt_offset(plane_state) +
+			      dspaddr_offset);
+	else
 		I915_WRITE_FW(DSPADDR(i9xx_plane),
 			      intel_plane_ggtt_offset(plane_state) +
 			      dspaddr_offset);
-	}
 
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
@@ -10056,8 +10059,8 @@ static void i9xx_update_cursor(struct intel_plane *plane,
 	 * On some platforms writing CURCNTR first will also
 	 * cause CURPOS to be armed by the CURBASE write.
 	 * Without the CURCNTR write the CURPOS write would
-	 * arm itself. Thus we always start the full update
-	 * with a CURCNTR write.
+	 * arm itself. Thus we always update CURCNTR before
+	 * CURPOS.
 	 *
 	 * On other platforms CURPOS always requires the
 	 * CURBASE write to arm the update. Additonally
@@ -10067,15 +10070,16 @@ static void i9xx_update_cursor(struct intel_plane *plane,
 	 * cursor that doesn't appear to move, or even change
 	 * shape. Thus we always write CURBASE.
 	 *
-	 * CURCNTR and CUR_FBC_CTL are always
-	 * armed by the CURBASE write only.
+	 * The other registers are armed by by the CURBASE write
+	 * except when the plane is getting enabled at which time
+	 * the CURCNTR write arms the update.
 	 */
 	if (plane->cursor.base != base ||
 	    plane->cursor.size != fbc_ctl ||
 	    plane->cursor.cntl != cntl) {
-		I915_WRITE_FW(CURCNTR(pipe), cntl);
 		if (HAS_CUR_FBC(dev_priv))
 			I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
+		I915_WRITE_FW(CURCNTR(pipe), cntl);
 		I915_WRITE_FW(CURPOS(pipe), pos);
 		I915_WRITE_FW(CURBASE(pipe), base);
 
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 5e0f7b575a50..a80773211265 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -508,28 +508,12 @@ skl_program_plane(struct intel_plane *plane,
 
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
-	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
-		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
-			      plane_state->color_ctl);
-
-	if (fb->format->is_yuv && icl_is_hdr_plane(plane))
-		icl_program_input_csc_coeff(crtc_state, plane_state);
-
-	I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
-	I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax);
-	I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk);
-
-	I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
 	I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
+	I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 	I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
 	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
 		      (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
 
-	if (INTEL_GEN(dev_priv) < 11)
-		I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
-			      (plane_state->color_plane[1].y << 16) |
-			       plane_state->color_plane[1].x);
-
 	if (icl_is_hdr_plane(plane)) {
 		u32 cus_ctl = 0;
 
@@ -551,15 +535,36 @@ skl_program_plane(struct intel_plane *plane,
 		I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), cus_ctl);
 	}
 
-	if (!slave && plane_state->scaler_id >= 0)
-		skl_program_scaler(plane, crtc_state, plane_state);
+	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
+			      plane_state->color_ctl);
 
-	I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
+	if (fb->format->is_yuv && icl_is_hdr_plane(plane))
+		icl_program_input_csc_coeff(crtc_state, plane_state);
 
+	I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
+	I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk);
+	I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax);
+
+	I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
+
+	if (INTEL_GEN(dev_priv) < 11)
+		I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
+			      (plane_state->color_plane[1].y << 16) |
+			      plane_state->color_plane[1].x);
+
+	/*
+	 * The control register self-arms if the plane was previously
+	 * disabled. Try to make the plane enable atomic by writing
+	 * the control register just before the surface register.
+	 */
 	I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
 	I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
 		      intel_plane_ggtt_offset(plane_state) + surf_addr);
 
+	if (!slave && plane_state->scaler_id >= 0)
+		skl_program_scaler(plane, crtc_state, plane_state);
+
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 
@@ -821,24 +826,29 @@ vlv_update_plane(struct intel_plane *plane,
 
 	vlv_update_clrc(plane_state);
 
+	I915_WRITE_FW(SPSTRIDE(pipe, plane_id),
+		      plane_state->color_plane[0].stride);
+	I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
+	I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
+	I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
+
 	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
 		chv_update_csc(plane_state);
 
 	if (key->flags) {
 		I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
-		I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
 		I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
+		I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
 	}
-	I915_WRITE_FW(SPSTRIDE(pipe, plane_id),
-		      plane_state->color_plane[0].stride);
-	I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 
-	I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
 	I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
+	I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
 
-	I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
-
-	I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
+	/*
+	 * The control register self-arms if the plane was previously
+	 * disabled. Try to make the plane enable atomic by writing
+	 * the control register just before the surface register.
+	 */
 	I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
 	I915_WRITE_FW(SPSURF(pipe, plane_id),
 		      intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
@@ -980,27 +990,32 @@ ivb_update_plane(struct intel_plane *plane,
 
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
-	if (key->flags) {
-		I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
-		I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
-		I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
-	}
-
 	I915_WRITE_FW(SPRSTRIDE(pipe), plane_state->color_plane[0].stride);
 	I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
+	I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
+	if (IS_IVYBRIDGE(dev_priv))
+		I915_WRITE_FW(SPRSCALE(pipe), sprscale);
+
+	if (key->flags) {
+		I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
+		I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
+		I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
+	}
 
 	/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 	 * register */
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 		I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
 	} else {
-		I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
 		I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
+		I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
 	}
 
-	I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
-	if (IS_IVYBRIDGE(dev_priv))
-		I915_WRITE_FW(SPRSCALE(pipe), sprscale);
+	/*
+	 * The control register self-arms if the plane was previously
+	 * disabled. Try to make the plane enable atomic by writing
+	 * the control register just before the surface register.
+	 */
 	I915_WRITE_FW(SPRCTL(pipe), sprctl);
 	I915_WRITE_FW(SPRSURF(pipe),
 		      intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
@@ -1018,7 +1033,7 @@ ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
 	I915_WRITE_FW(SPRCTL(pipe), 0);
-	/* Can't leave the scaler enabled... */
+	/* Disable the scaler */
 	if (IS_IVYBRIDGE(dev_priv))
 		I915_WRITE_FW(SPRSCALE(pipe), 0);
 	I915_WRITE_FW(SPRSURF(pipe), 0);
@@ -1148,20 +1163,25 @@ g4x_update_plane(struct intel_plane *plane,
 
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
-	if (key->flags) {
-		I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
-		I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
-		I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
-	}
-
 	I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride);
 	I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
-
-	I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
-	I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
-
 	I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 	I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
+
+	if (key->flags) {
+		I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
+		I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
+		I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
+	}
+
+	I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
+	I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
+
+	/*
+	 * The control register self-arms if the plane was previously
+	 * disabled. Try to make the plane enable atomic by writing
+	 * the control register just before the surface register.
+	 */
 	I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
 	I915_WRITE_FW(DVSSURF(pipe),
 		      intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
-- 
2.18.1

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Re: [PATCH v2 01/13] drm/i915: Reorganize plane register writes to make them more atomic

[Matt Roper]

On Wed, Nov 14, 2018 at 11:07:17PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Some observations about the plane registers:
> - the control register will self-arm if the plane is not already
>   enabled, thus we want to write it as close to (or ideally after)
>   the surface register
> - tileoff/linoff/offset/aux_offset are self-arming as well so we want
>   them close to the surface register as well
> - color keying registers we maybe self arming before SKL. Not 100%
>   sure but we can try to keep them near to the surface register
>   as well
> - chv pipe b csc register are double buffered but self arming so
>   moving them down a bit
> - the rest should be mostly armed by the surface register so we can
>   safely write them first, and to just for some consistency let's try
>   to follow keep them in order based on the register offset
> 
> None of this will have any effect of course unless the vblank evasion
> fails (which it still does sometimes). Another potential future benefit
> might be pulling the non-self armings registers outside the vblank
> evasion since they won't latch until the arming register has been
> written. This would make the critical section a bit lighter and thus
> less likely to exceed the deadline.
> 
> v2: Rebase due to input CSC
> v3: Swap LINOFF/TILEOFF and KEYMSK/KEYMAX to actually follow
>     the last rule above (Matt)
>     Add a bit more rationale to the commit message (Matt)
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c |  52 ++++++------
>  drivers/gpu/drm/i915/intel_sprite.c  | 118 ++++++++++++++++-----------
>  2 files changed, 97 insertions(+), 73 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 132e978227fb..3c760a2eacc8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3314,7 +3314,6 @@ static void i9xx_update_plane(struct intel_plane *plane,
>  	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
>  	u32 linear_offset;
>  	u32 dspcntr = plane_state->ctl;
> -	i915_reg_t reg = DSPCNTR(i9xx_plane);
>  	int x = plane_state->color_plane[0].x;
>  	int y = plane_state->color_plane[0].y;
>  	unsigned long irqflags;
> @@ -3329,41 +3328,45 @@ static void i9xx_update_plane(struct intel_plane *plane,
>  
>  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>  
> +	I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
> +
>  	if (INTEL_GEN(dev_priv) < 4) {
>  		/* pipesrc and dspsize control the size that is scaled from,
>  		 * which should always be the user's requested size.
>  		 */
> -		I915_WRITE_FW(DSPSIZE(i9xx_plane),
> -			      ((crtc_state->pipe_src_h - 1) << 16) |
> -			      (crtc_state->pipe_src_w - 1));
>  		I915_WRITE_FW(DSPPOS(i9xx_plane), 0);
> +		I915_WRITE_FW(DSPSIZE(i9xx_plane),
> +			      ((crtc_state->pipe_src_h - 1) << 16) |
> +			      (crtc_state->pipe_src_w - 1));
>  	} else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
> -		I915_WRITE_FW(PRIMSIZE(i9xx_plane),
> -			      ((crtc_state->pipe_src_h - 1) << 16) |
> -			      (crtc_state->pipe_src_w - 1));
>  		I915_WRITE_FW(PRIMPOS(i9xx_plane), 0);
> +		I915_WRITE_FW(PRIMSIZE(i9xx_plane),
> +			      ((crtc_state->pipe_src_h - 1) << 16) |
> +			      (crtc_state->pipe_src_w - 1));
>  		I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
>  	}
>  
> -	I915_WRITE_FW(reg, dspcntr);
> -
> -	I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> -		I915_WRITE_FW(DSPSURF(i9xx_plane),
> -			      intel_plane_ggtt_offset(plane_state) +
> -			      dspaddr_offset);
>  		I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
>  	} else if (INTEL_GEN(dev_priv) >= 4) {
> -		I915_WRITE_FW(DSPSURF(i9xx_plane),
> -			      intel_plane_ggtt_offset(plane_state) +
> -			      dspaddr_offset);
> -		I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
>  		I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset);
> -	} else {
> +		I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
> +	}
> +
> +	/*
> +	 * The control register self-arms if the plane was previously
> +	 * disabled. Try to make the plane enable atomic by writing
> +	 * the control register just before the surface register.
> +	 */
> +	I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
> +	if (INTEL_GEN(dev_priv) >= 4)
> +		I915_WRITE_FW(DSPSURF(i9xx_plane),
> +			      intel_plane_ggtt_offset(plane_state) +
> +			      dspaddr_offset);
> +	else
>  		I915_WRITE_FW(DSPADDR(i9xx_plane),
>  			      intel_plane_ggtt_offset(plane_state) +
>  			      dspaddr_offset);
> -	}
>  
>  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>  }
> @@ -10056,8 +10059,8 @@ static void i9xx_update_cursor(struct intel_plane *plane,
>  	 * On some platforms writing CURCNTR first will also
>  	 * cause CURPOS to be armed by the CURBASE write.
>  	 * Without the CURCNTR write the CURPOS write would
> -	 * arm itself. Thus we always start the full update
> -	 * with a CURCNTR write.
> +	 * arm itself. Thus we always update CURCNTR before
> +	 * CURPOS.
>  	 *
>  	 * On other platforms CURPOS always requires the
>  	 * CURBASE write to arm the update. Additonally
> @@ -10067,15 +10070,16 @@ static void i9xx_update_cursor(struct intel_plane *plane,
>  	 * cursor that doesn't appear to move, or even change
>  	 * shape. Thus we always write CURBASE.
>  	 *
> -	 * CURCNTR and CUR_FBC_CTL are always
> -	 * armed by the CURBASE write only.
> +	 * The other registers are armed by by the CURBASE write
> +	 * except when the plane is getting enabled at which time
> +	 * the CURCNTR write arms the update.
>  	 */
>  	if (plane->cursor.base != base ||
>  	    plane->cursor.size != fbc_ctl ||
>  	    plane->cursor.cntl != cntl) {
> -		I915_WRITE_FW(CURCNTR(pipe), cntl);
>  		if (HAS_CUR_FBC(dev_priv))
>  			I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
> +		I915_WRITE_FW(CURCNTR(pipe), cntl);
>  		I915_WRITE_FW(CURPOS(pipe), pos);
>  		I915_WRITE_FW(CURBASE(pipe), base);
>  
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 5e0f7b575a50..a80773211265 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -508,28 +508,12 @@ skl_program_plane(struct intel_plane *plane,
>  
>  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>  
> -	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> -		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
> -			      plane_state->color_ctl);
> -
> -	if (fb->format->is_yuv && icl_is_hdr_plane(plane))
> -		icl_program_input_csc_coeff(crtc_state, plane_state);
> -
> -	I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
> -	I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax);
> -	I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk);
> -
> -	I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
>  	I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
> +	I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
>  	I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
>  	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
>  		      (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
>  
> -	if (INTEL_GEN(dev_priv) < 11)
> -		I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
> -			      (plane_state->color_plane[1].y << 16) |
> -			       plane_state->color_plane[1].x);
> -
>  	if (icl_is_hdr_plane(plane)) {
>  		u32 cus_ctl = 0;
>  
> @@ -551,15 +535,36 @@ skl_program_plane(struct intel_plane *plane,
>  		I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), cus_ctl);
>  	}
>  
> -	if (!slave && plane_state->scaler_id >= 0)
> -		skl_program_scaler(plane, crtc_state, plane_state);
> +	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> +		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
> +			      plane_state->color_ctl);
>  
> -	I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
> +	if (fb->format->is_yuv && icl_is_hdr_plane(plane))
> +		icl_program_input_csc_coeff(crtc_state, plane_state);
>  
> +	I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
> +	I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk);
> +	I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax);
> +
> +	I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
> +
> +	if (INTEL_GEN(dev_priv) < 11)
> +		I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
> +			      (plane_state->color_plane[1].y << 16) |
> +			      plane_state->color_plane[1].x);
> +
> +	/*
> +	 * The control register self-arms if the plane was previously
> +	 * disabled. Try to make the plane enable atomic by writing
> +	 * the control register just before the surface register.
> +	 */
>  	I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
>  	I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
>  		      intel_plane_ggtt_offset(plane_state) + surf_addr);
>  
> +	if (!slave && plane_state->scaler_id >= 0)
> +		skl_program_scaler(plane, crtc_state, plane_state);
> +
>  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>  }
>  
> @@ -821,24 +826,29 @@ vlv_update_plane(struct intel_plane *plane,
>  
>  	vlv_update_clrc(plane_state);
>  
> +	I915_WRITE_FW(SPSTRIDE(pipe, plane_id),
> +		      plane_state->color_plane[0].stride);
> +	I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
> +	I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
> +	I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
> +
>  	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
>  		chv_update_csc(plane_state);
>  
>  	if (key->flags) {
>  		I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
> -		I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
>  		I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
> +		I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
>  	}
> -	I915_WRITE_FW(SPSTRIDE(pipe, plane_id),
> -		      plane_state->color_plane[0].stride);
> -	I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
>  
> -	I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
>  	I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
> +	I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
>  
> -	I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
> -
> -	I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
> +	/*
> +	 * The control register self-arms if the plane was previously
> +	 * disabled. Try to make the plane enable atomic by writing
> +	 * the control register just before the surface register.
> +	 */
>  	I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
>  	I915_WRITE_FW(SPSURF(pipe, plane_id),
>  		      intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
> @@ -980,27 +990,32 @@ ivb_update_plane(struct intel_plane *plane,
>  
>  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>  
> -	if (key->flags) {
> -		I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
> -		I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
> -		I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
> -	}
> -
>  	I915_WRITE_FW(SPRSTRIDE(pipe), plane_state->color_plane[0].stride);
>  	I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
> +	I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
> +	if (IS_IVYBRIDGE(dev_priv))
> +		I915_WRITE_FW(SPRSCALE(pipe), sprscale);
> +
> +	if (key->flags) {
> +		I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
> +		I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
> +		I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
> +	}
>  
>  	/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
>  	 * register */
>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
>  		I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
>  	} else {
> -		I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
>  		I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
> +		I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
>  	}
>  
> -	I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
> -	if (IS_IVYBRIDGE(dev_priv))
> -		I915_WRITE_FW(SPRSCALE(pipe), sprscale);
> +	/*
> +	 * The control register self-arms if the plane was previously
> +	 * disabled. Try to make the plane enable atomic by writing
> +	 * the control register just before the surface register.
> +	 */
>  	I915_WRITE_FW(SPRCTL(pipe), sprctl);
>  	I915_WRITE_FW(SPRSURF(pipe),
>  		      intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
> @@ -1018,7 +1033,7 @@ ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
>  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>  
>  	I915_WRITE_FW(SPRCTL(pipe), 0);
> -	/* Can't leave the scaler enabled... */
> +	/* Disable the scaler */
>  	if (IS_IVYBRIDGE(dev_priv))
>  		I915_WRITE_FW(SPRSCALE(pipe), 0);
>  	I915_WRITE_FW(SPRSURF(pipe), 0);
> @@ -1148,20 +1163,25 @@ g4x_update_plane(struct intel_plane *plane,
>  
>  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>  
> -	if (key->flags) {
> -		I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
> -		I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
> -		I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
> -	}
> -
>  	I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride);
>  	I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
> -
> -	I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
> -	I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
> -
>  	I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
>  	I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
> +
> +	if (key->flags) {
> +		I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
> +		I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
> +		I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
> +	}
> +
> +	I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
> +	I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
> +
> +	/*
> +	 * The control register self-arms if the plane was previously
> +	 * disabled. Try to make the plane enable atomic by writing
> +	 * the control register just before the surface register.
> +	 */
>  	I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
>  	I915_WRITE_FW(DVSSURF(pipe),
>  		      intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
> -- 
> 2.18.1
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2 02/13] drm/i915: Move single buffered plane register writes to the end

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The plane color correction registers are single buffered. So
ideally we would write them at the start of vblank just after the
double buffered plane registers have been latched. Since we have
no convenient way to do that for now let's at least move the
single buffered register writes to happen after the double
buffered registers have been written.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_sprite.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index a80773211265..6403ef2219d0 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -824,8 +824,6 @@ vlv_update_plane(struct intel_plane *plane,
 
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
-	vlv_update_clrc(plane_state);
-
 	I915_WRITE_FW(SPSTRIDE(pipe, plane_id),
 		      plane_state->color_plane[0].stride);
 	I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
@@ -853,6 +851,8 @@ vlv_update_plane(struct intel_plane *plane,
 	I915_WRITE_FW(SPSURF(pipe, plane_id),
 		      intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 
+	vlv_update_clrc(plane_state);
+
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 
-- 
2.18.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 02/13] drm/i915: Move single buffered plane register writes to the end

[Matt Roper]

On Wed, Nov 14, 2018 at 11:07:18PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The plane color correction registers are single buffered. So
> ideally we would write them at the start of vblank just after the
> double buffered plane registers have been latched. Since we have
> no convenient way to do that for now let's at least move the
> single buffered register writes to happen after the double
> buffered registers have been written.
> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_sprite.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index a80773211265..6403ef2219d0 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -824,8 +824,6 @@ vlv_update_plane(struct intel_plane *plane,
>  
>  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>  
> -	vlv_update_clrc(plane_state);
> -
>  	I915_WRITE_FW(SPSTRIDE(pipe, plane_id),
>  		      plane_state->color_plane[0].stride);
>  	I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
> @@ -853,6 +851,8 @@ vlv_update_plane(struct intel_plane *plane,
>  	I915_WRITE_FW(SPSURF(pipe, plane_id),
>  		      intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
>  
> +	vlv_update_clrc(plane_state);
> +
>  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>  }
>  
> -- 
> 2.18.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2 03/13] drm/i915: Introduce crtc_state->update_planes bitmask

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Keep track which planes need updating during the commit. For now this
is just (was_visible || is_visible) but I'll have need to update
invisible planes later on for skl plane ddbs and for pre-skl pipe
gamma/csc control (which lives in the primary plane control register).

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_atomic.c       | 1 +
 drivers/gpu/drm/i915/intel_atomic_plane.c | 8 ++++----
 drivers/gpu/drm/i915/intel_display.c      | 5 ++++-
 drivers/gpu/drm/i915/intel_drv.h          | 3 +++
 4 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index a5a2c8fe58a7..8cb02f28d30c 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -184,6 +184,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
 	crtc_state->fifo_changed = false;
 	crtc_state->wm.need_postvbl_update = false;
 	crtc_state->fb_bits = 0;
+	crtc_state->update_planes = 0;
 
 	return &crtc_state->base;
 }
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 7d3685075201..010269a12390 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -137,6 +137,9 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 	if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
 		crtc_state->nv12_planes |= BIT(intel_plane->id);
 
+	if (state->visible || old_plane_state->base.visible)
+		crtc_state->update_planes |= BIT(intel_plane->id);
+
 	return intel_plane_atomic_calc_changes(old_crtc_state,
 					       &crtc_state->base,
 					       old_plane_state,
@@ -171,14 +174,11 @@ void intel_update_planes_on_crtc(struct intel_atomic_state *old_state,
 				 struct intel_crtc_state *old_crtc_state,
 				 struct intel_crtc_state *new_crtc_state)
 {
+	u32 update_mask = new_crtc_state->update_planes;
 	struct intel_plane_state *new_plane_state;
 	struct intel_plane *plane;
-	u32 update_mask;
 	int i;
 
-	update_mask = old_crtc_state->active_planes;
-	update_mask |= new_crtc_state->active_planes;
-
 	for_each_new_intel_plane_in_state(old_state, plane, new_plane_state, i) {
 		if (crtc->pipe != plane->pipe ||
 		    !(update_mask & BIT(plane->id)))
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3c760a2eacc8..065c8befc6f8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10808,8 +10808,10 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
 			continue;
 
 		plane_state->linked_plane = NULL;
-		if (plane_state->slave && !plane_state->base.visible)
+		if (plane_state->slave && !plane_state->base.visible) {
 			crtc_state->active_planes &= ~BIT(plane->id);
+			crtc_state->update_planes |= BIT(plane->id);
+		}
 
 		plane_state->slave = false;
 	}
@@ -10850,6 +10852,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
 		linked_state->slave = true;
 		linked_state->linked_plane = plane;
 		crtc_state->active_planes |= BIT(linked->id);
+		crtc_state->update_planes |= BIT(linked->id);
 		DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name);
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 18b419f7f7fe..b0a24a81780a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -925,6 +925,9 @@ struct intel_crtc_state {
 	u8 active_planes;
 	u8 nv12_planes;
 
+	/* bitmask of planes that will be updated during the commit */
+	u8 update_planes;
+
 	/* HDMI scrambling status */
 	bool hdmi_scrambling;
 
-- 
2.18.1

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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 03/13] drm/i915: Introduce crtc_state->update_planes bitmask

[Matt Roper]

On Wed, Nov 14, 2018 at 11:07:19PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Keep track which planes need updating during the commit. For now this
> is just (was_visible || is_visible) but I'll have need to update

I still think it would be a good idea to mention was_slave || is_slave
here for completeness, but either way,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> invisible planes later on for skl plane ddbs and for pre-skl pipe
> gamma/csc control (which lives in the primary plane control register).
> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_atomic.c       | 1 +
>  drivers/gpu/drm/i915/intel_atomic_plane.c | 8 ++++----
>  drivers/gpu/drm/i915/intel_display.c      | 5 ++++-
>  drivers/gpu/drm/i915/intel_drv.h          | 3 +++
>  4 files changed, 12 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> index a5a2c8fe58a7..8cb02f28d30c 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -184,6 +184,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
>  	crtc_state->fifo_changed = false;
>  	crtc_state->wm.need_postvbl_update = false;
>  	crtc_state->fb_bits = 0;
> +	crtc_state->update_planes = 0;
>  
>  	return &crtc_state->base;
>  }
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index 7d3685075201..010269a12390 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -137,6 +137,9 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
>  	if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
>  		crtc_state->nv12_planes |= BIT(intel_plane->id);
>  
> +	if (state->visible || old_plane_state->base.visible)
> +		crtc_state->update_planes |= BIT(intel_plane->id);
> +
>  	return intel_plane_atomic_calc_changes(old_crtc_state,
>  					       &crtc_state->base,
>  					       old_plane_state,
> @@ -171,14 +174,11 @@ void intel_update_planes_on_crtc(struct intel_atomic_state *old_state,
>  				 struct intel_crtc_state *old_crtc_state,
>  				 struct intel_crtc_state *new_crtc_state)
>  {
> +	u32 update_mask = new_crtc_state->update_planes;
>  	struct intel_plane_state *new_plane_state;
>  	struct intel_plane *plane;
> -	u32 update_mask;
>  	int i;
>  
> -	update_mask = old_crtc_state->active_planes;
> -	update_mask |= new_crtc_state->active_planes;
> -
>  	for_each_new_intel_plane_in_state(old_state, plane, new_plane_state, i) {
>  		if (crtc->pipe != plane->pipe ||
>  		    !(update_mask & BIT(plane->id)))
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3c760a2eacc8..065c8befc6f8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10808,8 +10808,10 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
>  			continue;
>  
>  		plane_state->linked_plane = NULL;
> -		if (plane_state->slave && !plane_state->base.visible)
> +		if (plane_state->slave && !plane_state->base.visible) {
>  			crtc_state->active_planes &= ~BIT(plane->id);
> +			crtc_state->update_planes |= BIT(plane->id);
> +		}
>  
>  		plane_state->slave = false;
>  	}
> @@ -10850,6 +10852,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
>  		linked_state->slave = true;
>  		linked_state->linked_plane = plane;
>  		crtc_state->active_planes |= BIT(linked->id);
> +		crtc_state->update_planes |= BIT(linked->id);
>  		DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name);
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 18b419f7f7fe..b0a24a81780a 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -925,6 +925,9 @@ struct intel_crtc_state {
>  	u8 active_planes;
>  	u8 nv12_planes;
>  
> +	/* bitmask of planes that will be updated during the commit */
> +	u8 update_planes;
> +
>  	/* HDMI scrambling status */
>  	bool hdmi_scrambling;
>  
> -- 
> 2.18.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
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Re: [PATCH v2 03/13] drm/i915: Introduce crtc_state->update_planes bitmask

[Ville Syrjälä]

On Mon, Nov 19, 2018 at 03:14:14PM -0800, Matt Roper wrote:
> On Wed, Nov 14, 2018 at 11:07:19PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Keep track which planes need updating during the commit. For now this
> > is just (was_visible || is_visible) but I'll have need to update
> 
> I still think it would be a good idea to mention was_slave || is_slave
> here for completeness, but either way,

Ah, didn't even realize I didn't mention it. I'll add a few choice
words.

> 
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> 
> > invisible planes later on for skl plane ddbs and for pre-skl pipe
> > gamma/csc control (which lives in the primary plane control register).
> > 
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_atomic.c       | 1 +
> >  drivers/gpu/drm/i915/intel_atomic_plane.c | 8 ++++----
> >  drivers/gpu/drm/i915/intel_display.c      | 5 ++++-
> >  drivers/gpu/drm/i915/intel_drv.h          | 3 +++
> >  4 files changed, 12 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> > index a5a2c8fe58a7..8cb02f28d30c 100644
> > --- a/drivers/gpu/drm/i915/intel_atomic.c
> > +++ b/drivers/gpu/drm/i915/intel_atomic.c
> > @@ -184,6 +184,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
> >  	crtc_state->fifo_changed = false;
> >  	crtc_state->wm.need_postvbl_update = false;
> >  	crtc_state->fb_bits = 0;
> > +	crtc_state->update_planes = 0;
> >  
> >  	return &crtc_state->base;
> >  }
> > diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
> > index 7d3685075201..010269a12390 100644
> > --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> > +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> > @@ -137,6 +137,9 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
> >  	if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
> >  		crtc_state->nv12_planes |= BIT(intel_plane->id);
> >  
> > +	if (state->visible || old_plane_state->base.visible)
> > +		crtc_state->update_planes |= BIT(intel_plane->id);
> > +
> >  	return intel_plane_atomic_calc_changes(old_crtc_state,
> >  					       &crtc_state->base,
> >  					       old_plane_state,
> > @@ -171,14 +174,11 @@ void intel_update_planes_on_crtc(struct intel_atomic_state *old_state,
> >  				 struct intel_crtc_state *old_crtc_state,
> >  				 struct intel_crtc_state *new_crtc_state)
> >  {
> > +	u32 update_mask = new_crtc_state->update_planes;
> >  	struct intel_plane_state *new_plane_state;
> >  	struct intel_plane *plane;
> > -	u32 update_mask;
> >  	int i;
> >  
> > -	update_mask = old_crtc_state->active_planes;
> > -	update_mask |= new_crtc_state->active_planes;
> > -
> >  	for_each_new_intel_plane_in_state(old_state, plane, new_plane_state, i) {
> >  		if (crtc->pipe != plane->pipe ||
> >  		    !(update_mask & BIT(plane->id)))
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 3c760a2eacc8..065c8befc6f8 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -10808,8 +10808,10 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
> >  			continue;
> >  
> >  		plane_state->linked_plane = NULL;
> > -		if (plane_state->slave && !plane_state->base.visible)
> > +		if (plane_state->slave && !plane_state->base.visible) {
> >  			crtc_state->active_planes &= ~BIT(plane->id);
> > +			crtc_state->update_planes |= BIT(plane->id);
> > +		}
> >  
> >  		plane_state->slave = false;
> >  	}
> > @@ -10850,6 +10852,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
> >  		linked_state->slave = true;
> >  		linked_state->linked_plane = plane;
> >  		crtc_state->active_planes |= BIT(linked->id);
> > +		crtc_state->update_planes |= BIT(linked->id);
> >  		DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name);
> >  	}
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 18b419f7f7fe..b0a24a81780a 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -925,6 +925,9 @@ struct intel_crtc_state {
> >  	u8 active_planes;
> >  	u8 nv12_planes;
> >  
> > +	/* bitmask of planes that will be updated during the commit */
> > +	u8 update_planes;
> > +
> >  	/* HDMI scrambling status */
> >  	bool hdmi_scrambling;
> >  
> > -- 
> > 2.18.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795

-- 
Ville Syrjälä
Intel
_______________________________________________
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[PATCH v3 03/13] drm/i915: Introduce crtc_state->update_planes bitmask

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Keep track which planes need updating during the commit. For now
we set the bit for any plane that was or will be visible (including
icl+ nv12 slave planes). In the future I'll have need to update
invisible planes as well, for skl plane ddbs and for pre-skl pipe
gamma/csc control (which lives in the primary plane control register).

v2: Pimp the commit message to mention icl+ nv12 slave planes (Matt)

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_atomic.c       | 1 +
 drivers/gpu/drm/i915/intel_atomic_plane.c | 8 ++++----
 drivers/gpu/drm/i915/intel_display.c      | 5 ++++-
 drivers/gpu/drm/i915/intel_drv.h          | 3 +++
 4 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index a5a2c8fe58a7..8cb02f28d30c 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -184,6 +184,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
 	crtc_state->fifo_changed = false;
 	crtc_state->wm.need_postvbl_update = false;
 	crtc_state->fb_bits = 0;
+	crtc_state->update_planes = 0;
 
 	return &crtc_state->base;
 }
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 905f8ef3ba4f..026a11511941 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -139,6 +139,9 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 	if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
 		crtc_state->nv12_planes |= BIT(intel_plane->id);
 
+	if (state->visible || old_plane_state->base.visible)
+		crtc_state->update_planes |= BIT(intel_plane->id);
+
 	return intel_plane_atomic_calc_changes(old_crtc_state,
 					       &crtc_state->base,
 					       old_plane_state,
@@ -173,14 +176,11 @@ void intel_update_planes_on_crtc(struct intel_atomic_state *old_state,
 				 struct intel_crtc_state *old_crtc_state,
 				 struct intel_crtc_state *new_crtc_state)
 {
+	u32 update_mask = new_crtc_state->update_planes;
 	struct intel_plane_state *new_plane_state;
 	struct intel_plane *plane;
-	u32 update_mask;
 	int i;
 
-	update_mask = old_crtc_state->active_planes;
-	update_mask |= new_crtc_state->active_planes;
-
 	for_each_new_intel_plane_in_state(old_state, plane, new_plane_state, i) {
 		if (crtc->pipe != plane->pipe ||
 		    !(update_mask & BIT(plane->id)))
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3516b3d04787..4469b4511c92 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10839,8 +10839,10 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
 			continue;
 
 		plane_state->linked_plane = NULL;
-		if (plane_state->slave && !plane_state->base.visible)
+		if (plane_state->slave && !plane_state->base.visible) {
 			crtc_state->active_planes &= ~BIT(plane->id);
+			crtc_state->update_planes |= BIT(plane->id);
+		}
 
 		plane_state->slave = false;
 	}
@@ -10881,6 +10883,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
 		linked_state->slave = true;
 		linked_state->linked_plane = plane;
 		crtc_state->active_planes |= BIT(linked->id);
+		crtc_state->update_planes |= BIT(linked->id);
 		DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name);
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a62d77b76291..1f29061cefa1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -926,6 +926,9 @@ struct intel_crtc_state {
 	u8 active_planes;
 	u8 nv12_planes;
 
+	/* bitmask of planes that will be updated during the commit */
+	u8 update_planes;
+
 	/* HDMI scrambling status */
 	bool hdmi_scrambling;
 
-- 
2.18.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2 04/13] drm/i915: Pass the new crtc_state to ->disable_plane()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We're going to need access to the new crtc state in ->disable_plane()
for SKL+ wm/ddb programming and pre-skl pipe gamma/csc control. Pass
the crtc state down.

We'll also try to make intel_crtc_disable_planes() do the right
thing as much as it's possible. The fact that we don't have a
separate crtc state for the disabled state when we're going to
re-enable the crtc later means we might end up poking at a few
extra planes in there. But that's harmless. I suppose one might
argue that we wouldn't have to care about proper ddb/wm/csc/gamma
if the pipe is going to permanently disable anyway, but the state
checker probably cares so we should try our best to make sure
everything is programmed correctly even in that case.

v2: Fix the commit message a bit (Matt)

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_atomic_plane.c |  2 +-
 drivers/gpu/drm/i915/intel_display.c      | 39 ++++++++++++++---------
 drivers/gpu/drm/i915/intel_display.h      |  8 +++++
 drivers/gpu/drm/i915/intel_drv.h          |  2 +-
 drivers/gpu/drm/i915/intel_sprite.c       | 12 ++++---
 5 files changed, 42 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 010269a12390..69fc7010190c 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -210,7 +210,7 @@ void intel_update_planes_on_crtc(struct intel_atomic_state *old_state,
 		} else {
 			trace_intel_disable_plane(&plane->base, crtc);
 
-			plane->disable_plane(plane, crtc);
+			plane->disable_plane(plane, new_crtc_state);
 		}
 	}
 }
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 065c8befc6f8..0caba7258fee 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2767,7 +2767,7 @@ static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 		intel_pre_disable_primary_noatomic(&crtc->base);
 
 	trace_intel_disable_plane(&plane->base, crtc);
-	plane->disable_plane(plane, crtc);
+	plane->disable_plane(plane, crtc_state);
 }
 
 static void
@@ -3372,7 +3372,7 @@ static void i9xx_update_plane(struct intel_plane *plane,
 }
 
 static void i9xx_disable_plane(struct intel_plane *plane,
-			       struct intel_crtc *crtc)
+			       const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
@@ -5405,23 +5405,32 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 		intel_update_watermarks(crtc);
 }
 
-static void intel_crtc_disable_planes(struct intel_crtc *crtc, unsigned plane_mask)
+static void intel_crtc_disable_planes(struct intel_atomic_state *state,
+				      struct intel_crtc *crtc)
 {
-	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct intel_crtc_state *new_crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	unsigned int update_mask = new_crtc_state->update_planes;
+	const struct intel_plane_state *old_plane_state;
 	struct intel_plane *plane;
 	unsigned fb_bits = 0;
+	int i;
 
 	intel_crtc_dpms_overlay_disable(crtc);
 
-	for_each_intel_plane_on_crtc(dev, crtc, plane) {
-		if (plane_mask & BIT(plane->id)) {
-			plane->disable_plane(plane, crtc);
+	for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
+		if (crtc->pipe != plane->pipe ||
+		    !(update_mask & BIT(plane->id)))
+			continue;
 
+		plane->disable_plane(plane, new_crtc_state);
+
+		if (old_plane_state->base.visible)
 			fb_bits |= plane->frontbuffer_bit;
-		}
 	}
 
-	intel_frontbuffer_flip(to_i915(dev), fb_bits);
+	intel_frontbuffer_flip(dev_priv, fb_bits);
 }
 
 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
@@ -9866,9 +9875,9 @@ static void i845_update_cursor(struct intel_plane *plane,
 }
 
 static void i845_disable_cursor(struct intel_plane *plane,
-				struct intel_crtc *crtc)
+				const struct intel_crtc_state *crtc_state)
 {
-	i845_update_cursor(plane, NULL, NULL);
+	i845_update_cursor(plane, crtc_state, NULL);
 }
 
 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
@@ -10095,9 +10104,9 @@ static void i9xx_update_cursor(struct intel_plane *plane,
 }
 
 static void i9xx_disable_cursor(struct intel_plane *plane,
-				struct intel_crtc *crtc)
+				const struct intel_crtc_state *crtc_state)
 {
-	i9xx_update_cursor(plane, NULL, NULL);
+	i9xx_update_cursor(plane, crtc_state, NULL);
 }
 
 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
@@ -12861,7 +12870,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
 		intel_pre_plane_update(old_intel_crtc_state, new_intel_crtc_state);
 
 		if (old_crtc_state->active) {
-			intel_crtc_disable_planes(intel_crtc, old_intel_crtc_state->active_planes);
+			intel_crtc_disable_planes(intel_state, intel_crtc);
 
 			/*
 			 * We need to disable pipe CRC before disabling the pipe,
@@ -13711,7 +13720,7 @@ intel_legacy_cursor_update(struct drm_plane *plane,
 					  to_intel_plane_state(plane->state));
 	} else {
 		trace_intel_disable_plane(plane, to_intel_crtc(crtc));
-		intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
+		intel_plane->disable_plane(intel_plane, crtc_state);
 	}
 
 	intel_plane_unpin_fb(to_intel_plane_state(old_plane_state));
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index 5d50decbcbb5..df9e6ebb27de 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -382,6 +382,14 @@ struct intel_link_m_n {
 	for_each_power_well_rev(__dev_priv, __power_well)		        \
 		for_each_if((__power_well)->desc->domains & (__domain_mask))
 
+#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
+		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
+		      (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
+	     (__i)++) \
+		for_each_if(plane)
+
 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
 	for ((__i) = 0; \
 	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b0a24a81780a..23b33970db17 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1015,7 +1015,7 @@ struct intel_plane {
 			     const struct intel_crtc_state *crtc_state,
 			     const struct intel_plane_state *plane_state);
 	void (*disable_plane)(struct intel_plane *plane,
-			      struct intel_crtc *crtc);
+			      const struct intel_crtc_state *crtc_state);
 	bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
 	int (*check_plane)(struct intel_crtc_state *crtc_state,
 			   struct intel_plane_state *plane_state);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 6403ef2219d0..74d904a49bf9 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -594,7 +594,8 @@ icl_update_slave(struct intel_plane *plane,
 }
 
 static void
-skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
+skl_disable_plane(struct intel_plane *plane,
+		  const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	enum plane_id plane_id = plane->id;
@@ -857,7 +858,8 @@ vlv_update_plane(struct intel_plane *plane,
 }
 
 static void
-vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
+vlv_disable_plane(struct intel_plane *plane,
+		  const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	enum pipe pipe = plane->pipe;
@@ -1024,7 +1026,8 @@ ivb_update_plane(struct intel_plane *plane,
 }
 
 static void
-ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
+ivb_disable_plane(struct intel_plane *plane,
+		  const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	enum pipe pipe = plane->pipe;
@@ -1190,7 +1193,8 @@ g4x_update_plane(struct intel_plane *plane,
 }
 
 static void
-g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
+g4x_disable_plane(struct intel_plane *plane,
+		  const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	enum pipe pipe = plane->pipe;
-- 
2.18.1

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Re: [PATCH v2 04/13] drm/i915: Pass the new crtc_state to ->disable_plane()

[Matt Roper]

On Wed, Nov 14, 2018 at 11:07:20PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We're going to need access to the new crtc state in ->disable_plane()
> for SKL+ wm/ddb programming and pre-skl pipe gamma/csc control. Pass
> the crtc state down.
> 
> We'll also try to make intel_crtc_disable_planes() do the right
> thing as much as it's possible. The fact that we don't have a
> separate crtc state for the disabled state when we're going to
> re-enable the crtc later means we might end up poking at a few
> extra planes in there. But that's harmless. I suppose one might
> argue that we wouldn't have to care about proper ddb/wm/csc/gamma
> if the pipe is going to permanently disable anyway, but the state
> checker probably cares so we should try our best to make sure
> everything is programmed correctly even in that case.
> 
> v2: Fix the commit message a bit (Matt)
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_atomic_plane.c |  2 +-
>  drivers/gpu/drm/i915/intel_display.c      | 39 ++++++++++++++---------
>  drivers/gpu/drm/i915/intel_display.h      |  8 +++++
>  drivers/gpu/drm/i915/intel_drv.h          |  2 +-
>  drivers/gpu/drm/i915/intel_sprite.c       | 12 ++++---
>  5 files changed, 42 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index 010269a12390..69fc7010190c 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -210,7 +210,7 @@ void intel_update_planes_on_crtc(struct intel_atomic_state *old_state,
>  		} else {
>  			trace_intel_disable_plane(&plane->base, crtc);
>  
> -			plane->disable_plane(plane, crtc);
> +			plane->disable_plane(plane, new_crtc_state);
>  		}
>  	}
>  }
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 065c8befc6f8..0caba7258fee 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2767,7 +2767,7 @@ static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
>  		intel_pre_disable_primary_noatomic(&crtc->base);
>  
>  	trace_intel_disable_plane(&plane->base, crtc);
> -	plane->disable_plane(plane, crtc);
> +	plane->disable_plane(plane, crtc_state);
>  }
>  
>  static void
> @@ -3372,7 +3372,7 @@ static void i9xx_update_plane(struct intel_plane *plane,
>  }
>  
>  static void i9xx_disable_plane(struct intel_plane *plane,
> -			       struct intel_crtc *crtc)
> +			       const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> @@ -5405,23 +5405,32 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
>  		intel_update_watermarks(crtc);
>  }
>  
> -static void intel_crtc_disable_planes(struct intel_crtc *crtc, unsigned plane_mask)
> +static void intel_crtc_disable_planes(struct intel_atomic_state *state,
> +				      struct intel_crtc *crtc)
>  {
> -	struct drm_device *dev = crtc->base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	const struct intel_crtc_state *new_crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	unsigned int update_mask = new_crtc_state->update_planes;
> +	const struct intel_plane_state *old_plane_state;
>  	struct intel_plane *plane;
>  	unsigned fb_bits = 0;
> +	int i;
>  
>  	intel_crtc_dpms_overlay_disable(crtc);
>  
> -	for_each_intel_plane_on_crtc(dev, crtc, plane) {
> -		if (plane_mask & BIT(plane->id)) {
> -			plane->disable_plane(plane, crtc);
> +	for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
> +		if (crtc->pipe != plane->pipe ||
> +		    !(update_mask & BIT(plane->id)))
> +			continue;
>  
> +		plane->disable_plane(plane, new_crtc_state);
> +
> +		if (old_plane_state->base.visible)
>  			fb_bits |= plane->frontbuffer_bit;
> -		}
>  	}
>  
> -	intel_frontbuffer_flip(to_i915(dev), fb_bits);
> +	intel_frontbuffer_flip(dev_priv, fb_bits);
>  }
>  
>  static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
> @@ -9866,9 +9875,9 @@ static void i845_update_cursor(struct intel_plane *plane,
>  }
>  
>  static void i845_disable_cursor(struct intel_plane *plane,
> -				struct intel_crtc *crtc)
> +				const struct intel_crtc_state *crtc_state)
>  {
> -	i845_update_cursor(plane, NULL, NULL);
> +	i845_update_cursor(plane, crtc_state, NULL);
>  }
>  
>  static bool i845_cursor_get_hw_state(struct intel_plane *plane,
> @@ -10095,9 +10104,9 @@ static void i9xx_update_cursor(struct intel_plane *plane,
>  }
>  
>  static void i9xx_disable_cursor(struct intel_plane *plane,
> -				struct intel_crtc *crtc)
> +				const struct intel_crtc_state *crtc_state)
>  {
> -	i9xx_update_cursor(plane, NULL, NULL);
> +	i9xx_update_cursor(plane, crtc_state, NULL);
>  }
>  
>  static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
> @@ -12861,7 +12870,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
>  		intel_pre_plane_update(old_intel_crtc_state, new_intel_crtc_state);
>  
>  		if (old_crtc_state->active) {
> -			intel_crtc_disable_planes(intel_crtc, old_intel_crtc_state->active_planes);
> +			intel_crtc_disable_planes(intel_state, intel_crtc);
>  
>  			/*
>  			 * We need to disable pipe CRC before disabling the pipe,
> @@ -13711,7 +13720,7 @@ intel_legacy_cursor_update(struct drm_plane *plane,
>  					  to_intel_plane_state(plane->state));
>  	} else {
>  		trace_intel_disable_plane(plane, to_intel_crtc(crtc));
> -		intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
> +		intel_plane->disable_plane(intel_plane, crtc_state);
>  	}
>  
>  	intel_plane_unpin_fb(to_intel_plane_state(old_plane_state));
> diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
> index 5d50decbcbb5..df9e6ebb27de 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -382,6 +382,14 @@ struct intel_link_m_n {
>  	for_each_power_well_rev(__dev_priv, __power_well)		        \
>  		for_each_if((__power_well)->desc->domains & (__domain_mask))
>  
> +#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
> +	for ((__i) = 0; \
> +	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
> +		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
> +		      (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
> +	     (__i)++) \
> +		for_each_if(plane)
> +
>  #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
>  	for ((__i) = 0; \
>  	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index b0a24a81780a..23b33970db17 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1015,7 +1015,7 @@ struct intel_plane {
>  			     const struct intel_crtc_state *crtc_state,
>  			     const struct intel_plane_state *plane_state);
>  	void (*disable_plane)(struct intel_plane *plane,
> -			      struct intel_crtc *crtc);
> +			      const struct intel_crtc_state *crtc_state);
>  	bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
>  	int (*check_plane)(struct intel_crtc_state *crtc_state,
>  			   struct intel_plane_state *plane_state);
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 6403ef2219d0..74d904a49bf9 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -594,7 +594,8 @@ icl_update_slave(struct intel_plane *plane,
>  }
>  
>  static void
> -skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
> +skl_disable_plane(struct intel_plane *plane,
> +		  const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	enum plane_id plane_id = plane->id;
> @@ -857,7 +858,8 @@ vlv_update_plane(struct intel_plane *plane,
>  }
>  
>  static void
> -vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
> +vlv_disable_plane(struct intel_plane *plane,
> +		  const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	enum pipe pipe = plane->pipe;
> @@ -1024,7 +1026,8 @@ ivb_update_plane(struct intel_plane *plane,
>  }
>  
>  static void
> -ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
> +ivb_disable_plane(struct intel_plane *plane,
> +		  const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	enum pipe pipe = plane->pipe;
> @@ -1190,7 +1193,8 @@ g4x_update_plane(struct intel_plane *plane,
>  }
>  
>  static void
> -g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
> +g4x_disable_plane(struct intel_plane *plane,
> +		  const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	enum pipe pipe = plane->pipe;
> -- 
> 2.18.1
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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[PATCH v2 05/13] drm/i915: Fix latency==0 handling for level 0 watermark on skl+

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

If the level 0 latency is 0 we can't do anything. Return an error
rather than success.

While this can't happen due to WaWmMemoryReadLatency, it can
happen if the user clears out the level 0 latency via debugfs.

v2: Clarify how how we can end here with zero level 0 latency (Matt)

Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 27498ded4949..25f589c4f68c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4704,8 +4704,10 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 	bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
 	uint32_t min_disp_buf_needed;
 
-	if (latency == 0 ||
-	    !intel_wm_plane_visible(cstate, intel_pstate)) {
+	if (latency == 0)
+		return level == 0 ? -EINVAL : 0;
+
+	if (!intel_wm_plane_visible(cstate, intel_pstate)) {
 		result->plane_en = false;
 		return 0;
 	}
-- 
2.18.1

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Re: [PATCH v2 05/13] drm/i915: Fix latency==0 handling for level 0 watermark on skl+

[Matt Roper]

On Wed, Nov 14, 2018 at 11:07:21PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> If the level 0 latency is 0 we can't do anything. Return an error
> rather than success.
> 
> While this can't happen due to WaWmMemoryReadLatency, it can
> happen if the user clears out the level 0 latency via debugfs.
> 
> v2: Clarify how how we can end here with zero level 0 latency (Matt)
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

I wonder whether we should really be letting users shoot themselves in
the foot with debugfs here.  Maybe we should pull the sanitization and
hardware workarounds out of intel_read_wm_latency() and also apply it to
whatever debugfs gives us.

This is good enough for now though.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 27498ded4949..25f589c4f68c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4704,8 +4704,10 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>  	bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
>  	uint32_t min_disp_buf_needed;
>  
> -	if (latency == 0 ||
> -	    !intel_wm_plane_visible(cstate, intel_pstate)) {
> +	if (latency == 0)
> +		return level == 0 ? -EINVAL : 0;
> +
> +	if (!intel_wm_plane_visible(cstate, intel_pstate)) {
>  		result->plane_en = false;
>  		return 0;
>  	}
> -- 
> 2.18.1
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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Re: [PATCH v2 05/13] drm/i915: Fix latency==0 handling for level 0 watermark on skl+

[Ville Syrjälä]

On Mon, Nov 19, 2018 at 03:14:34PM -0800, Matt Roper wrote:
> On Wed, Nov 14, 2018 at 11:07:21PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > If the level 0 latency is 0 we can't do anything. Return an error
> > rather than success.
> > 
> > While this can't happen due to WaWmMemoryReadLatency, it can
> > happen if the user clears out the level 0 latency via debugfs.
> > 
> > v2: Clarify how how we can end here with zero level 0 latency (Matt)
> > 
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> I wonder whether we should really be letting users shoot themselves in
> the foot with debugfs here. Maybe we should pull the sanitization and
> hardware workarounds out of intel_read_wm_latency() and also apply it to
> whatever debugfs gives us.

I've considered that. But OTOH it's rather nice to be able to override
the workarounds and just test exactly what you want. And no normal
user should be poking around in debugfs anyway. It's only for debugging
and as such is generally understood to contain some amount of dragons.

> 
> This is good enough for now though.
> 
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> 
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
> >  1 file changed, 4 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 27498ded4949..25f589c4f68c 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4704,8 +4704,10 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> >  	bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
> >  	uint32_t min_disp_buf_needed;
> >  
> > -	if (latency == 0 ||
> > -	    !intel_wm_plane_visible(cstate, intel_pstate)) {
> > +	if (latency == 0)
> > +		return level == 0 ? -EINVAL : 0;
> > +
> > +	if (!intel_wm_plane_visible(cstate, intel_pstate)) {
> >  		result->plane_en = false;
> >  		return 0;
> >  	}
> > -- 
> > 2.18.1
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795

-- 
Ville Syrjälä
Intel
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[PATCH v2 06/13] drm/i915: Remove some useless zeroing on skl+ wm calculations

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We memset(0) the entire watermark struct the start, so there's no
need to clear things later on.

v2: Rebase due to some stale w/a removal

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 25f589c4f68c..eb3ce3ee4df3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4707,10 +4707,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 	if (latency == 0)
 		return level == 0 ? -EINVAL : 0;
 
-	if (!intel_wm_plane_visible(cstate, intel_pstate)) {
-		result->plane_en = false;
+	if (!intel_wm_plane_visible(cstate, intel_pstate))
 		return 0;
-	}
 
 	/* Display WA #1141: kbl,cfl */
 	if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
@@ -4807,8 +4805,6 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 	if ((level > 0 && res_lines > 31) ||
 	    res_blocks >= ddb_allocation ||
 	    min_disp_buf_needed >= ddb_allocation) {
-		result->plane_en = false;
-
 		/*
 		 * If there are no valid level 0 watermarks, then we can't
 		 * support this display configuration.
@@ -4910,15 +4906,15 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
 	uint16_t wm0_sel_res_b, trans_offset_b, res_blocks;
 
 	if (!cstate->base.active)
-		goto exit;
+		return;
 
 	/* Transition WM are not recommended by HW team for GEN9 */
 	if (INTEL_GEN(dev_priv) <= 9)
-		goto exit;
+		return;
 
 	/* Transition WM don't make any sense if ipc is disabled */
 	if (!dev_priv->ipc_enabled)
-		goto exit;
+		return;
 
 	trans_min = 14;
 	if (INTEL_GEN(dev_priv) >= 11)
@@ -4957,11 +4953,7 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
 	if (res_blocks < ddb_allocation) {
 		trans_wm->plane_res_b = res_blocks;
 		trans_wm->plane_en = true;
-		return;
 	}
-
-exit:
-	trans_wm->plane_en = false;
 }
 
 static int __skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
-- 
2.18.1

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Re: [PATCH v2 06/13] drm/i915: Remove some useless zeroing on skl+ wm calculations

[Matt Roper]

On Wed, Nov 14, 2018 at 11:07:22PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We memset(0) the entire watermark struct the start, so there's no
> need to clear things later on.
> 
> v2: Rebase due to some stale w/a removal
> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 16 ++++------------
>  1 file changed, 4 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 25f589c4f68c..eb3ce3ee4df3 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4707,10 +4707,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>  	if (latency == 0)
>  		return level == 0 ? -EINVAL : 0;
>  
> -	if (!intel_wm_plane_visible(cstate, intel_pstate)) {
> -		result->plane_en = false;
> +	if (!intel_wm_plane_visible(cstate, intel_pstate))
>  		return 0;
> -	}
>  
>  	/* Display WA #1141: kbl,cfl */
>  	if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
> @@ -4807,8 +4805,6 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>  	if ((level > 0 && res_lines > 31) ||
>  	    res_blocks >= ddb_allocation ||
>  	    min_disp_buf_needed >= ddb_allocation) {
> -		result->plane_en = false;
> -
>  		/*
>  		 * If there are no valid level 0 watermarks, then we can't
>  		 * support this display configuration.
> @@ -4910,15 +4906,15 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
>  	uint16_t wm0_sel_res_b, trans_offset_b, res_blocks;
>  
>  	if (!cstate->base.active)
> -		goto exit;
> +		return;
>  
>  	/* Transition WM are not recommended by HW team for GEN9 */
>  	if (INTEL_GEN(dev_priv) <= 9)
> -		goto exit;
> +		return;
>  
>  	/* Transition WM don't make any sense if ipc is disabled */
>  	if (!dev_priv->ipc_enabled)
> -		goto exit;
> +		return;
>  
>  	trans_min = 14;
>  	if (INTEL_GEN(dev_priv) >= 11)
> @@ -4957,11 +4953,7 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
>  	if (res_blocks < ddb_allocation) {
>  		trans_wm->plane_res_b = res_blocks;
>  		trans_wm->plane_en = true;
> -		return;
>  	}
> -
> -exit:
> -	trans_wm->plane_en = false;
>  }
>  
>  static int __skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
> -- 
> 2.18.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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[PATCH v2 07/13] drm/i915: Pass the entire skl_plane_wm to skl_compute_transition_wm()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We have to pass both level 0 watermark struct and the transition
watermark struct to skl_compute_transition_wm(). Make life less
confusing by just passing the entire plane watermark struct that
contains both aforementioned structures.

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index eb3ce3ee4df3..59c91ec11c60 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4894,10 +4894,9 @@ skl_compute_linetime_wm(const struct intel_crtc_state *cstate)
 }
 
 static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
-				      struct skl_wm_params *wp,
-				      struct skl_wm_level *wm_l0,
-				      uint16_t ddb_allocation,
-				      struct skl_wm_level *trans_wm /* out */)
+				      const struct skl_wm_params *wp,
+				      struct skl_plane_wm *wm,
+				      uint16_t ddb_allocation)
 {
 	struct drm_device *dev = cstate->base.crtc->dev;
 	const struct drm_i915_private *dev_priv = to_i915(dev);
@@ -4932,7 +4931,7 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
 	 * Result Blocks is Result Blocks minus 1 and it should work for the
 	 * current platforms.
 	 */
-	wm0_sel_res_b = wm_l0->plane_res_b - 1;
+	wm0_sel_res_b = wm->wm[0].plane_res_b - 1;
 
 	if (wp->y_tiled) {
 		trans_y_tile_min = (uint16_t) mul_round_up_u32_fixed16(2,
@@ -4951,8 +4950,8 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
 	res_blocks += 1;
 
 	if (res_blocks < ddb_allocation) {
-		trans_wm->plane_res_b = res_blocks;
-		trans_wm->plane_en = true;
+		wm->trans_wm.plane_res_b = res_blocks;
+		wm->trans_wm.plane_en = true;
 	}
 }
 
@@ -4981,8 +4980,7 @@ static int __skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
 	if (ret)
 		return ret;
 
-	skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0],
-				  ddb_blocks, &wm->trans_wm);
+	skl_compute_transition_wm(cstate, &wm_params, wm, ddb_blocks);
 
 	return 0;
 }
-- 
2.18.1

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Re: [PATCH v2 07/13] drm/i915: Pass the entire skl_plane_wm to skl_compute_transition_wm()

[Matt Roper]

On Wed, Nov 14, 2018 at 11:07:23PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We have to pass both level 0 watermark struct and the transition
> watermark struct to skl_compute_transition_wm(). Make life less
> confusing by just passing the entire plane watermark struct that
> contains both aforementioned structures.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 16 +++++++---------
>  1 file changed, 7 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index eb3ce3ee4df3..59c91ec11c60 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4894,10 +4894,9 @@ skl_compute_linetime_wm(const struct intel_crtc_state *cstate)
>  }
>  
>  static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
> -				      struct skl_wm_params *wp,
> -				      struct skl_wm_level *wm_l0,
> -				      uint16_t ddb_allocation,
> -				      struct skl_wm_level *trans_wm /* out */)
> +				      const struct skl_wm_params *wp,
> +				      struct skl_plane_wm *wm,
> +				      uint16_t ddb_allocation)
>  {
>  	struct drm_device *dev = cstate->base.crtc->dev;
>  	const struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -4932,7 +4931,7 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
>  	 * Result Blocks is Result Blocks minus 1 and it should work for the
>  	 * current platforms.
>  	 */
> -	wm0_sel_res_b = wm_l0->plane_res_b - 1;
> +	wm0_sel_res_b = wm->wm[0].plane_res_b - 1;
>  
>  	if (wp->y_tiled) {
>  		trans_y_tile_min = (uint16_t) mul_round_up_u32_fixed16(2,
> @@ -4951,8 +4950,8 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
>  	res_blocks += 1;
>  
>  	if (res_blocks < ddb_allocation) {
> -		trans_wm->plane_res_b = res_blocks;
> -		trans_wm->plane_en = true;
> +		wm->trans_wm.plane_res_b = res_blocks;
> +		wm->trans_wm.plane_en = true;
>  	}
>  }
>  
> @@ -4981,8 +4980,7 @@ static int __skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
>  	if (ret)
>  		return ret;
>  
> -	skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0],
> -				  ddb_blocks, &wm->trans_wm);
> +	skl_compute_transition_wm(cstate, &wm_params, wm, ddb_blocks);
>  
>  	return 0;
>  }
> -- 
> 2.18.1
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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[PATCH v2 08/13] drm/i915: Clean up skl+ vs. icl+ watermark computation

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Make a cleaner split between the skl+ and icl+ ways of computing
watermarks. This way skl_build_pipe_wm() doesn't have to know any
of the gritty details of icl+ master/slave planes.

We can also simplify a bunch of the lower level code by pulling
the plane visibility checks a bit higher up.

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 192 +++++++++++++++++---------------
 1 file changed, 103 insertions(+), 89 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 59c91ec11c60..a743e089ab7d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4591,9 +4591,6 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
 		to_intel_atomic_state(cstate->base.state);
 	bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
 
-	if (!intel_wm_plane_visible(cstate, intel_pstate))
-		return 0;
-
 	/* only NV12 format has two planes */
 	if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
 		DRM_DEBUG_KMS("Non NV12 format have single plane\n");
@@ -4707,9 +4704,6 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 	if (latency == 0)
 		return level == 0 ? -EINVAL : 0;
 
-	if (!intel_wm_plane_visible(cstate, intel_pstate))
-		return 0;
-
 	/* Display WA #1141: kbl,cfl */
 	if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
 	    IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) &&
@@ -4832,21 +4826,16 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 
 static int
 skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
-		      struct skl_ddb_allocation *ddb,
 		      const struct intel_crtc_state *cstate,
 		      const struct intel_plane_state *intel_pstate,
 		      uint16_t ddb_blocks,
 		      const struct skl_wm_params *wm_params,
-		      struct skl_plane_wm *wm,
 		      struct skl_wm_level *levels)
 {
 	int level, max_level = ilk_wm_max_level(dev_priv);
 	struct skl_wm_level *result_prev = &levels[0];
 	int ret;
 
-	if (WARN_ON(!intel_pstate->base.fb))
-		return -EINVAL;
-
 	for (level = 0; level <= max_level; level++) {
 		struct skl_wm_level *result = &levels[level];
 
@@ -4864,9 +4853,6 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
 		result_prev = result;
 	}
 
-	if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
-		wm->is_planar = true;
-
 	return 0;
 }
 
@@ -4904,9 +4890,6 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
 	const uint16_t trans_amount = 10; /* This is configurable amount */
 	uint16_t wm0_sel_res_b, trans_offset_b, res_blocks;
 
-	if (!cstate->base.active)
-		return;
-
 	/* Transition WM are not recommended by HW team for GEN9 */
 	if (INTEL_GEN(dev_priv) <= 9)
 		return;
@@ -4955,97 +4938,134 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
 	}
 }
 
-static int __skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
-				       struct skl_pipe_wm *pipe_wm,
-				       enum plane_id plane_id,
-				       const struct intel_crtc_state *cstate,
-				       const struct intel_plane_state *pstate,
-				       int color_plane)
-{
-	struct drm_i915_private *dev_priv = to_i915(pstate->base.plane->dev);
-	struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
-	enum pipe pipe = to_intel_plane(pstate->base.plane)->pipe;
-	struct skl_wm_params wm_params;
-	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
-	int ret;
-
-	ret = skl_compute_plane_wm_params(dev_priv, cstate, pstate,
-					  &wm_params, color_plane);
-	if (ret)
-		return ret;
-
-	ret = skl_compute_wm_levels(dev_priv, ddb, cstate, pstate,
-				    ddb_blocks, &wm_params, wm, wm->wm);
-
-	if (ret)
-		return ret;
-
-	skl_compute_transition_wm(cstate, &wm_params, wm, ddb_blocks);
-
-	return 0;
-}
-
 static int skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
-				     struct skl_pipe_wm *pipe_wm,
-				     const struct intel_crtc_state *cstate,
-				     const struct intel_plane_state *pstate)
+				     struct intel_crtc_state *crtc_state,
+				     const struct intel_plane_state *plane_state,
+				     enum plane_id plane_id, int color_plane)
 {
-	enum plane_id plane_id = to_intel_plane(pstate->base.plane)->id;
-
-	return __skl_build_plane_wm_single(ddb, pipe_wm, plane_id, cstate, pstate, 0);
-}
-
-static int skl_build_plane_wm_planar(struct skl_ddb_allocation *ddb,
-				     struct skl_pipe_wm *pipe_wm,
-				     const struct intel_crtc_state *cstate,
-				     const struct intel_plane_state *pstate)
-{
-	struct intel_plane *plane = to_intel_plane(pstate->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-	enum plane_id plane_id = plane->id;
-	struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
+	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
 	struct skl_wm_params wm_params;
 	enum pipe pipe = plane->pipe;
 	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
 	int ret;
 
-	ret = __skl_build_plane_wm_single(ddb, pipe_wm, plane_id, cstate, pstate, 0);
+	ret = skl_compute_plane_wm_params(dev_priv, crtc_state, plane_state,
+					  &wm_params, color_plane);
 	if (ret)
 		return ret;
 
+	ret = skl_compute_wm_levels(dev_priv, crtc_state, plane_state,
+				    ddb_blocks, &wm_params, wm->wm);
+	if (ret)
+		return ret;
+
+	skl_compute_transition_wm(crtc_state, &wm_params, wm, ddb_blocks);
+
+	return 0;
+}
+
+static int skl_build_plane_wm_uv(struct skl_ddb_allocation *ddb,
+				 struct intel_crtc_state *crtc_state,
+				 const struct intel_plane_state *plane_state,
+				 enum plane_id plane_id)
+{
+	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
+	struct skl_wm_params wm_params;
+	enum pipe pipe = plane->pipe;
+	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->uv_plane[pipe][plane_id]);
+	int ret;
+
+	wm->is_planar = true;
+
 	/* uv plane watermarks must also be validated for NV12/Planar */
-	ddb_blocks = skl_ddb_entry_size(&ddb->uv_plane[pipe][plane_id]);
+	ret = skl_compute_plane_wm_params(dev_priv, crtc_state, plane_state,
+					  &wm_params, 1);
+	if (ret)
+		return ret;
 
-	ret = skl_compute_plane_wm_params(dev_priv, cstate, pstate, &wm_params, 1);
+	ret = skl_compute_wm_levels(dev_priv, crtc_state, plane_state,
+				    ddb_blocks, &wm_params, wm->uv_wm);
 	if (ret)
 		return ret;
 
-	return skl_compute_wm_levels(dev_priv, ddb, cstate, pstate,
-				     ddb_blocks, &wm_params, wm, wm->uv_wm);
+	return 0;
 }
 
-static int icl_build_plane_wm_planar(struct skl_ddb_allocation *ddb,
-				     struct skl_pipe_wm *pipe_wm,
-				     const struct intel_crtc_state *cstate,
-				     const struct intel_plane_state *pstate)
+static int skl_build_plane_wm(struct skl_ddb_allocation *ddb,
+			      struct skl_pipe_wm *pipe_wm,
+			      struct intel_crtc_state *crtc_state,
+			      const struct intel_plane_state *plane_state)
 {
+	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	const struct drm_framebuffer *fb = plane_state->base.fb;
+	enum plane_id plane_id = plane->id;
 	int ret;
-	enum plane_id y_plane_id = pstate->linked_plane->id;
-	enum plane_id uv_plane_id = to_intel_plane(pstate->base.plane)->id;
 
-	ret = __skl_build_plane_wm_single(ddb, pipe_wm, y_plane_id,
-					  cstate, pstate, 0);
+	if (!intel_wm_plane_visible(crtc_state, plane_state))
+		return 0;
+
+	ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
+					plane_id, 0);
 	if (ret)
 		return ret;
 
-	return __skl_build_plane_wm_single(ddb, pipe_wm, uv_plane_id,
-					   cstate, pstate, 1);
+	if (fb->format->is_yuv && fb->format->num_planes > 1) {
+		ret = skl_build_plane_wm_uv(ddb, crtc_state, plane_state,
+					    plane_id);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int icl_build_plane_wm(struct skl_ddb_allocation *ddb,
+			      struct skl_pipe_wm *pipe_wm,
+			      struct intel_crtc_state *crtc_state,
+			      const struct intel_plane_state *plane_state)
+{
+	enum plane_id plane_id = to_intel_plane(plane_state->base.plane)->id;
+	int ret;
+
+	/* Watermarks calculated in master */
+	if (plane_state->slave)
+		return 0;
+
+	if (plane_state->linked_plane) {
+		const struct drm_framebuffer *fb = plane_state->base.fb;
+		enum plane_id y_plane_id = plane_state->linked_plane->id;
+
+		WARN_ON(!fb->format->is_yuv ||
+			fb->format->num_planes == 1);
+
+		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
+						y_plane_id, 0);
+		if (ret)
+			return ret;
+
+		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
+						plane_id, 1);
+		if (ret)
+			return ret;
+	} else if (intel_wm_plane_visible(crtc_state, plane_state)) {
+		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
+						plane_id, 0);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
 }
 
 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
 			     struct skl_ddb_allocation *ddb,
 			     struct skl_pipe_wm *pipe_wm)
 {
+	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
 	struct drm_crtc_state *crtc_state = &cstate->base;
 	struct drm_plane *plane;
 	const struct drm_plane_state *pstate;
@@ -5061,18 +5081,12 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
 		const struct intel_plane_state *intel_pstate =
 						to_intel_plane_state(pstate);
 
-		/* Watermarks calculated in master */
-		if (intel_pstate->slave)
-			continue;
-
-		if (intel_pstate->linked_plane)
-			ret = icl_build_plane_wm_planar(ddb, pipe_wm, cstate, intel_pstate);
-		else if (intel_pstate->base.fb &&
-			 intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
-			ret = skl_build_plane_wm_planar(ddb, pipe_wm, cstate, intel_pstate);
+		if (INTEL_GEN(dev_priv) >= 11)
+			ret = icl_build_plane_wm(ddb, pipe_wm,
+						 cstate, intel_pstate);
 		else
-			ret = skl_build_plane_wm_single(ddb, pipe_wm, cstate, intel_pstate);
-
+			ret = skl_build_plane_wm(ddb, pipe_wm,
+						 cstate, intel_pstate);
 		if (ret)
 			return ret;
 	}
-- 
2.18.1

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Re: [PATCH v2 08/13] drm/i915: Clean up skl+ vs. icl+ watermark computation

[Matt Roper]

On Wed, Nov 14, 2018 at 11:07:24PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Make a cleaner split between the skl+ and icl+ ways of computing
> watermarks. This way skl_build_pipe_wm() doesn't have to know any
> of the gritty details of icl+ master/slave planes.
> 
> We can also simplify a bunch of the lower level code by pulling
> the plane visibility checks a bit higher up.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 192 +++++++++++++++++---------------
>  1 file changed, 103 insertions(+), 89 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 59c91ec11c60..a743e089ab7d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4591,9 +4591,6 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
>  		to_intel_atomic_state(cstate->base.state);
>  	bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
>  
> -	if (!intel_wm_plane_visible(cstate, intel_pstate))
> -		return 0;
> -
>  	/* only NV12 format has two planes */
>  	if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
>  		DRM_DEBUG_KMS("Non NV12 format have single plane\n");
> @@ -4707,9 +4704,6 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>  	if (latency == 0)
>  		return level == 0 ? -EINVAL : 0;
>  
> -	if (!intel_wm_plane_visible(cstate, intel_pstate))
> -		return 0;
> -
>  	/* Display WA #1141: kbl,cfl */
>  	if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
>  	    IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) &&
> @@ -4832,21 +4826,16 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>  
>  static int
>  skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
> -		      struct skl_ddb_allocation *ddb,
>  		      const struct intel_crtc_state *cstate,
>  		      const struct intel_plane_state *intel_pstate,
>  		      uint16_t ddb_blocks,
>  		      const struct skl_wm_params *wm_params,
> -		      struct skl_plane_wm *wm,
>  		      struct skl_wm_level *levels)
>  {
>  	int level, max_level = ilk_wm_max_level(dev_priv);
>  	struct skl_wm_level *result_prev = &levels[0];
>  	int ret;
>  
> -	if (WARN_ON(!intel_pstate->base.fb))
> -		return -EINVAL;
> -
>  	for (level = 0; level <= max_level; level++) {
>  		struct skl_wm_level *result = &levels[level];
>  
> @@ -4864,9 +4853,6 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
>  		result_prev = result;
>  	}
>  
> -	if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
> -		wm->is_planar = true;
> -
>  	return 0;
>  }
>  
> @@ -4904,9 +4890,6 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
>  	const uint16_t trans_amount = 10; /* This is configurable amount */
>  	uint16_t wm0_sel_res_b, trans_offset_b, res_blocks;
>  
> -	if (!cstate->base.active)
> -		return;
> -
>  	/* Transition WM are not recommended by HW team for GEN9 */
>  	if (INTEL_GEN(dev_priv) <= 9)
>  		return;
> @@ -4955,97 +4938,134 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
>  	}
>  }
>  
> -static int __skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
> -				       struct skl_pipe_wm *pipe_wm,
> -				       enum plane_id plane_id,
> -				       const struct intel_crtc_state *cstate,
> -				       const struct intel_plane_state *pstate,
> -				       int color_plane)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(pstate->base.plane->dev);
> -	struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> -	enum pipe pipe = to_intel_plane(pstate->base.plane)->pipe;
> -	struct skl_wm_params wm_params;
> -	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
> -	int ret;
> -
> -	ret = skl_compute_plane_wm_params(dev_priv, cstate, pstate,
> -					  &wm_params, color_plane);
> -	if (ret)
> -		return ret;
> -
> -	ret = skl_compute_wm_levels(dev_priv, ddb, cstate, pstate,
> -				    ddb_blocks, &wm_params, wm, wm->wm);
> -
> -	if (ret)
> -		return ret;
> -
> -	skl_compute_transition_wm(cstate, &wm_params, wm, ddb_blocks);
> -
> -	return 0;
> -}
> -
>  static int skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
> -				     struct skl_pipe_wm *pipe_wm,
> -				     const struct intel_crtc_state *cstate,
> -				     const struct intel_plane_state *pstate)
> +				     struct intel_crtc_state *crtc_state,
> +				     const struct intel_plane_state *plane_state,
> +				     enum plane_id plane_id, int color_plane)
>  {
> -	enum plane_id plane_id = to_intel_plane(pstate->base.plane)->id;
> -
> -	return __skl_build_plane_wm_single(ddb, pipe_wm, plane_id, cstate, pstate, 0);
> -}
> -
> -static int skl_build_plane_wm_planar(struct skl_ddb_allocation *ddb,
> -				     struct skl_pipe_wm *pipe_wm,
> -				     const struct intel_crtc_state *cstate,
> -				     const struct intel_plane_state *pstate)
> -{
> -	struct intel_plane *plane = to_intel_plane(pstate->base.plane);
> +	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> -	enum plane_id plane_id = plane->id;
> -	struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> +	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
>  	struct skl_wm_params wm_params;
>  	enum pipe pipe = plane->pipe;
>  	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
>  	int ret;
>  
> -	ret = __skl_build_plane_wm_single(ddb, pipe_wm, plane_id, cstate, pstate, 0);
> +	ret = skl_compute_plane_wm_params(dev_priv, crtc_state, plane_state,
> +					  &wm_params, color_plane);
>  	if (ret)
>  		return ret;
>  
> +	ret = skl_compute_wm_levels(dev_priv, crtc_state, plane_state,
> +				    ddb_blocks, &wm_params, wm->wm);
> +	if (ret)
> +		return ret;
> +
> +	skl_compute_transition_wm(crtc_state, &wm_params, wm, ddb_blocks);
> +
> +	return 0;
> +}
> +
> +static int skl_build_plane_wm_uv(struct skl_ddb_allocation *ddb,
> +				 struct intel_crtc_state *crtc_state,
> +				 const struct intel_plane_state *plane_state,
> +				 enum plane_id plane_id)
> +{
> +	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
> +	struct skl_wm_params wm_params;
> +	enum pipe pipe = plane->pipe;
> +	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->uv_plane[pipe][plane_id]);
> +	int ret;
> +
> +	wm->is_planar = true;
> +
>  	/* uv plane watermarks must also be validated for NV12/Planar */
> -	ddb_blocks = skl_ddb_entry_size(&ddb->uv_plane[pipe][plane_id]);
> +	ret = skl_compute_plane_wm_params(dev_priv, crtc_state, plane_state,
> +					  &wm_params, 1);
> +	if (ret)
> +		return ret;
>  
> -	ret = skl_compute_plane_wm_params(dev_priv, cstate, pstate, &wm_params, 1);
> +	ret = skl_compute_wm_levels(dev_priv, crtc_state, plane_state,
> +				    ddb_blocks, &wm_params, wm->uv_wm);
>  	if (ret)
>  		return ret;
>  
> -	return skl_compute_wm_levels(dev_priv, ddb, cstate, pstate,
> -				     ddb_blocks, &wm_params, wm, wm->uv_wm);
> +	return 0;
>  }
>  
> -static int icl_build_plane_wm_planar(struct skl_ddb_allocation *ddb,
> -				     struct skl_pipe_wm *pipe_wm,
> -				     const struct intel_crtc_state *cstate,
> -				     const struct intel_plane_state *pstate)
> +static int skl_build_plane_wm(struct skl_ddb_allocation *ddb,
> +			      struct skl_pipe_wm *pipe_wm,
> +			      struct intel_crtc_state *crtc_state,
> +			      const struct intel_plane_state *plane_state)
>  {
> +	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> +	const struct drm_framebuffer *fb = plane_state->base.fb;
> +	enum plane_id plane_id = plane->id;
>  	int ret;
> -	enum plane_id y_plane_id = pstate->linked_plane->id;
> -	enum plane_id uv_plane_id = to_intel_plane(pstate->base.plane)->id;
>  
> -	ret = __skl_build_plane_wm_single(ddb, pipe_wm, y_plane_id,
> -					  cstate, pstate, 0);
> +	if (!intel_wm_plane_visible(crtc_state, plane_state))
> +		return 0;
> +
> +	ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
> +					plane_id, 0);
>  	if (ret)
>  		return ret;
>  
> -	return __skl_build_plane_wm_single(ddb, pipe_wm, uv_plane_id,
> -					   cstate, pstate, 1);
> +	if (fb->format->is_yuv && fb->format->num_planes > 1) {
> +		ret = skl_build_plane_wm_uv(ddb, crtc_state, plane_state,
> +					    plane_id);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int icl_build_plane_wm(struct skl_ddb_allocation *ddb,
> +			      struct skl_pipe_wm *pipe_wm,
> +			      struct intel_crtc_state *crtc_state,
> +			      const struct intel_plane_state *plane_state)
> +{
> +	enum plane_id plane_id = to_intel_plane(plane_state->base.plane)->id;
> +	int ret;
> +
> +	/* Watermarks calculated in master */
> +	if (plane_state->slave)
> +		return 0;
> +
> +	if (plane_state->linked_plane) {
> +		const struct drm_framebuffer *fb = plane_state->base.fb;
> +		enum plane_id y_plane_id = plane_state->linked_plane->id;
> +
> +		WARN_ON(!fb->format->is_yuv ||
> +			fb->format->num_planes == 1);
> +
> +		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
> +						y_plane_id, 0);
> +		if (ret)
> +			return ret;
> +
> +		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
> +						plane_id, 1);
> +		if (ret)
> +			return ret;
> +	} else if (intel_wm_plane_visible(crtc_state, plane_state)) {

Isn't a visibility test also relevant to the nv12 (master plane) case
above?  I don't understand why we'd only test it for rgb planes.


Matt

> +		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
> +						plane_id, 0);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	return 0;
>  }
>  
>  static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
>  			     struct skl_ddb_allocation *ddb,
>  			     struct skl_pipe_wm *pipe_wm)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
>  	struct drm_crtc_state *crtc_state = &cstate->base;
>  	struct drm_plane *plane;
>  	const struct drm_plane_state *pstate;
> @@ -5061,18 +5081,12 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
>  		const struct intel_plane_state *intel_pstate =
>  						to_intel_plane_state(pstate);
>  
> -		/* Watermarks calculated in master */
> -		if (intel_pstate->slave)
> -			continue;
> -
> -		if (intel_pstate->linked_plane)
> -			ret = icl_build_plane_wm_planar(ddb, pipe_wm, cstate, intel_pstate);
> -		else if (intel_pstate->base.fb &&
> -			 intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
> -			ret = skl_build_plane_wm_planar(ddb, pipe_wm, cstate, intel_pstate);
> +		if (INTEL_GEN(dev_priv) >= 11)
> +			ret = icl_build_plane_wm(ddb, pipe_wm,
> +						 cstate, intel_pstate);
>  		else
> -			ret = skl_build_plane_wm_single(ddb, pipe_wm, cstate, intel_pstate);
> -
> +			ret = skl_build_plane_wm(ddb, pipe_wm,
> +						 cstate, intel_pstate);
>  		if (ret)
>  			return ret;
>  	}
> -- 
> 2.18.1
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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Re: [PATCH v2 08/13] drm/i915: Clean up skl+ vs. icl+ watermark computation

[Ville Syrjälä]

On Tue, Nov 20, 2018 at 02:44:34PM -0800, Matt Roper wrote:
> On Wed, Nov 14, 2018 at 11:07:24PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Make a cleaner split between the skl+ and icl+ ways of computing
> > watermarks. This way skl_build_pipe_wm() doesn't have to know any
> > of the gritty details of icl+ master/slave planes.
> > 
> > We can also simplify a bunch of the lower level code by pulling
> > the plane visibility checks a bit higher up.
> > 
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 192 +++++++++++++++++---------------
> >  1 file changed, 103 insertions(+), 89 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 59c91ec11c60..a743e089ab7d 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4591,9 +4591,6 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
> >  		to_intel_atomic_state(cstate->base.state);
> >  	bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
> >  
> > -	if (!intel_wm_plane_visible(cstate, intel_pstate))
> > -		return 0;
> > -
> >  	/* only NV12 format has two planes */
> >  	if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
> >  		DRM_DEBUG_KMS("Non NV12 format have single plane\n");
> > @@ -4707,9 +4704,6 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> >  	if (latency == 0)
> >  		return level == 0 ? -EINVAL : 0;
> >  
> > -	if (!intel_wm_plane_visible(cstate, intel_pstate))
> > -		return 0;
> > -
> >  	/* Display WA #1141: kbl,cfl */
> >  	if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
> >  	    IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) &&
> > @@ -4832,21 +4826,16 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> >  
> >  static int
> >  skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
> > -		      struct skl_ddb_allocation *ddb,
> >  		      const struct intel_crtc_state *cstate,
> >  		      const struct intel_plane_state *intel_pstate,
> >  		      uint16_t ddb_blocks,
> >  		      const struct skl_wm_params *wm_params,
> > -		      struct skl_plane_wm *wm,
> >  		      struct skl_wm_level *levels)
> >  {
> >  	int level, max_level = ilk_wm_max_level(dev_priv);
> >  	struct skl_wm_level *result_prev = &levels[0];
> >  	int ret;
> >  
> > -	if (WARN_ON(!intel_pstate->base.fb))
> > -		return -EINVAL;
> > -
> >  	for (level = 0; level <= max_level; level++) {
> >  		struct skl_wm_level *result = &levels[level];
> >  
> > @@ -4864,9 +4853,6 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
> >  		result_prev = result;
> >  	}
> >  
> > -	if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
> > -		wm->is_planar = true;
> > -
> >  	return 0;
> >  }
> >  
> > @@ -4904,9 +4890,6 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
> >  	const uint16_t trans_amount = 10; /* This is configurable amount */
> >  	uint16_t wm0_sel_res_b, trans_offset_b, res_blocks;
> >  
> > -	if (!cstate->base.active)
> > -		return;
> > -
> >  	/* Transition WM are not recommended by HW team for GEN9 */
> >  	if (INTEL_GEN(dev_priv) <= 9)
> >  		return;
> > @@ -4955,97 +4938,134 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
> >  	}
> >  }
> >  
> > -static int __skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
> > -				       struct skl_pipe_wm *pipe_wm,
> > -				       enum plane_id plane_id,
> > -				       const struct intel_crtc_state *cstate,
> > -				       const struct intel_plane_state *pstate,
> > -				       int color_plane)
> > -{
> > -	struct drm_i915_private *dev_priv = to_i915(pstate->base.plane->dev);
> > -	struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> > -	enum pipe pipe = to_intel_plane(pstate->base.plane)->pipe;
> > -	struct skl_wm_params wm_params;
> > -	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
> > -	int ret;
> > -
> > -	ret = skl_compute_plane_wm_params(dev_priv, cstate, pstate,
> > -					  &wm_params, color_plane);
> > -	if (ret)
> > -		return ret;
> > -
> > -	ret = skl_compute_wm_levels(dev_priv, ddb, cstate, pstate,
> > -				    ddb_blocks, &wm_params, wm, wm->wm);
> > -
> > -	if (ret)
> > -		return ret;
> > -
> > -	skl_compute_transition_wm(cstate, &wm_params, wm, ddb_blocks);
> > -
> > -	return 0;
> > -}
> > -
> >  static int skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
> > -				     struct skl_pipe_wm *pipe_wm,
> > -				     const struct intel_crtc_state *cstate,
> > -				     const struct intel_plane_state *pstate)
> > +				     struct intel_crtc_state *crtc_state,
> > +				     const struct intel_plane_state *plane_state,
> > +				     enum plane_id plane_id, int color_plane)
> >  {
> > -	enum plane_id plane_id = to_intel_plane(pstate->base.plane)->id;
> > -
> > -	return __skl_build_plane_wm_single(ddb, pipe_wm, plane_id, cstate, pstate, 0);
> > -}
> > -
> > -static int skl_build_plane_wm_planar(struct skl_ddb_allocation *ddb,
> > -				     struct skl_pipe_wm *pipe_wm,
> > -				     const struct intel_crtc_state *cstate,
> > -				     const struct intel_plane_state *pstate)
> > -{
> > -	struct intel_plane *plane = to_intel_plane(pstate->base.plane);
> > +	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > -	enum plane_id plane_id = plane->id;
> > -	struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> > +	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
> >  	struct skl_wm_params wm_params;
> >  	enum pipe pipe = plane->pipe;
> >  	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
> >  	int ret;
> >  
> > -	ret = __skl_build_plane_wm_single(ddb, pipe_wm, plane_id, cstate, pstate, 0);
> > +	ret = skl_compute_plane_wm_params(dev_priv, crtc_state, plane_state,
> > +					  &wm_params, color_plane);
> >  	if (ret)
> >  		return ret;
> >  
> > +	ret = skl_compute_wm_levels(dev_priv, crtc_state, plane_state,
> > +				    ddb_blocks, &wm_params, wm->wm);
> > +	if (ret)
> > +		return ret;
> > +
> > +	skl_compute_transition_wm(crtc_state, &wm_params, wm, ddb_blocks);
> > +
> > +	return 0;
> > +}
> > +
> > +static int skl_build_plane_wm_uv(struct skl_ddb_allocation *ddb,
> > +				 struct intel_crtc_state *crtc_state,
> > +				 const struct intel_plane_state *plane_state,
> > +				 enum plane_id plane_id)
> > +{
> > +	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> > +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > +	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
> > +	struct skl_wm_params wm_params;
> > +	enum pipe pipe = plane->pipe;
> > +	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->uv_plane[pipe][plane_id]);
> > +	int ret;
> > +
> > +	wm->is_planar = true;
> > +
> >  	/* uv plane watermarks must also be validated for NV12/Planar */
> > -	ddb_blocks = skl_ddb_entry_size(&ddb->uv_plane[pipe][plane_id]);
> > +	ret = skl_compute_plane_wm_params(dev_priv, crtc_state, plane_state,
> > +					  &wm_params, 1);
> > +	if (ret)
> > +		return ret;
> >  
> > -	ret = skl_compute_plane_wm_params(dev_priv, cstate, pstate, &wm_params, 1);
> > +	ret = skl_compute_wm_levels(dev_priv, crtc_state, plane_state,
> > +				    ddb_blocks, &wm_params, wm->uv_wm);
> >  	if (ret)
> >  		return ret;
> >  
> > -	return skl_compute_wm_levels(dev_priv, ddb, cstate, pstate,
> > -				     ddb_blocks, &wm_params, wm, wm->uv_wm);
> > +	return 0;
> >  }
> >  
> > -static int icl_build_plane_wm_planar(struct skl_ddb_allocation *ddb,
> > -				     struct skl_pipe_wm *pipe_wm,
> > -				     const struct intel_crtc_state *cstate,
> > -				     const struct intel_plane_state *pstate)
> > +static int skl_build_plane_wm(struct skl_ddb_allocation *ddb,
> > +			      struct skl_pipe_wm *pipe_wm,
> > +			      struct intel_crtc_state *crtc_state,
> > +			      const struct intel_plane_state *plane_state)
> >  {
> > +	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> > +	const struct drm_framebuffer *fb = plane_state->base.fb;
> > +	enum plane_id plane_id = plane->id;
> >  	int ret;
> > -	enum plane_id y_plane_id = pstate->linked_plane->id;
> > -	enum plane_id uv_plane_id = to_intel_plane(pstate->base.plane)->id;
> >  
> > -	ret = __skl_build_plane_wm_single(ddb, pipe_wm, y_plane_id,
> > -					  cstate, pstate, 0);
> > +	if (!intel_wm_plane_visible(crtc_state, plane_state))
> > +		return 0;
> > +
> > +	ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
> > +					plane_id, 0);
> >  	if (ret)
> >  		return ret;
> >  
> > -	return __skl_build_plane_wm_single(ddb, pipe_wm, uv_plane_id,
> > -					   cstate, pstate, 1);
> > +	if (fb->format->is_yuv && fb->format->num_planes > 1) {
> > +		ret = skl_build_plane_wm_uv(ddb, crtc_state, plane_state,
> > +					    plane_id);
> > +		if (ret)
> > +			return ret;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +static int icl_build_plane_wm(struct skl_ddb_allocation *ddb,
> > +			      struct skl_pipe_wm *pipe_wm,
> > +			      struct intel_crtc_state *crtc_state,
> > +			      const struct intel_plane_state *plane_state)
> > +{
> > +	enum plane_id plane_id = to_intel_plane(plane_state->base.plane)->id;
> > +	int ret;
> > +
> > +	/* Watermarks calculated in master */
> > +	if (plane_state->slave)
> > +		return 0;
> > +
> > +	if (plane_state->linked_plane) {
> > +		const struct drm_framebuffer *fb = plane_state->base.fb;
> > +		enum plane_id y_plane_id = plane_state->linked_plane->id;
> > +
> > +		WARN_ON(!fb->format->is_yuv ||
> > +			fb->format->num_planes == 1);
> > +
> > +		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
> > +						y_plane_id, 0);
> > +		if (ret)
> > +			return ret;
> > +
> > +		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
> > +						plane_id, 1);
> > +		if (ret)
> > +			return ret;
> > +	} else if (intel_wm_plane_visible(crtc_state, plane_state)) {
> 
> Isn't a visibility test also relevant to the nv12 (master plane) case
> above?  I don't understand why we'd only test it for rgb planes.

linked_plane!=NULL implies that the plane is visible (see 
icl_check_nv12_planes()). I should probably add another WARN_ON() for
that.

> 
> 
> Matt
> 
> > +		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
> > +						plane_id, 0);
> > +		if (ret)
> > +			return ret;
> > +	}
> > +
> > +	return 0;
> >  }
> >  
> >  static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
> >  			     struct skl_ddb_allocation *ddb,
> >  			     struct skl_pipe_wm *pipe_wm)
> >  {
> > +	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
> >  	struct drm_crtc_state *crtc_state = &cstate->base;
> >  	struct drm_plane *plane;
> >  	const struct drm_plane_state *pstate;
> > @@ -5061,18 +5081,12 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
> >  		const struct intel_plane_state *intel_pstate =
> >  						to_intel_plane_state(pstate);
> >  
> > -		/* Watermarks calculated in master */
> > -		if (intel_pstate->slave)
> > -			continue;
> > -
> > -		if (intel_pstate->linked_plane)
> > -			ret = icl_build_plane_wm_planar(ddb, pipe_wm, cstate, intel_pstate);
> > -		else if (intel_pstate->base.fb &&
> > -			 intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
> > -			ret = skl_build_plane_wm_planar(ddb, pipe_wm, cstate, intel_pstate);
> > +		if (INTEL_GEN(dev_priv) >= 11)
> > +			ret = icl_build_plane_wm(ddb, pipe_wm,
> > +						 cstate, intel_pstate);
> >  		else
> > -			ret = skl_build_plane_wm_single(ddb, pipe_wm, cstate, intel_pstate);
> > -
> > +			ret = skl_build_plane_wm(ddb, pipe_wm,
> > +						 cstate, intel_pstate);
> >  		if (ret)
> >  			return ret;
> >  	}
> > -- 
> > 2.18.1
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 08/13] drm/i915: Clean up skl+ vs. icl+ watermark computation

[Matt Roper]

On Wed, Nov 21, 2018 at 09:05:33PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 20, 2018 at 02:44:34PM -0800, Matt Roper wrote:
> > On Wed, Nov 14, 2018 at 11:07:24PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
...snip...
> > > +static int icl_build_plane_wm(struct skl_ddb_allocation *ddb,
> > > +			      struct skl_pipe_wm *pipe_wm,
> > > +			      struct intel_crtc_state *crtc_state,
> > > +			      const struct intel_plane_state *plane_state)
> > > +{
> > > +	enum plane_id plane_id = to_intel_plane(plane_state->base.plane)->id;
> > > +	int ret;
> > > +
> > > +	/* Watermarks calculated in master */
> > > +	if (plane_state->slave)
> > > +		return 0;
> > > +
> > > +	if (plane_state->linked_plane) {
> > > +		const struct drm_framebuffer *fb = plane_state->base.fb;
> > > +		enum plane_id y_plane_id = plane_state->linked_plane->id;
> > > +
> > > +		WARN_ON(!fb->format->is_yuv ||
> > > +			fb->format->num_planes == 1);
> > > +
> > > +		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
> > > +						y_plane_id, 0);
> > > +		if (ret)
> > > +			return ret;
> > > +
> > > +		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
> > > +						plane_id, 1);
> > > +		if (ret)
> > > +			return ret;
> > > +	} else if (intel_wm_plane_visible(crtc_state, plane_state)) {
> > 
> > Isn't a visibility test also relevant to the nv12 (master plane) case
> > above?  I don't understand why we'd only test it for rgb planes.
> 
> linked_plane!=NULL implies that the plane is visible (see 
> icl_check_nv12_planes()). I should probably add another WARN_ON() for
> that.

Ah, okay.  In that case, with or without the WARN_ON(),

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>


-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 08/13] drm/i915: Clean up skl+ vs. icl+ watermark computation

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Make a cleaner split between the skl+ and icl+ ways of computing
watermarks. This way skl_build_pipe_wm() doesn't have to know any
of the gritty details of icl+ master/slave planes.

We can also simplify a bunch of the lower level code by pulling
the plane visibility checks a bit higher up.

v2: WARN_ON(!visible) for the icl+ master plane case (Matt)

Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 169 +++++++++++++++++---------------
 1 file changed, 92 insertions(+), 77 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index db28fc547c65..99f825d1c2e7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4630,9 +4630,6 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
 		to_intel_atomic_state(cstate->base.state);
 	bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
 
-	if (!intel_wm_plane_visible(cstate, intel_pstate))
-		return 0;
-
 	/* only NV12 format has two planes */
 	if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
 		DRM_DEBUG_KMS("Non NV12 format have single plane\n");
@@ -4746,9 +4743,6 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 	if (latency == 0)
 		return level == 0 ? -EINVAL : 0;
 
-	if (!intel_wm_plane_visible(cstate, intel_pstate))
-		return 0;
-
 	/* Display WA #1141: kbl,cfl */
 	if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
 	    IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) &&
@@ -4871,21 +4865,16 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 
 static int
 skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
-		      struct skl_ddb_allocation *ddb,
 		      const struct intel_crtc_state *cstate,
 		      const struct intel_plane_state *intel_pstate,
 		      uint16_t ddb_blocks,
 		      const struct skl_wm_params *wm_params,
-		      struct skl_plane_wm *wm,
 		      struct skl_wm_level *levels)
 {
 	int level, max_level = ilk_wm_max_level(dev_priv);
 	struct skl_wm_level *result_prev = &levels[0];
 	int ret;
 
-	if (WARN_ON(!intel_pstate->base.fb))
-		return -EINVAL;
-
 	for (level = 0; level <= max_level; level++) {
 		struct skl_wm_level *result = &levels[level];
 
@@ -4903,9 +4892,6 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
 		result_prev = result;
 	}
 
-	if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
-		wm->is_planar = true;
-
 	return 0;
 }
 
@@ -4943,9 +4929,6 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
 	const uint16_t trans_amount = 10; /* This is configurable amount */
 	uint16_t wm0_sel_res_b, trans_offset_b, res_blocks;
 
-	if (!cstate->base.active)
-		return;
-
 	/* Transition WM are not recommended by HW team for GEN9 */
 	if (INTEL_GEN(dev_priv) <= 9)
 		return;
@@ -4994,97 +4977,135 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
 	}
 }
 
-static int __skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
-				       struct skl_pipe_wm *pipe_wm,
-				       enum plane_id plane_id,
-				       const struct intel_crtc_state *cstate,
-				       const struct intel_plane_state *pstate,
-				       int color_plane)
+static int skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
+				     struct intel_crtc_state *crtc_state,
+				     const struct intel_plane_state *plane_state,
+				     enum plane_id plane_id, int color_plane)
 {
-	struct drm_i915_private *dev_priv = to_i915(pstate->base.plane->dev);
-	struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
-	enum pipe pipe = to_intel_plane(pstate->base.plane)->pipe;
+	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
 	struct skl_wm_params wm_params;
+	enum pipe pipe = plane->pipe;
 	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
 	int ret;
 
-	ret = skl_compute_plane_wm_params(dev_priv, cstate, pstate,
+	ret = skl_compute_plane_wm_params(dev_priv, crtc_state, plane_state,
 					  &wm_params, color_plane);
 	if (ret)
 		return ret;
 
-	ret = skl_compute_wm_levels(dev_priv, ddb, cstate, pstate,
-				    ddb_blocks, &wm_params, wm, wm->wm);
-
+	ret = skl_compute_wm_levels(dev_priv, crtc_state, plane_state,
+				    ddb_blocks, &wm_params, wm->wm);
 	if (ret)
 		return ret;
 
-	skl_compute_transition_wm(cstate, &wm_params, wm, ddb_blocks);
+	skl_compute_transition_wm(crtc_state, &wm_params, wm, ddb_blocks);
 
 	return 0;
 }
 
-static int skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
-				     struct skl_pipe_wm *pipe_wm,
-				     const struct intel_crtc_state *cstate,
-				     const struct intel_plane_state *pstate)
-{
-	enum plane_id plane_id = to_intel_plane(pstate->base.plane)->id;
-
-	return __skl_build_plane_wm_single(ddb, pipe_wm, plane_id, cstate, pstate, 0);
-}
-
-static int skl_build_plane_wm_planar(struct skl_ddb_allocation *ddb,
-				     struct skl_pipe_wm *pipe_wm,
-				     const struct intel_crtc_state *cstate,
-				     const struct intel_plane_state *pstate)
+static int skl_build_plane_wm_uv(struct skl_ddb_allocation *ddb,
+				 struct intel_crtc_state *crtc_state,
+				 const struct intel_plane_state *plane_state,
+				 enum plane_id plane_id)
 {
-	struct intel_plane *plane = to_intel_plane(pstate->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-	enum plane_id plane_id = plane->id;
-	struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
+	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
 	struct skl_wm_params wm_params;
 	enum pipe pipe = plane->pipe;
-	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
+	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->uv_plane[pipe][plane_id]);
 	int ret;
 
-	ret = __skl_build_plane_wm_single(ddb, pipe_wm, plane_id, cstate, pstate, 0);
-	if (ret)
-		return ret;
+	wm->is_planar = true;
 
 	/* uv plane watermarks must also be validated for NV12/Planar */
-	ddb_blocks = skl_ddb_entry_size(&ddb->uv_plane[pipe][plane_id]);
+	ret = skl_compute_plane_wm_params(dev_priv, crtc_state, plane_state,
+					  &wm_params, 1);
+	if (ret)
+		return ret;
 
-	ret = skl_compute_plane_wm_params(dev_priv, cstate, pstate, &wm_params, 1);
+	ret = skl_compute_wm_levels(dev_priv, crtc_state, plane_state,
+				    ddb_blocks, &wm_params, wm->uv_wm);
 	if (ret)
 		return ret;
 
-	return skl_compute_wm_levels(dev_priv, ddb, cstate, pstate,
-				     ddb_blocks, &wm_params, wm, wm->uv_wm);
+	return 0;
 }
 
-static int icl_build_plane_wm_planar(struct skl_ddb_allocation *ddb,
-				     struct skl_pipe_wm *pipe_wm,
-				     const struct intel_crtc_state *cstate,
-				     const struct intel_plane_state *pstate)
+static int skl_build_plane_wm(struct skl_ddb_allocation *ddb,
+			      struct skl_pipe_wm *pipe_wm,
+			      struct intel_crtc_state *crtc_state,
+			      const struct intel_plane_state *plane_state)
 {
+	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	const struct drm_framebuffer *fb = plane_state->base.fb;
+	enum plane_id plane_id = plane->id;
 	int ret;
-	enum plane_id y_plane_id = pstate->linked_plane->id;
-	enum plane_id uv_plane_id = to_intel_plane(pstate->base.plane)->id;
 
-	ret = __skl_build_plane_wm_single(ddb, pipe_wm, y_plane_id,
-					  cstate, pstate, 0);
+	if (!intel_wm_plane_visible(crtc_state, plane_state))
+		return 0;
+
+	ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
+					plane_id, 0);
 	if (ret)
 		return ret;
 
-	return __skl_build_plane_wm_single(ddb, pipe_wm, uv_plane_id,
-					   cstate, pstate, 1);
+	if (fb->format->is_yuv && fb->format->num_planes > 1) {
+		ret = skl_build_plane_wm_uv(ddb, crtc_state, plane_state,
+					    plane_id);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int icl_build_plane_wm(struct skl_ddb_allocation *ddb,
+			      struct skl_pipe_wm *pipe_wm,
+			      struct intel_crtc_state *crtc_state,
+			      const struct intel_plane_state *plane_state)
+{
+	enum plane_id plane_id = to_intel_plane(plane_state->base.plane)->id;
+	int ret;
+
+	/* Watermarks calculated in master */
+	if (plane_state->slave)
+		return 0;
+
+	if (plane_state->linked_plane) {
+		const struct drm_framebuffer *fb = plane_state->base.fb;
+		enum plane_id y_plane_id = plane_state->linked_plane->id;
+
+		WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state));
+		WARN_ON(!fb->format->is_yuv ||
+			fb->format->num_planes == 1);
+
+		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
+						y_plane_id, 0);
+		if (ret)
+			return ret;
+
+		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
+						plane_id, 1);
+		if (ret)
+			return ret;
+	} else if (intel_wm_plane_visible(crtc_state, plane_state)) {
+		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
+						plane_id, 0);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
 }
 
 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
 			     struct skl_ddb_allocation *ddb,
 			     struct skl_pipe_wm *pipe_wm)
 {
+	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
 	struct drm_crtc_state *crtc_state = &cstate->base;
 	struct drm_plane *plane;
 	const struct drm_plane_state *pstate;
@@ -5100,18 +5121,12 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
 		const struct intel_plane_state *intel_pstate =
 						to_intel_plane_state(pstate);
 
-		/* Watermarks calculated in master */
-		if (intel_pstate->slave)
-			continue;
-
-		if (intel_pstate->linked_plane)
-			ret = icl_build_plane_wm_planar(ddb, pipe_wm, cstate, intel_pstate);
-		else if (intel_pstate->base.fb &&
-			 intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
-			ret = skl_build_plane_wm_planar(ddb, pipe_wm, cstate, intel_pstate);
+		if (INTEL_GEN(dev_priv) >= 11)
+			ret = icl_build_plane_wm(ddb, pipe_wm,
+						 cstate, intel_pstate);
 		else
-			ret = skl_build_plane_wm_single(ddb, pipe_wm, cstate, intel_pstate);
-
+			ret = skl_build_plane_wm(ddb, pipe_wm,
+						 cstate, intel_pstate);
 		if (ret)
 			return ret;
 	}
-- 
2.18.1

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[PATCH v2 09/13] drm/i915: Don't pass dev_priv around so much

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Simplify the calling convention of the skl+ watermark functions
by not passing around dev_priv needlessly. The callees have
what they need to dig it out anyway.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 27 +++++++++++++--------------
 1 file changed, 13 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a743e089ab7d..a21654c974ba 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4578,12 +4578,12 @@ skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
 }
 
 static int
-skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
-			    const struct intel_crtc_state *cstate,
+skl_compute_plane_wm_params(const struct intel_crtc_state *cstate,
 			    const struct intel_plane_state *intel_pstate,
 			    struct skl_wm_params *wp, int plane_id)
 {
 	struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	const struct drm_plane_state *pstate = &intel_pstate->base;
 	const struct drm_framebuffer *fb = pstate->fb;
 	uint32_t interm_pbpl;
@@ -4682,8 +4682,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
 	return 0;
 }
 
-static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
-				const struct intel_crtc_state *cstate,
+static int skl_compute_plane_wm(const struct intel_crtc_state *cstate,
 				const struct intel_plane_state *intel_pstate,
 				uint16_t ddb_allocation,
 				int level,
@@ -4691,6 +4690,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 				const struct skl_wm_level *result_prev,
 				struct skl_wm_level *result /* out */)
 {
+	struct drm_i915_private *dev_priv =
+		to_i915(intel_pstate->base.plane->dev);
 	const struct drm_plane_state *pstate = &intel_pstate->base;
 	uint32_t latency = dev_priv->wm.skl_latency[level];
 	uint_fixed_16_16_t method1, method2;
@@ -4825,13 +4826,14 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 }
 
 static int
-skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
-		      const struct intel_crtc_state *cstate,
+skl_compute_wm_levels(const struct intel_crtc_state *cstate,
 		      const struct intel_plane_state *intel_pstate,
 		      uint16_t ddb_blocks,
 		      const struct skl_wm_params *wm_params,
 		      struct skl_wm_level *levels)
 {
+	struct drm_i915_private *dev_priv =
+		to_i915(intel_pstate->base.plane->dev);
 	int level, max_level = ilk_wm_max_level(dev_priv);
 	struct skl_wm_level *result_prev = &levels[0];
 	int ret;
@@ -4839,8 +4841,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
 	for (level = 0; level <= max_level; level++) {
 		struct skl_wm_level *result = &levels[level];
 
-		ret = skl_compute_plane_wm(dev_priv,
-					   cstate,
+		ret = skl_compute_plane_wm(cstate,
 					   intel_pstate,
 					   ddb_blocks,
 					   level,
@@ -4944,19 +4945,18 @@ static int skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
 				     enum plane_id plane_id, int color_plane)
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
-	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
 	struct skl_wm_params wm_params;
 	enum pipe pipe = plane->pipe;
 	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
 	int ret;
 
-	ret = skl_compute_plane_wm_params(dev_priv, crtc_state, plane_state,
+	ret = skl_compute_plane_wm_params(crtc_state, plane_state,
 					  &wm_params, color_plane);
 	if (ret)
 		return ret;
 
-	ret = skl_compute_wm_levels(dev_priv, crtc_state, plane_state,
+	ret = skl_compute_wm_levels(crtc_state, plane_state,
 				    ddb_blocks, &wm_params, wm->wm);
 	if (ret)
 		return ret;
@@ -4972,7 +4972,6 @@ static int skl_build_plane_wm_uv(struct skl_ddb_allocation *ddb,
 				 enum plane_id plane_id)
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
-	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
 	struct skl_wm_params wm_params;
 	enum pipe pipe = plane->pipe;
@@ -4982,12 +4981,12 @@ static int skl_build_plane_wm_uv(struct skl_ddb_allocation *ddb,
 	wm->is_planar = true;
 
 	/* uv plane watermarks must also be validated for NV12/Planar */
-	ret = skl_compute_plane_wm_params(dev_priv, crtc_state, plane_state,
+	ret = skl_compute_plane_wm_params(crtc_state, plane_state,
 					  &wm_params, 1);
 	if (ret)
 		return ret;
 
-	ret = skl_compute_wm_levels(dev_priv, crtc_state, plane_state,
+	ret = skl_compute_wm_levels(crtc_state, plane_state,
 				    ddb_blocks, &wm_params, wm->uv_wm);
 	if (ret)
 		return ret;
-- 
2.18.1

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Re: [PATCH v2 09/13] drm/i915: Don't pass dev_priv around so much

[Matt Roper]

On Wed, Nov 14, 2018 at 11:07:25PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Simplify the calling convention of the skl+ watermark functions
> by not passing around dev_priv needlessly. The callees have
> what they need to dig it out anyway.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 27 +++++++++++++--------------
>  1 file changed, 13 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a743e089ab7d..a21654c974ba 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4578,12 +4578,12 @@ skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
>  }
>  
>  static int
> -skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
> -			    const struct intel_crtc_state *cstate,
> +skl_compute_plane_wm_params(const struct intel_crtc_state *cstate,
>  			    const struct intel_plane_state *intel_pstate,
>  			    struct skl_wm_params *wp, int plane_id)
>  {
>  	struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	const struct drm_plane_state *pstate = &intel_pstate->base;
>  	const struct drm_framebuffer *fb = pstate->fb;
>  	uint32_t interm_pbpl;
> @@ -4682,8 +4682,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
>  	return 0;
>  }
>  
> -static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> -				const struct intel_crtc_state *cstate,
> +static int skl_compute_plane_wm(const struct intel_crtc_state *cstate,
>  				const struct intel_plane_state *intel_pstate,
>  				uint16_t ddb_allocation,
>  				int level,
> @@ -4691,6 +4690,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>  				const struct skl_wm_level *result_prev,
>  				struct skl_wm_level *result /* out */)
>  {
> +	struct drm_i915_private *dev_priv =
> +		to_i915(intel_pstate->base.plane->dev);
>  	const struct drm_plane_state *pstate = &intel_pstate->base;
>  	uint32_t latency = dev_priv->wm.skl_latency[level];
>  	uint_fixed_16_16_t method1, method2;
> @@ -4825,13 +4826,14 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>  }
>  
>  static int
> -skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
> -		      const struct intel_crtc_state *cstate,
> +skl_compute_wm_levels(const struct intel_crtc_state *cstate,
>  		      const struct intel_plane_state *intel_pstate,
>  		      uint16_t ddb_blocks,
>  		      const struct skl_wm_params *wm_params,
>  		      struct skl_wm_level *levels)
>  {
> +	struct drm_i915_private *dev_priv =
> +		to_i915(intel_pstate->base.plane->dev);
>  	int level, max_level = ilk_wm_max_level(dev_priv);
>  	struct skl_wm_level *result_prev = &levels[0];
>  	int ret;
> @@ -4839,8 +4841,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
>  	for (level = 0; level <= max_level; level++) {
>  		struct skl_wm_level *result = &levels[level];
>  
> -		ret = skl_compute_plane_wm(dev_priv,
> -					   cstate,
> +		ret = skl_compute_plane_wm(cstate,
>  					   intel_pstate,
>  					   ddb_blocks,
>  					   level,
> @@ -4944,19 +4945,18 @@ static int skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
>  				     enum plane_id plane_id, int color_plane)
>  {
>  	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> -	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
>  	struct skl_wm_params wm_params;
>  	enum pipe pipe = plane->pipe;
>  	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
>  	int ret;
>  
> -	ret = skl_compute_plane_wm_params(dev_priv, crtc_state, plane_state,
> +	ret = skl_compute_plane_wm_params(crtc_state, plane_state,
>  					  &wm_params, color_plane);
>  	if (ret)
>  		return ret;
>  
> -	ret = skl_compute_wm_levels(dev_priv, crtc_state, plane_state,
> +	ret = skl_compute_wm_levels(crtc_state, plane_state,
>  				    ddb_blocks, &wm_params, wm->wm);
>  	if (ret)
>  		return ret;
> @@ -4972,7 +4972,6 @@ static int skl_build_plane_wm_uv(struct skl_ddb_allocation *ddb,
>  				 enum plane_id plane_id)
>  {
>  	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> -	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
>  	struct skl_wm_params wm_params;
>  	enum pipe pipe = plane->pipe;
> @@ -4982,12 +4981,12 @@ static int skl_build_plane_wm_uv(struct skl_ddb_allocation *ddb,
>  	wm->is_planar = true;
>  
>  	/* uv plane watermarks must also be validated for NV12/Planar */
> -	ret = skl_compute_plane_wm_params(dev_priv, crtc_state, plane_state,
> +	ret = skl_compute_plane_wm_params(crtc_state, plane_state,
>  					  &wm_params, 1);
>  	if (ret)
>  		return ret;
>  
> -	ret = skl_compute_wm_levels(dev_priv, crtc_state, plane_state,
> +	ret = skl_compute_wm_levels(crtc_state, plane_state,
>  				    ddb_blocks, &wm_params, wm->uv_wm);
>  	if (ret)
>  		return ret;
> -- 
> 2.18.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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[PATCH v2 10/13] drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On SKL+ the plane WM/BUF_CFG registers are a proper part of each
plane's register set. That means accessing them will cancel any
pending plane update, and we would need a PLANE_SURF register write
to arm the wm/ddb change as well.

To avoid all the problems with that let's just move the wm/ddb
programming into the plane update/disable hooks. Now all plane
registers get written in one (hopefully atomic) operation.

To make that feasible we'll move the plane ddb tracking into
the crtc state. Watermarks were already tracked there.

v2: Rebase due to input CSC
v3: Split out a bunch of junk (Matt)

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  21 +-
 drivers/gpu/drm/i915/i915_drv.h      |   3 -
 drivers/gpu/drm/i915/intel_display.c |  16 +-
 drivers/gpu/drm/i915/intel_display.h |  11 +-
 drivers/gpu/drm/i915/intel_drv.h     |   9 +
 drivers/gpu/drm/i915/intel_pm.c      | 317 ++++++++++++---------------
 drivers/gpu/drm/i915/intel_sprite.c  |   4 +
 7 files changed, 181 insertions(+), 200 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 670db5073d70..f8b2200947cf 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3437,31 +3437,32 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
 	struct drm_device *dev = &dev_priv->drm;
-	struct skl_ddb_allocation *ddb;
 	struct skl_ddb_entry *entry;
-	enum pipe pipe;
-	int plane;
+	struct intel_crtc *crtc;
 
 	if (INTEL_GEN(dev_priv) < 9)
 		return -ENODEV;
 
 	drm_modeset_lock_all(dev);
 
-	ddb = &dev_priv->wm.skl_hw.ddb;
-
 	seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
 
-	for_each_pipe(dev_priv, pipe) {
+	for_each_intel_crtc(&dev_priv->drm, crtc) {
+		struct intel_crtc_state *crtc_state =
+			to_intel_crtc_state(crtc->base.state);
+		enum pipe pipe = crtc->pipe;
+		enum plane_id plane_id;
+
 		seq_printf(m, "Pipe %c\n", pipe_name(pipe));
 
-		for_each_universal_plane(dev_priv, pipe, plane) {
-			entry = &ddb->plane[pipe][plane];
-			seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
+		for_each_plane_id_on_crtc(crtc, plane_id) {
+			entry = &crtc_state->wm.skl.plane_ddb_y[plane_id];
+			seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane_id + 1,
 				   entry->start, entry->end,
 				   skl_ddb_entry_size(entry));
 		}
 
-		entry = &ddb->plane[pipe][PLANE_CURSOR];
+		entry = &crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
 		seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
 			   entry->end, skl_ddb_entry_size(entry));
 	}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5d686b585a95..89af64fe90a5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1241,9 +1241,6 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
 }
 
 struct skl_ddb_allocation {
-	/* packed/y */
-	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
-	struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
 	u8 enabled_slices; /* GEN11 has configurable 2 slices */
 };
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0caba7258fee..2981cea3704a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10083,6 +10083,10 @@ static void i9xx_update_cursor(struct intel_plane *plane,
 	 * except when the plane is getting enabled at which time
 	 * the CURCNTR write arms the update.
 	 */
+
+	if (INTEL_GEN(dev_priv) >= 9)
+		skl_write_cursor_wm(plane, crtc_state);
+
 	if (plane->cursor.base != base ||
 	    plane->cursor.size != fbc_ctl ||
 	    plane->cursor.cntl != cntl) {
@@ -11872,6 +11876,8 @@ static void verify_wm_state(struct drm_crtc *crtc,
 	struct skl_pipe_wm hw_wm, *sw_wm;
 	struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
 	struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
+	struct skl_ddb_entry hw_ddb_y[I915_MAX_PLANES];
+	struct skl_ddb_entry hw_ddb_uv[I915_MAX_PLANES];
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	const enum pipe pipe = intel_crtc->pipe;
 	int plane, level, max_level = ilk_wm_max_level(dev_priv);
@@ -11882,6 +11888,8 @@ static void verify_wm_state(struct drm_crtc *crtc,
 	skl_pipe_wm_get_hw_state(crtc, &hw_wm);
 	sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
 
+	skl_pipe_ddb_get_hw_state(intel_crtc, hw_ddb_y, hw_ddb_uv);
+
 	skl_ddb_get_hw_state(dev_priv, &hw_ddb);
 	sw_ddb = &dev_priv->wm.skl_hw.ddb;
 
@@ -11924,8 +11932,8 @@ static void verify_wm_state(struct drm_crtc *crtc,
 		}
 
 		/* DDB */
-		hw_ddb_entry = &hw_ddb.plane[pipe][plane];
-		sw_ddb_entry = &sw_ddb->plane[pipe][plane];
+		hw_ddb_entry = &hw_ddb_y[plane];
+		sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[plane];
 
 		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
 			DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
@@ -11974,8 +11982,8 @@ static void verify_wm_state(struct drm_crtc *crtc,
 		}
 
 		/* DDB */
-		hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
-		sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
+		hw_ddb_entry = &hw_ddb_y[PLANE_CURSOR];
+		sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[PLANE_CURSOR];
 
 		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
 			DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index df9e6ebb27de..078406dc65e5 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -319,7 +319,7 @@ struct intel_link_m_n {
 			    &(dev)->mode_config.plane_list,		\
 			    base.head)					\
 		for_each_if((plane_mask) &				\
-			    drm_plane_mask(&intel_plane->base)))
+			    drm_plane_mask(&intel_plane->base))
 
 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
 	list_for_each_entry(intel_plane,				\
@@ -415,6 +415,15 @@ struct intel_link_m_n {
 	     (__i)++) \
 		for_each_if(plane)
 
+#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.dev->mode_config.num_crtc && \
+		     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+		      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+		      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)++) \
+		for_each_if(crtc)
+
 void intel_link_compute_m_n(int bpp, int nlanes,
 			    int pixel_clock, int link_clock,
 			    struct intel_link_m_n *m_n,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 23b33970db17..4a9af09c483a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -705,6 +705,8 @@ struct intel_crtc_wm_state {
 			/* gen9+ only needs 1-step wm programming */
 			struct skl_pipe_wm optimal;
 			struct skl_ddb_entry ddb;
+			struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
+			struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
 		} skl;
 
 		struct {
@@ -2183,6 +2185,9 @@ void g4x_wm_get_hw_state(struct drm_device *dev);
 void vlv_wm_get_hw_state(struct drm_device *dev);
 void ilk_wm_get_hw_state(struct drm_device *dev);
 void skl_wm_get_hw_state(struct drm_device *dev);
+void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
+			       struct skl_ddb_entry *ddb_y,
+			       struct skl_ddb_entry *ddb_uv);
 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
 			  struct skl_ddb_allocation *ddb /* out */);
 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
@@ -2197,6 +2202,10 @@ bool skl_wm_level_equals(const struct skl_wm_level *l1,
 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
 				 const struct skl_ddb_entry entries[],
 				 int num_entries, int ignore_idx);
+void skl_write_plane_wm(struct intel_plane *plane,
+			const struct intel_crtc_state *crtc_state);
+void skl_write_cursor_wm(struct intel_plane *plane,
+			 const struct intel_crtc_state *crtc_state);
 bool ilk_disable_lp_wm(struct drm_device *dev);
 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
 				  struct intel_crtc_state *cstate);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a21654c974ba..1b337004054a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3912,68 +3912,70 @@ static void
 skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
 			   const enum pipe pipe,
 			   const enum plane_id plane_id,
-			   struct skl_ddb_allocation *ddb /* out */)
+			   struct skl_ddb_entry *ddb_y,
+			   struct skl_ddb_entry *ddb_uv)
 {
-	u32 val, val2 = 0;
-	int fourcc, pixel_format;
+	u32 val, val2;
+	u32 fourcc = 0;
 
 	/* Cursor doesn't support NV12/planar, so no extra calculation needed */
 	if (plane_id == PLANE_CURSOR) {
 		val = I915_READ(CUR_BUF_CFG(pipe));
-		skl_ddb_entry_init_from_hw(dev_priv,
-					   &ddb->plane[pipe][plane_id], val);
+		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
 		return;
 	}
 
 	val = I915_READ(PLANE_CTL(pipe, plane_id));
 
 	/* No DDB allocated for disabled planes */
-	if (!(val & PLANE_CTL_ENABLE))
-		return;
+	if (val & PLANE_CTL_ENABLE)
+		fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK,
+					      val & PLANE_CTL_ORDER_RGBX,
+					      val & PLANE_CTL_ALPHA_MASK);
 
-	pixel_format = val & PLANE_CTL_FORMAT_MASK;
-	fourcc = skl_format_to_fourcc(pixel_format,
-				      val & PLANE_CTL_ORDER_RGBX,
-				      val & PLANE_CTL_ALPHA_MASK);
-
-	val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
-	if (fourcc == DRM_FORMAT_NV12 && INTEL_GEN(dev_priv) < 11) {
+	if (INTEL_GEN(dev_priv) >= 11) {
+		val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
+		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
+	} else {
+		val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
 		val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
 
-		skl_ddb_entry_init_from_hw(dev_priv,
-					   &ddb->plane[pipe][plane_id], val2);
-		skl_ddb_entry_init_from_hw(dev_priv,
-					   &ddb->uv_plane[pipe][plane_id], val);
-	} else {
-		skl_ddb_entry_init_from_hw(dev_priv,
-					   &ddb->plane[pipe][plane_id], val);
+		if (fourcc == DRM_FORMAT_NV12)
+			swap(val, val2);
+
+		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
+		skl_ddb_entry_init_from_hw(dev_priv, ddb_uv, val2);
 	}
 }
 
+void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
+			       struct skl_ddb_entry *ddb_y,
+			       struct skl_ddb_entry *ddb_uv)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum intel_display_power_domain power_domain;
+	enum pipe pipe = crtc->pipe;
+	enum plane_id plane_id;
+
+	power_domain = POWER_DOMAIN_PIPE(pipe);
+	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
+		return;
+
+	for_each_plane_id_on_crtc(crtc, plane_id)
+		skl_ddb_get_hw_plane_state(dev_priv, pipe,
+					   plane_id,
+					   &ddb_y[plane_id],
+					   &ddb_uv[plane_id]);
+
+	intel_display_power_put(dev_priv, power_domain);
+}
+
 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
 			  struct skl_ddb_allocation *ddb /* out */)
 {
-	struct intel_crtc *crtc;
-
 	memset(ddb, 0, sizeof(*ddb));
 
 	ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
-
-	for_each_intel_crtc(&dev_priv->drm, crtc) {
-		enum intel_display_power_domain power_domain;
-		enum plane_id plane_id;
-		enum pipe pipe = crtc->pipe;
-
-		power_domain = POWER_DOMAIN_PIPE(pipe);
-		if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
-			continue;
-
-		for_each_plane_id_on_crtc(crtc, plane_id)
-			skl_ddb_get_hw_plane_state(dev_priv, pipe,
-						   plane_id, ddb);
-
-		intel_display_power_put(dev_priv, power_domain);
-	}
 }
 
 /*
@@ -4371,7 +4373,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 	struct drm_crtc *crtc = cstate->base.crtc;
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	enum pipe pipe = intel_crtc->pipe;
 	struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
 	uint16_t alloc_size, start;
 	uint16_t minimum[I915_MAX_PLANES] = {};
@@ -4384,8 +4385,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 	uint16_t total_min_blocks = 0;
 
 	/* Clear the partitioning for disabled planes. */
-	memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
-	memset(ddb->uv_plane[pipe], 0, sizeof(ddb->uv_plane[pipe]));
+	memset(cstate->wm.skl.plane_ddb_y, 0, sizeof(cstate->wm.skl.plane_ddb_y));
+	memset(cstate->wm.skl.plane_ddb_uv, 0, sizeof(cstate->wm.skl.plane_ddb_uv));
 
 	if (WARN_ON(!state))
 		return 0;
@@ -4432,8 +4433,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 	}
 
 	alloc_size -= total_min_blocks;
-	ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
-	ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
+	cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
+	cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
 
 	/*
 	 * 2. Distribute the remaining space in proportion to the amount of
@@ -4464,8 +4465,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 
 		/* Leave disabled planes at (0,0) */
 		if (data_rate) {
-			ddb->plane[pipe][plane_id].start = start;
-			ddb->plane[pipe][plane_id].end = start + plane_blocks;
+			cstate->wm.skl.plane_ddb_y[plane_id].start = start;
+			cstate->wm.skl.plane_ddb_y[plane_id].end = start + plane_blocks;
 		}
 
 		start += plane_blocks;
@@ -4480,8 +4481,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 		WARN_ON(INTEL_GEN(dev_priv) >= 11 && uv_plane_blocks);
 
 		if (uv_data_rate) {
-			ddb->uv_plane[pipe][plane_id].start = start;
-			ddb->uv_plane[pipe][plane_id].end =
+			cstate->wm.skl.plane_ddb_uv[plane_id].start = start;
+			cstate->wm.skl.plane_ddb_uv[plane_id].end =
 				start + uv_plane_blocks;
 		}
 
@@ -4939,16 +4940,13 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
 	}
 }
 
-static int skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
-				     struct intel_crtc_state *crtc_state,
+static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
 				     const struct intel_plane_state *plane_state,
 				     enum plane_id plane_id, int color_plane)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
+	u16 ddb_blocks = skl_ddb_entry_size(&crtc_state->wm.skl.plane_ddb_y[plane_id]);
 	struct skl_wm_params wm_params;
-	enum pipe pipe = plane->pipe;
-	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
 	int ret;
 
 	ret = skl_compute_plane_wm_params(crtc_state, plane_state,
@@ -4966,16 +4964,13 @@ static int skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
 	return 0;
 }
 
-static int skl_build_plane_wm_uv(struct skl_ddb_allocation *ddb,
-				 struct intel_crtc_state *crtc_state,
+static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
 				 const struct intel_plane_state *plane_state,
 				 enum plane_id plane_id)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
+	u16 ddb_blocks = skl_ddb_entry_size(&crtc_state->wm.skl.plane_ddb_uv[plane_id]);
 	struct skl_wm_params wm_params;
-	enum pipe pipe = plane->pipe;
-	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->uv_plane[pipe][plane_id]);
 	int ret;
 
 	wm->is_planar = true;
@@ -4994,8 +4989,7 @@ static int skl_build_plane_wm_uv(struct skl_ddb_allocation *ddb,
 	return 0;
 }
 
-static int skl_build_plane_wm(struct skl_ddb_allocation *ddb,
-			      struct skl_pipe_wm *pipe_wm,
+static int skl_build_plane_wm(struct skl_pipe_wm *pipe_wm,
 			      struct intel_crtc_state *crtc_state,
 			      const struct intel_plane_state *plane_state)
 {
@@ -5007,13 +5001,13 @@ static int skl_build_plane_wm(struct skl_ddb_allocation *ddb,
 	if (!intel_wm_plane_visible(crtc_state, plane_state))
 		return 0;
 
-	ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
+	ret = skl_build_plane_wm_single(crtc_state, plane_state,
 					plane_id, 0);
 	if (ret)
 		return ret;
 
 	if (fb->format->is_yuv && fb->format->num_planes > 1) {
-		ret = skl_build_plane_wm_uv(ddb, crtc_state, plane_state,
+		ret = skl_build_plane_wm_uv(crtc_state, plane_state,
 					    plane_id);
 		if (ret)
 			return ret;
@@ -5022,8 +5016,7 @@ static int skl_build_plane_wm(struct skl_ddb_allocation *ddb,
 	return 0;
 }
 
-static int icl_build_plane_wm(struct skl_ddb_allocation *ddb,
-			      struct skl_pipe_wm *pipe_wm,
+static int icl_build_plane_wm(struct skl_pipe_wm *pipe_wm,
 			      struct intel_crtc_state *crtc_state,
 			      const struct intel_plane_state *plane_state)
 {
@@ -5041,17 +5034,17 @@ static int icl_build_plane_wm(struct skl_ddb_allocation *ddb,
 		WARN_ON(!fb->format->is_yuv ||
 			fb->format->num_planes == 1);
 
-		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
+		ret = skl_build_plane_wm_single(crtc_state, plane_state,
 						y_plane_id, 0);
 		if (ret)
 			return ret;
 
-		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
+		ret = skl_build_plane_wm_single(crtc_state, plane_state,
 						plane_id, 1);
 		if (ret)
 			return ret;
 	} else if (intel_wm_plane_visible(crtc_state, plane_state)) {
-		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
+		ret = skl_build_plane_wm_single(crtc_state, plane_state,
 						plane_id, 0);
 		if (ret)
 			return ret;
@@ -5061,7 +5054,6 @@ static int icl_build_plane_wm(struct skl_ddb_allocation *ddb,
 }
 
 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
-			     struct skl_ddb_allocation *ddb,
 			     struct skl_pipe_wm *pipe_wm)
 {
 	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
@@ -5081,10 +5073,10 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
 						to_intel_plane_state(pstate);
 
 		if (INTEL_GEN(dev_priv) >= 11)
-			ret = icl_build_plane_wm(ddb, pipe_wm,
+			ret = icl_build_plane_wm(pipe_wm,
 						 cstate, intel_pstate);
 		else
-			ret = skl_build_plane_wm(ddb, pipe_wm,
+			ret = skl_build_plane_wm(pipe_wm,
 						 cstate, intel_pstate);
 		if (ret)
 			return ret;
@@ -5100,9 +5092,9 @@ static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
 				const struct skl_ddb_entry *entry)
 {
 	if (entry->end)
-		I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
+		I915_WRITE_FW(reg, (entry->end - 1) << 16 | entry->start);
 	else
-		I915_WRITE(reg, 0);
+		I915_WRITE_FW(reg, 0);
 }
 
 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
@@ -5117,19 +5109,22 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv,
 		val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
 	}
 
-	I915_WRITE(reg, val);
+	I915_WRITE_FW(reg, val);
 }
 
-static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
-			       const struct skl_plane_wm *wm,
-			       const struct skl_ddb_allocation *ddb,
-			       enum plane_id plane_id)
+void skl_write_plane_wm(struct intel_plane *plane,
+			const struct intel_crtc_state *crtc_state)
 {
-	struct drm_crtc *crtc = &intel_crtc->base;
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	int level, max_level = ilk_wm_max_level(dev_priv);
-	enum pipe pipe = intel_crtc->pipe;
+	enum plane_id plane_id = plane->id;
+	enum pipe pipe = plane->pipe;
+	const struct skl_plane_wm *wm =
+		&crtc_state->wm.skl.optimal.planes[plane_id];
+	const struct skl_ddb_entry *ddb_y =
+		&crtc_state->wm.skl.plane_ddb_y[plane_id];
+	const struct skl_ddb_entry *ddb_uv =
+		&crtc_state->wm.skl.plane_ddb_uv[plane_id];
 
 	for (level = 0; level <= max_level; level++) {
 		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
@@ -5138,29 +5133,32 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
 	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
 			   &wm->trans_wm);
 
-	if (wm->is_planar && INTEL_GEN(dev_priv) < 11) {
-		skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
-				    &ddb->uv_plane[pipe][plane_id]);
+	if (INTEL_GEN(dev_priv) >= 11) {
 		skl_ddb_entry_write(dev_priv,
-				    PLANE_NV12_BUF_CFG(pipe, plane_id),
-				    &ddb->plane[pipe][plane_id]);
-	} else {
-		skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
-				    &ddb->plane[pipe][plane_id]);
-		if (INTEL_GEN(dev_priv) < 11)
-			I915_WRITE(PLANE_NV12_BUF_CFG(pipe, plane_id), 0x0);
+				    PLANE_BUF_CFG(pipe, plane_id), ddb_y);
+		return;
 	}
+
+	if (wm->is_planar)
+		swap(ddb_y, ddb_uv);
+
+	skl_ddb_entry_write(dev_priv,
+			    PLANE_BUF_CFG(pipe, plane_id), ddb_y);
+	skl_ddb_entry_write(dev_priv,
+			    PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_uv);
 }
 
-static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
-				const struct skl_plane_wm *wm,
-				const struct skl_ddb_allocation *ddb)
+void skl_write_cursor_wm(struct intel_plane *plane,
+			 const struct intel_crtc_state *crtc_state)
 {
-	struct drm_crtc *crtc = &intel_crtc->base;
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	int level, max_level = ilk_wm_max_level(dev_priv);
-	enum pipe pipe = intel_crtc->pipe;
+	enum plane_id plane_id = plane->id;
+	enum pipe pipe = plane->pipe;
+	const struct skl_plane_wm *wm =
+		&crtc_state->wm.skl.optimal.planes[plane_id];
+	const struct skl_ddb_entry *ddb =
+		&crtc_state->wm.skl.plane_ddb_y[plane_id];
 
 	for (level = 0; level <= max_level; level++) {
 		skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
@@ -5168,8 +5166,7 @@ static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
 	}
 	skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
 
-	skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
-			    &ddb->plane[pipe][PLANE_CURSOR]);
+	skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), ddb);
 }
 
 bool skl_wm_level_equals(const struct skl_wm_level *l1,
@@ -5210,13 +5207,12 @@ bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
 			      const struct skl_pipe_wm *old_pipe_wm,
 			      struct skl_pipe_wm *pipe_wm, /* out */
-			      struct skl_ddb_allocation *ddb, /* out */
 			      bool *changed /* out */)
 {
 	struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
 	int ret;
 
-	ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
+	ret = skl_build_pipe_wm(intel_cstate, pipe_wm);
 	if (ret)
 		return ret;
 
@@ -5242,42 +5238,29 @@ pipes_modified(struct drm_atomic_state *state)
 }
 
 static int
-skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
+skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
+			    struct intel_crtc_state *new_crtc_state)
 {
-	struct drm_atomic_state *state = cstate->base.state;
-	struct drm_device *dev = state->dev;
-	struct drm_crtc *crtc = cstate->base.crtc;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-	struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
-	struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
-	struct drm_plane *plane;
-	enum pipe pipe = intel_crtc->pipe;
+	struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->base.state);
+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_plane *plane;
 
-	drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
-		struct drm_plane_state *plane_state;
-		struct intel_plane *linked;
-		enum plane_id plane_id = to_intel_plane(plane)->id;
+	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+		struct intel_plane_state *plane_state;
+		enum plane_id plane_id = plane->id;
 
-		if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
-					&new_ddb->plane[pipe][plane_id]) &&
-		    skl_ddb_entry_equal(&cur_ddb->uv_plane[pipe][plane_id],
-					&new_ddb->uv_plane[pipe][plane_id]))
+		if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
+					&new_crtc_state->wm.skl.plane_ddb_y[plane_id]) &&
+		    skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_uv[plane_id],
+					&new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
 			continue;
 
-		plane_state = drm_atomic_get_plane_state(state, plane);
+		plane_state = intel_atomic_get_plane_state(state, plane);
 		if (IS_ERR(plane_state))
 			return PTR_ERR(plane_state);
 
-		/* Make sure linked plane is updated too */
-		linked = to_intel_plane_state(plane_state)->linked_plane;
-		if (!linked)
-			continue;
-
-		plane_state = drm_atomic_get_plane_state(state, &linked->base);
-		if (IS_ERR(plane_state))
-			return PTR_ERR(plane_state);
+		new_crtc_state->update_planes |= BIT(plane_id);
 	}
 
 	return 0;
@@ -5289,18 +5272,21 @@ skl_compute_ddb(struct drm_atomic_state *state)
 	const struct drm_i915_private *dev_priv = to_i915(state->dev);
 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
 	struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
+	struct intel_crtc_state *old_crtc_state;
+	struct intel_crtc_state *new_crtc_state;
 	struct intel_crtc *crtc;
-	struct intel_crtc_state *cstate;
 	int ret, i;
 
 	memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
 
-	for_each_new_intel_crtc_in_state(intel_state, crtc, cstate, i) {
-		ret = skl_allocate_pipe_ddb(cstate, ddb);
+	for_each_oldnew_intel_crtc_in_state(intel_state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		ret = skl_allocate_pipe_ddb(new_crtc_state, ddb);
 		if (ret)
 			return ret;
 
-		ret = skl_ddb_add_affected_planes(cstate);
+		ret = skl_ddb_add_affected_planes(old_crtc_state,
+						  new_crtc_state);
 		if (ret)
 			return ret;
 	}
@@ -5309,36 +5295,29 @@ skl_compute_ddb(struct drm_atomic_state *state)
 }
 
 static void
-skl_print_wm_changes(const struct drm_atomic_state *state)
+skl_print_wm_changes(struct intel_atomic_state *state)
 {
-	const struct drm_device *dev = state->dev;
-	const struct drm_i915_private *dev_priv = to_i915(dev);
-	const struct intel_atomic_state *intel_state =
-		to_intel_atomic_state(state);
-	const struct drm_crtc *crtc;
-	const struct drm_crtc_state *cstate;
-	const struct intel_plane *intel_plane;
-	const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
-	const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	const struct intel_crtc_state *old_crtc_state;
+	const struct intel_crtc_state *new_crtc_state;
+	struct intel_plane *plane;
+	struct intel_crtc *crtc;
 	int i;
 
-	for_each_new_crtc_in_state(state, crtc, cstate, i) {
-		const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-		enum pipe pipe = intel_crtc->pipe;
-
-		for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
-			enum plane_id plane_id = intel_plane->id;
+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+			enum plane_id plane_id = plane->id;
 			const struct skl_ddb_entry *old, *new;
 
-			old = &old_ddb->plane[pipe][plane_id];
-			new = &new_ddb->plane[pipe][plane_id];
+			old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];
+			new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];
 
 			if (skl_ddb_entry_equal(old, new))
 				continue;
 
 			DRM_DEBUG_KMS("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
-				      intel_plane->base.base.id,
-				      intel_plane->base.name,
+				      plane->base.base.id, plane->base.name,
 				      old->start, old->end,
 				      new->start, new->end);
 		}
@@ -5474,8 +5453,7 @@ skl_compute_wm(struct drm_atomic_state *state)
 			&to_intel_crtc_state(crtc->state)->wm.skl.optimal;
 
 		pipe_wm = &intel_cstate->wm.skl.optimal;
-		ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
-					 &results->ddb, &changed);
+		ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm, &changed);
 		if (ret)
 			return ret;
 
@@ -5489,7 +5467,7 @@ skl_compute_wm(struct drm_atomic_state *state)
 		intel_cstate->update_wm_pre = true;
 	}
 
-	skl_print_wm_changes(state);
+	skl_print_wm_changes(intel_state);
 
 	return 0;
 }
@@ -5500,23 +5478,12 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
 	struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
-	const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
 	enum pipe pipe = crtc->pipe;
-	enum plane_id plane_id;
 
 	if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
 		return;
 
 	I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
-
-	for_each_plane_id_on_crtc(crtc, plane_id) {
-		if (plane_id != PLANE_CURSOR)
-			skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id],
-					   ddb, plane_id);
-		else
-			skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id],
-					    ddb);
-	}
 }
 
 static void skl_initial_wm(struct intel_atomic_state *state,
@@ -5526,8 +5493,6 @@ static void skl_initial_wm(struct intel_atomic_state *state,
 	struct drm_device *dev = intel_crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct skl_ddb_values *results = &state->wm_results;
-	struct skl_ddb_values *hw_vals = &dev_priv->wm.skl_hw;
-	enum pipe pipe = intel_crtc->pipe;
 
 	if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
 		return;
@@ -5537,11 +5502,6 @@ static void skl_initial_wm(struct intel_atomic_state *state,
 	if (cstate->base.active_changed)
 		skl_atomic_update_crtc_wm(state, cstate);
 
-	memcpy(hw_vals->ddb.uv_plane[pipe], results->ddb.uv_plane[pipe],
-	       sizeof(hw_vals->ddb.uv_plane[pipe]));
-	memcpy(hw_vals->ddb.plane[pipe], results->ddb.plane[pipe],
-	       sizeof(hw_vals->ddb.plane[pipe]));
-
 	mutex_unlock(&dev_priv->wm.wm_mutex);
 }
 
@@ -5692,13 +5652,6 @@ void skl_wm_get_hw_state(struct drm_device *dev)
 	if (dev_priv->active_crtcs) {
 		/* Fully recompute DDB on first atomic commit */
 		dev_priv->wm.distrust_bios_wm = true;
-	} else {
-		/*
-		 * Easy/common case; just sanitize DDB now if everything off
-		 * Keep dbuf slice info intact
-		 */
-		memset(ddb->plane, 0, sizeof(ddb->plane));
-		memset(ddb->uv_plane, 0, sizeof(ddb->uv_plane));
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 74d904a49bf9..0262159e7084 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -542,6 +542,8 @@ skl_program_plane(struct intel_plane *plane,
 	if (fb->format->is_yuv && icl_is_hdr_plane(plane))
 		icl_program_input_csc_coeff(crtc_state, plane_state);
 
+	skl_write_plane_wm(plane, crtc_state);
+
 	I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
 	I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk);
 	I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax);
@@ -604,6 +606,8 @@ skl_disable_plane(struct intel_plane *plane,
 
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
+	skl_write_plane_wm(plane, crtc_state);
+
 	I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
 	I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
 
-- 
2.18.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v4 10/13] drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On SKL+ the plane WM/BUF_CFG registers are a proper part of each
plane's register set. That means accessing them will cancel any
pending plane update, and we would need a PLANE_SURF register write
to arm the wm/ddb change as well.

To avoid all the problems with that let's just move the wm/ddb
programming into the plane update/disable hooks. Now all plane
registers get written in one (hopefully atomic) operation.

To make that feasible we'll move the plane ddb tracking into
the crtc state. Watermarks were already tracked there.

v2: Rebase due to input CSC
v3: Split out a bunch of junk (Matt)
v4: Add skl_wm_add_affected_planes() to deal with
    cursor special case and non-zero wm register reset value

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> #v3
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  21 +-
 drivers/gpu/drm/i915/i915_drv.h      |   3 -
 drivers/gpu/drm/i915/intel_display.c |  16 +-
 drivers/gpu/drm/i915/intel_display.h |  11 +-
 drivers/gpu/drm/i915/intel_drv.h     |   9 +
 drivers/gpu/drm/i915/intel_pm.c      | 405 ++++++++++++++-------------
 drivers/gpu/drm/i915/intel_sprite.c  |   4 +
 7 files changed, 262 insertions(+), 207 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 670db5073d70..f8b2200947cf 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3437,31 +3437,32 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
 	struct drm_device *dev = &dev_priv->drm;
-	struct skl_ddb_allocation *ddb;
 	struct skl_ddb_entry *entry;
-	enum pipe pipe;
-	int plane;
+	struct intel_crtc *crtc;
 
 	if (INTEL_GEN(dev_priv) < 9)
 		return -ENODEV;
 
 	drm_modeset_lock_all(dev);
 
-	ddb = &dev_priv->wm.skl_hw.ddb;
-
 	seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
 
-	for_each_pipe(dev_priv, pipe) {
+	for_each_intel_crtc(&dev_priv->drm, crtc) {
+		struct intel_crtc_state *crtc_state =
+			to_intel_crtc_state(crtc->base.state);
+		enum pipe pipe = crtc->pipe;
+		enum plane_id plane_id;
+
 		seq_printf(m, "Pipe %c\n", pipe_name(pipe));
 
-		for_each_universal_plane(dev_priv, pipe, plane) {
-			entry = &ddb->plane[pipe][plane];
-			seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
+		for_each_plane_id_on_crtc(crtc, plane_id) {
+			entry = &crtc_state->wm.skl.plane_ddb_y[plane_id];
+			seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane_id + 1,
 				   entry->start, entry->end,
 				   skl_ddb_entry_size(entry));
 		}
 
-		entry = &ddb->plane[pipe][PLANE_CURSOR];
+		entry = &crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
 		seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
 			   entry->end, skl_ddb_entry_size(entry));
 	}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 017f851a586a..845995051afa 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1230,9 +1230,6 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
 }
 
 struct skl_ddb_allocation {
-	/* packed/y */
-	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
-	struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
 	u8 enabled_slices; /* GEN11 has configurable 2 slices */
 };
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0caba7258fee..2981cea3704a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10083,6 +10083,10 @@ static void i9xx_update_cursor(struct intel_plane *plane,
 	 * except when the plane is getting enabled at which time
 	 * the CURCNTR write arms the update.
 	 */
+
+	if (INTEL_GEN(dev_priv) >= 9)
+		skl_write_cursor_wm(plane, crtc_state);
+
 	if (plane->cursor.base != base ||
 	    plane->cursor.size != fbc_ctl ||
 	    plane->cursor.cntl != cntl) {
@@ -11872,6 +11876,8 @@ static void verify_wm_state(struct drm_crtc *crtc,
 	struct skl_pipe_wm hw_wm, *sw_wm;
 	struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
 	struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
+	struct skl_ddb_entry hw_ddb_y[I915_MAX_PLANES];
+	struct skl_ddb_entry hw_ddb_uv[I915_MAX_PLANES];
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	const enum pipe pipe = intel_crtc->pipe;
 	int plane, level, max_level = ilk_wm_max_level(dev_priv);
@@ -11882,6 +11888,8 @@ static void verify_wm_state(struct drm_crtc *crtc,
 	skl_pipe_wm_get_hw_state(crtc, &hw_wm);
 	sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
 
+	skl_pipe_ddb_get_hw_state(intel_crtc, hw_ddb_y, hw_ddb_uv);
+
 	skl_ddb_get_hw_state(dev_priv, &hw_ddb);
 	sw_ddb = &dev_priv->wm.skl_hw.ddb;
 
@@ -11924,8 +11932,8 @@ static void verify_wm_state(struct drm_crtc *crtc,
 		}
 
 		/* DDB */
-		hw_ddb_entry = &hw_ddb.plane[pipe][plane];
-		sw_ddb_entry = &sw_ddb->plane[pipe][plane];
+		hw_ddb_entry = &hw_ddb_y[plane];
+		sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[plane];
 
 		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
 			DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
@@ -11974,8 +11982,8 @@ static void verify_wm_state(struct drm_crtc *crtc,
 		}
 
 		/* DDB */
-		hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
-		sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
+		hw_ddb_entry = &hw_ddb_y[PLANE_CURSOR];
+		sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[PLANE_CURSOR];
 
 		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
 			DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index 597c16366273..296425b12f62 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -319,7 +319,7 @@ struct intel_link_m_n {
 			    &(dev)->mode_config.plane_list,		\
 			    base.head)					\
 		for_each_if((plane_mask) &				\
-			    drm_plane_mask(&intel_plane->base)))
+			    drm_plane_mask(&intel_plane->base))
 
 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
 	list_for_each_entry(intel_plane,				\
@@ -415,6 +415,15 @@ struct intel_link_m_n {
 	     (__i)++) \
 		for_each_if(plane)
 
+#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.dev->mode_config.num_crtc && \
+		     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+		      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+		      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)++) \
+		for_each_if(crtc)
+
 void intel_link_compute_m_n(int bpp, int nlanes,
 			    int pixel_clock, int link_clock,
 			    struct intel_link_m_n *m_n,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a29a4f192773..76f91485c74a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -705,6 +705,8 @@ struct intel_crtc_wm_state {
 			/* gen9+ only needs 1-step wm programming */
 			struct skl_pipe_wm optimal;
 			struct skl_ddb_entry ddb;
+			struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
+			struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
 		} skl;
 
 		struct {
@@ -2183,6 +2185,9 @@ void g4x_wm_get_hw_state(struct drm_device *dev);
 void vlv_wm_get_hw_state(struct drm_device *dev);
 void ilk_wm_get_hw_state(struct drm_device *dev);
 void skl_wm_get_hw_state(struct drm_device *dev);
+void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
+			       struct skl_ddb_entry *ddb_y,
+			       struct skl_ddb_entry *ddb_uv);
 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
 			  struct skl_ddb_allocation *ddb /* out */);
 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
@@ -2197,6 +2202,10 @@ bool skl_wm_level_equals(const struct skl_wm_level *l1,
 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
 				 const struct skl_ddb_entry entries[],
 				 int num_entries, int ignore_idx);
+void skl_write_plane_wm(struct intel_plane *plane,
+			const struct intel_crtc_state *crtc_state);
+void skl_write_cursor_wm(struct intel_plane *plane,
+			 const struct intel_crtc_state *crtc_state);
 bool ilk_disable_lp_wm(struct drm_device *dev);
 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
 				  struct intel_crtc_state *cstate);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d85d94079192..6150f59cc52f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3951,68 +3951,70 @@ static void
 skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
 			   const enum pipe pipe,
 			   const enum plane_id plane_id,
-			   struct skl_ddb_allocation *ddb /* out */)
+			   struct skl_ddb_entry *ddb_y,
+			   struct skl_ddb_entry *ddb_uv)
 {
-	u32 val, val2 = 0;
-	int fourcc, pixel_format;
+	u32 val, val2;
+	u32 fourcc = 0;
 
 	/* Cursor doesn't support NV12/planar, so no extra calculation needed */
 	if (plane_id == PLANE_CURSOR) {
 		val = I915_READ(CUR_BUF_CFG(pipe));
-		skl_ddb_entry_init_from_hw(dev_priv,
-					   &ddb->plane[pipe][plane_id], val);
+		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
 		return;
 	}
 
 	val = I915_READ(PLANE_CTL(pipe, plane_id));
 
 	/* No DDB allocated for disabled planes */
-	if (!(val & PLANE_CTL_ENABLE))
-		return;
+	if (val & PLANE_CTL_ENABLE)
+		fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK,
+					      val & PLANE_CTL_ORDER_RGBX,
+					      val & PLANE_CTL_ALPHA_MASK);
 
-	pixel_format = val & PLANE_CTL_FORMAT_MASK;
-	fourcc = skl_format_to_fourcc(pixel_format,
-				      val & PLANE_CTL_ORDER_RGBX,
-				      val & PLANE_CTL_ALPHA_MASK);
-
-	val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
-	if (fourcc == DRM_FORMAT_NV12 && INTEL_GEN(dev_priv) < 11) {
+	if (INTEL_GEN(dev_priv) >= 11) {
+		val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
+		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
+	} else {
+		val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
 		val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
 
-		skl_ddb_entry_init_from_hw(dev_priv,
-					   &ddb->plane[pipe][plane_id], val2);
-		skl_ddb_entry_init_from_hw(dev_priv,
-					   &ddb->uv_plane[pipe][plane_id], val);
-	} else {
-		skl_ddb_entry_init_from_hw(dev_priv,
-					   &ddb->plane[pipe][plane_id], val);
+		if (fourcc == DRM_FORMAT_NV12)
+			swap(val, val2);
+
+		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
+		skl_ddb_entry_init_from_hw(dev_priv, ddb_uv, val2);
 	}
 }
 
+void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
+			       struct skl_ddb_entry *ddb_y,
+			       struct skl_ddb_entry *ddb_uv)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum intel_display_power_domain power_domain;
+	enum pipe pipe = crtc->pipe;
+	enum plane_id plane_id;
+
+	power_domain = POWER_DOMAIN_PIPE(pipe);
+	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
+		return;
+
+	for_each_plane_id_on_crtc(crtc, plane_id)
+		skl_ddb_get_hw_plane_state(dev_priv, pipe,
+					   plane_id,
+					   &ddb_y[plane_id],
+					   &ddb_uv[plane_id]);
+
+	intel_display_power_put(dev_priv, power_domain);
+}
+
 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
 			  struct skl_ddb_allocation *ddb /* out */)
 {
-	struct intel_crtc *crtc;
-
 	memset(ddb, 0, sizeof(*ddb));
 
 	ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
-
-	for_each_intel_crtc(&dev_priv->drm, crtc) {
-		enum intel_display_power_domain power_domain;
-		enum plane_id plane_id;
-		enum pipe pipe = crtc->pipe;
-
-		power_domain = POWER_DOMAIN_PIPE(pipe);
-		if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
-			continue;
-
-		for_each_plane_id_on_crtc(crtc, plane_id)
-			skl_ddb_get_hw_plane_state(dev_priv, pipe,
-						   plane_id, ddb);
-
-		intel_display_power_put(dev_priv, power_domain);
-	}
 }
 
 /*
@@ -4410,7 +4412,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 	struct drm_crtc *crtc = cstate->base.crtc;
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	enum pipe pipe = intel_crtc->pipe;
 	struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
 	uint16_t alloc_size, start;
 	uint16_t minimum[I915_MAX_PLANES] = {};
@@ -4423,8 +4424,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 	uint16_t total_min_blocks = 0;
 
 	/* Clear the partitioning for disabled planes. */
-	memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
-	memset(ddb->uv_plane[pipe], 0, sizeof(ddb->uv_plane[pipe]));
+	memset(cstate->wm.skl.plane_ddb_y, 0, sizeof(cstate->wm.skl.plane_ddb_y));
+	memset(cstate->wm.skl.plane_ddb_uv, 0, sizeof(cstate->wm.skl.plane_ddb_uv));
 
 	if (WARN_ON(!state))
 		return 0;
@@ -4471,8 +4472,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 	}
 
 	alloc_size -= total_min_blocks;
-	ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
-	ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
+	cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
+	cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
 
 	/*
 	 * 2. Distribute the remaining space in proportion to the amount of
@@ -4503,8 +4504,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 
 		/* Leave disabled planes at (0,0) */
 		if (data_rate) {
-			ddb->plane[pipe][plane_id].start = start;
-			ddb->plane[pipe][plane_id].end = start + plane_blocks;
+			cstate->wm.skl.plane_ddb_y[plane_id].start = start;
+			cstate->wm.skl.plane_ddb_y[plane_id].end = start + plane_blocks;
 		}
 
 		start += plane_blocks;
@@ -4519,8 +4520,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 		WARN_ON(INTEL_GEN(dev_priv) >= 11 && uv_plane_blocks);
 
 		if (uv_data_rate) {
-			ddb->uv_plane[pipe][plane_id].start = start;
-			ddb->uv_plane[pipe][plane_id].end =
+			cstate->wm.skl.plane_ddb_uv[plane_id].start = start;
+			cstate->wm.skl.plane_ddb_uv[plane_id].end =
 				start + uv_plane_blocks;
 		}
 
@@ -4978,16 +4979,13 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
 	}
 }
 
-static int skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
-				     struct intel_crtc_state *crtc_state,
+static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
 				     const struct intel_plane_state *plane_state,
 				     enum plane_id plane_id, int color_plane)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
+	u16 ddb_blocks = skl_ddb_entry_size(&crtc_state->wm.skl.plane_ddb_y[plane_id]);
 	struct skl_wm_params wm_params;
-	enum pipe pipe = plane->pipe;
-	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
 	int ret;
 
 	ret = skl_compute_plane_wm_params(crtc_state, plane_state,
@@ -5005,16 +5003,13 @@ static int skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
 	return 0;
 }
 
-static int skl_build_plane_wm_uv(struct skl_ddb_allocation *ddb,
-				 struct intel_crtc_state *crtc_state,
+static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
 				 const struct intel_plane_state *plane_state,
 				 enum plane_id plane_id)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
+	u16 ddb_blocks = skl_ddb_entry_size(&crtc_state->wm.skl.plane_ddb_uv[plane_id]);
 	struct skl_wm_params wm_params;
-	enum pipe pipe = plane->pipe;
-	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->uv_plane[pipe][plane_id]);
 	int ret;
 
 	wm->is_planar = true;
@@ -5033,8 +5028,7 @@ static int skl_build_plane_wm_uv(struct skl_ddb_allocation *ddb,
 	return 0;
 }
 
-static int skl_build_plane_wm(struct skl_ddb_allocation *ddb,
-			      struct skl_pipe_wm *pipe_wm,
+static int skl_build_plane_wm(struct skl_pipe_wm *pipe_wm,
 			      struct intel_crtc_state *crtc_state,
 			      const struct intel_plane_state *plane_state)
 {
@@ -5046,13 +5040,13 @@ static int skl_build_plane_wm(struct skl_ddb_allocation *ddb,
 	if (!intel_wm_plane_visible(crtc_state, plane_state))
 		return 0;
 
-	ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
+	ret = skl_build_plane_wm_single(crtc_state, plane_state,
 					plane_id, 0);
 	if (ret)
 		return ret;
 
 	if (fb->format->is_yuv && fb->format->num_planes > 1) {
-		ret = skl_build_plane_wm_uv(ddb, crtc_state, plane_state,
+		ret = skl_build_plane_wm_uv(crtc_state, plane_state,
 					    plane_id);
 		if (ret)
 			return ret;
@@ -5061,8 +5055,7 @@ static int skl_build_plane_wm(struct skl_ddb_allocation *ddb,
 	return 0;
 }
 
-static int icl_build_plane_wm(struct skl_ddb_allocation *ddb,
-			      struct skl_pipe_wm *pipe_wm,
+static int icl_build_plane_wm(struct skl_pipe_wm *pipe_wm,
 			      struct intel_crtc_state *crtc_state,
 			      const struct intel_plane_state *plane_state)
 {
@@ -5080,17 +5073,17 @@ static int icl_build_plane_wm(struct skl_ddb_allocation *ddb,
 		WARN_ON(!fb->format->is_yuv ||
 			fb->format->num_planes == 1);
 
-		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
+		ret = skl_build_plane_wm_single(crtc_state, plane_state,
 						y_plane_id, 0);
 		if (ret)
 			return ret;
 
-		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
+		ret = skl_build_plane_wm_single(crtc_state, plane_state,
 						plane_id, 1);
 		if (ret)
 			return ret;
 	} else if (intel_wm_plane_visible(crtc_state, plane_state)) {
-		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
+		ret = skl_build_plane_wm_single(crtc_state, plane_state,
 						plane_id, 0);
 		if (ret)
 			return ret;
@@ -5100,7 +5093,6 @@ static int icl_build_plane_wm(struct skl_ddb_allocation *ddb,
 }
 
 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
-			     struct skl_ddb_allocation *ddb,
 			     struct skl_pipe_wm *pipe_wm)
 {
 	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
@@ -5120,10 +5112,10 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
 						to_intel_plane_state(pstate);
 
 		if (INTEL_GEN(dev_priv) >= 11)
-			ret = icl_build_plane_wm(ddb, pipe_wm,
+			ret = icl_build_plane_wm(pipe_wm,
 						 cstate, intel_pstate);
 		else
-			ret = skl_build_plane_wm(ddb, pipe_wm,
+			ret = skl_build_plane_wm(pipe_wm,
 						 cstate, intel_pstate);
 		if (ret)
 			return ret;
@@ -5139,9 +5131,9 @@ static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
 				const struct skl_ddb_entry *entry)
 {
 	if (entry->end)
-		I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
+		I915_WRITE_FW(reg, (entry->end - 1) << 16 | entry->start);
 	else
-		I915_WRITE(reg, 0);
+		I915_WRITE_FW(reg, 0);
 }
 
 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
@@ -5156,19 +5148,22 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv,
 		val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
 	}
 
-	I915_WRITE(reg, val);
+	I915_WRITE_FW(reg, val);
 }
 
-static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
-			       const struct skl_plane_wm *wm,
-			       const struct skl_ddb_allocation *ddb,
-			       enum plane_id plane_id)
+void skl_write_plane_wm(struct intel_plane *plane,
+			const struct intel_crtc_state *crtc_state)
 {
-	struct drm_crtc *crtc = &intel_crtc->base;
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	int level, max_level = ilk_wm_max_level(dev_priv);
-	enum pipe pipe = intel_crtc->pipe;
+	enum plane_id plane_id = plane->id;
+	enum pipe pipe = plane->pipe;
+	const struct skl_plane_wm *wm =
+		&crtc_state->wm.skl.optimal.planes[plane_id];
+	const struct skl_ddb_entry *ddb_y =
+		&crtc_state->wm.skl.plane_ddb_y[plane_id];
+	const struct skl_ddb_entry *ddb_uv =
+		&crtc_state->wm.skl.plane_ddb_uv[plane_id];
 
 	for (level = 0; level <= max_level; level++) {
 		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
@@ -5177,29 +5172,32 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
 	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
 			   &wm->trans_wm);
 
-	if (wm->is_planar && INTEL_GEN(dev_priv) < 11) {
-		skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
-				    &ddb->uv_plane[pipe][plane_id]);
+	if (INTEL_GEN(dev_priv) >= 11) {
 		skl_ddb_entry_write(dev_priv,
-				    PLANE_NV12_BUF_CFG(pipe, plane_id),
-				    &ddb->plane[pipe][plane_id]);
-	} else {
-		skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
-				    &ddb->plane[pipe][plane_id]);
-		if (INTEL_GEN(dev_priv) < 11)
-			I915_WRITE(PLANE_NV12_BUF_CFG(pipe, plane_id), 0x0);
+				    PLANE_BUF_CFG(pipe, plane_id), ddb_y);
+		return;
 	}
+
+	if (wm->is_planar)
+		swap(ddb_y, ddb_uv);
+
+	skl_ddb_entry_write(dev_priv,
+			    PLANE_BUF_CFG(pipe, plane_id), ddb_y);
+	skl_ddb_entry_write(dev_priv,
+			    PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_uv);
 }
 
-static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
-				const struct skl_plane_wm *wm,
-				const struct skl_ddb_allocation *ddb)
+void skl_write_cursor_wm(struct intel_plane *plane,
+			 const struct intel_crtc_state *crtc_state)
 {
-	struct drm_crtc *crtc = &intel_crtc->base;
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	int level, max_level = ilk_wm_max_level(dev_priv);
-	enum pipe pipe = intel_crtc->pipe;
+	enum plane_id plane_id = plane->id;
+	enum pipe pipe = plane->pipe;
+	const struct skl_plane_wm *wm =
+		&crtc_state->wm.skl.optimal.planes[plane_id];
+	const struct skl_ddb_entry *ddb =
+		&crtc_state->wm.skl.plane_ddb_y[plane_id];
 
 	for (level = 0; level <= max_level; level++) {
 		skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
@@ -5207,22 +5205,30 @@ static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
 	}
 	skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
 
-	skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
-			    &ddb->plane[pipe][PLANE_CURSOR]);
+	skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), ddb);
 }
 
 bool skl_wm_level_equals(const struct skl_wm_level *l1,
 			 const struct skl_wm_level *l2)
 {
-	if (l1->plane_en != l2->plane_en)
-		return false;
+	return l1->plane_en == l2->plane_en &&
+		l1->plane_res_l == l2->plane_res_l &&
+		l1->plane_res_b == l2->plane_res_b;
+}
 
-	/* If both planes aren't enabled, the rest shouldn't matter */
-	if (!l1->plane_en)
-		return true;
+static bool skl_plane_wm_equals(struct drm_i915_private *dev_priv,
+				const struct skl_plane_wm *wm1,
+				const struct skl_plane_wm *wm2)
+{
+	int level, max_level = ilk_wm_max_level(dev_priv);
 
-	return (l1->plane_res_l == l2->plane_res_l &&
-		l1->plane_res_b == l2->plane_res_b);
+	for (level = 0; level <= max_level; level++) {
+		if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level]) ||
+		    !skl_wm_level_equals(&wm1->uv_wm[level], &wm2->uv_wm[level]))
+			return false;
+	}
+
+	return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm);
 }
 
 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
@@ -5249,13 +5255,12 @@ bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
 			      const struct skl_pipe_wm *old_pipe_wm,
 			      struct skl_pipe_wm *pipe_wm, /* out */
-			      struct skl_ddb_allocation *ddb, /* out */
 			      bool *changed /* out */)
 {
 	struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
 	int ret;
 
-	ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
+	ret = skl_build_pipe_wm(intel_cstate, pipe_wm);
 	if (ret)
 		return ret;
 
@@ -5281,42 +5286,29 @@ pipes_modified(struct drm_atomic_state *state)
 }
 
 static int
-skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
+skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
+			    struct intel_crtc_state *new_crtc_state)
 {
-	struct drm_atomic_state *state = cstate->base.state;
-	struct drm_device *dev = state->dev;
-	struct drm_crtc *crtc = cstate->base.crtc;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-	struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
-	struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
-	struct drm_plane *plane;
-	enum pipe pipe = intel_crtc->pipe;
+	struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->base.state);
+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_plane *plane;
 
-	drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
-		struct drm_plane_state *plane_state;
-		struct intel_plane *linked;
-		enum plane_id plane_id = to_intel_plane(plane)->id;
+	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+		struct intel_plane_state *plane_state;
+		enum plane_id plane_id = plane->id;
 
-		if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
-					&new_ddb->plane[pipe][plane_id]) &&
-		    skl_ddb_entry_equal(&cur_ddb->uv_plane[pipe][plane_id],
-					&new_ddb->uv_plane[pipe][plane_id]))
+		if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
+					&new_crtc_state->wm.skl.plane_ddb_y[plane_id]) &&
+		    skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_uv[plane_id],
+					&new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
 			continue;
 
-		plane_state = drm_atomic_get_plane_state(state, plane);
+		plane_state = intel_atomic_get_plane_state(state, plane);
 		if (IS_ERR(plane_state))
 			return PTR_ERR(plane_state);
 
-		/* Make sure linked plane is updated too */
-		linked = to_intel_plane_state(plane_state)->linked_plane;
-		if (!linked)
-			continue;
-
-		plane_state = drm_atomic_get_plane_state(state, &linked->base);
-		if (IS_ERR(plane_state))
-			return PTR_ERR(plane_state);
+		new_crtc_state->update_planes |= BIT(plane_id);
 	}
 
 	return 0;
@@ -5328,18 +5320,21 @@ skl_compute_ddb(struct drm_atomic_state *state)
 	const struct drm_i915_private *dev_priv = to_i915(state->dev);
 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
 	struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
+	struct intel_crtc_state *old_crtc_state;
+	struct intel_crtc_state *new_crtc_state;
 	struct intel_crtc *crtc;
-	struct intel_crtc_state *cstate;
 	int ret, i;
 
 	memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
 
-	for_each_new_intel_crtc_in_state(intel_state, crtc, cstate, i) {
-		ret = skl_allocate_pipe_ddb(cstate, ddb);
+	for_each_oldnew_intel_crtc_in_state(intel_state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		ret = skl_allocate_pipe_ddb(new_crtc_state, ddb);
 		if (ret)
 			return ret;
 
-		ret = skl_ddb_add_affected_planes(cstate);
+		ret = skl_ddb_add_affected_planes(old_crtc_state,
+						  new_crtc_state);
 		if (ret)
 			return ret;
 	}
@@ -5348,36 +5343,29 @@ skl_compute_ddb(struct drm_atomic_state *state)
 }
 
 static void
-skl_print_wm_changes(const struct drm_atomic_state *state)
+skl_print_wm_changes(struct intel_atomic_state *state)
 {
-	const struct drm_device *dev = state->dev;
-	const struct drm_i915_private *dev_priv = to_i915(dev);
-	const struct intel_atomic_state *intel_state =
-		to_intel_atomic_state(state);
-	const struct drm_crtc *crtc;
-	const struct drm_crtc_state *cstate;
-	const struct intel_plane *intel_plane;
-	const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
-	const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	const struct intel_crtc_state *old_crtc_state;
+	const struct intel_crtc_state *new_crtc_state;
+	struct intel_plane *plane;
+	struct intel_crtc *crtc;
 	int i;
 
-	for_each_new_crtc_in_state(state, crtc, cstate, i) {
-		const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-		enum pipe pipe = intel_crtc->pipe;
-
-		for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
-			enum plane_id plane_id = intel_plane->id;
+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+			enum plane_id plane_id = plane->id;
 			const struct skl_ddb_entry *old, *new;
 
-			old = &old_ddb->plane[pipe][plane_id];
-			new = &new_ddb->plane[pipe][plane_id];
+			old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];
+			new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];
 
 			if (skl_ddb_entry_equal(old, new))
 				continue;
 
 			DRM_DEBUG_KMS("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
-				      intel_plane->base.base.id,
-				      intel_plane->base.name,
+				      plane->base.base.id, plane->base.name,
 				      old->start, old->end,
 				      new->start, new->end);
 		}
@@ -5474,6 +5462,66 @@ skl_ddb_add_affected_pipes(struct drm_atomic_state *state, bool *changed)
 	return 0;
 }
 
+/*
+ * To make sure the cursor watermark registers are always consistent
+ * with our computed state the following scenario needs special
+ * treatment:
+ *
+ * 1. enable cursor
+ * 2. move cursor entirely offscreen
+ * 3. disable cursor
+ *
+ * Step 2. does call .disable_plane() but does not zero the watermarks
+ * (since we consider an offscreen cursor still active for the purposes
+ * of watermarks). Step 3. would not normally call .disable_plane()
+ * because the actual plane visibility isn't changing, and we don't
+ * deallocate the cursor ddb until the pipe gets disabled. So we must
+ * force step 3. to call .disable_plane() to update the watermark
+ * registers properly.
+ *
+ * Other planes do not suffer from this issues as their watermarks are
+ * calculated based on the actual plane visibility. The only time this
+ * can trigger for the other planes is during the initial readout as the
+ * default value of the watermarks registers is not zero.
+ */
+static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
+				      struct intel_crtc *crtc)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct intel_crtc_state *old_crtc_state =
+		intel_atomic_get_old_crtc_state(state, crtc);
+	struct intel_crtc_state *new_crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	struct intel_plane *plane;
+
+	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+		struct intel_plane_state *plane_state;
+		enum plane_id plane_id = plane->id;
+
+		/*
+		 * Force a full wm update for every plane on modeset.
+		 * Required because the reset value of the wm registers
+		 * is non-zero, whereas we want all disabled planes to
+		 * have zero watermarks. So if we turn off the relevant
+		 * power well the hardware state will go out of sync
+		 * with the software state.
+		 */
+		if (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) &&
+		    skl_plane_wm_equals(dev_priv,
+					&old_crtc_state->wm.skl.optimal.planes[plane_id],
+					&new_crtc_state->wm.skl.optimal.planes[plane_id]))
+			continue;
+
+		plane_state = intel_atomic_get_plane_state(state, plane);
+		if (IS_ERR(plane_state))
+			return PTR_ERR(plane_state);
+
+		new_crtc_state->update_planes |= BIT(plane_id);
+	}
+
+	return 0;
+}
+
 static int
 skl_compute_wm(struct drm_atomic_state *state)
 {
@@ -5513,8 +5561,12 @@ skl_compute_wm(struct drm_atomic_state *state)
 			&to_intel_crtc_state(crtc->state)->wm.skl.optimal;
 
 		pipe_wm = &intel_cstate->wm.skl.optimal;
-		ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
-					 &results->ddb, &changed);
+		ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm, &changed);
+		if (ret)
+			return ret;
+
+		ret = skl_wm_add_affected_planes(intel_state,
+						 to_intel_crtc(crtc));
 		if (ret)
 			return ret;
 
@@ -5528,7 +5580,7 @@ skl_compute_wm(struct drm_atomic_state *state)
 		intel_cstate->update_wm_pre = true;
 	}
 
-	skl_print_wm_changes(state);
+	skl_print_wm_changes(intel_state);
 
 	return 0;
 }
@@ -5539,23 +5591,12 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
 	struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
-	const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
 	enum pipe pipe = crtc->pipe;
-	enum plane_id plane_id;
 
 	if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
 		return;
 
 	I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
-
-	for_each_plane_id_on_crtc(crtc, plane_id) {
-		if (plane_id != PLANE_CURSOR)
-			skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id],
-					   ddb, plane_id);
-		else
-			skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id],
-					    ddb);
-	}
 }
 
 static void skl_initial_wm(struct intel_atomic_state *state,
@@ -5565,8 +5606,6 @@ static void skl_initial_wm(struct intel_atomic_state *state,
 	struct drm_device *dev = intel_crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct skl_ddb_values *results = &state->wm_results;
-	struct skl_ddb_values *hw_vals = &dev_priv->wm.skl_hw;
-	enum pipe pipe = intel_crtc->pipe;
 
 	if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
 		return;
@@ -5576,11 +5615,6 @@ static void skl_initial_wm(struct intel_atomic_state *state,
 	if (cstate->base.active_changed)
 		skl_atomic_update_crtc_wm(state, cstate);
 
-	memcpy(hw_vals->ddb.uv_plane[pipe], results->ddb.uv_plane[pipe],
-	       sizeof(hw_vals->ddb.uv_plane[pipe]));
-	memcpy(hw_vals->ddb.plane[pipe], results->ddb.plane[pipe],
-	       sizeof(hw_vals->ddb.plane[pipe]));
-
 	mutex_unlock(&dev_priv->wm.wm_mutex);
 }
 
@@ -5731,13 +5765,6 @@ void skl_wm_get_hw_state(struct drm_device *dev)
 	if (dev_priv->active_crtcs) {
 		/* Fully recompute DDB on first atomic commit */
 		dev_priv->wm.distrust_bios_wm = true;
-	} else {
-		/*
-		 * Easy/common case; just sanitize DDB now if everything off
-		 * Keep dbuf slice info intact
-		 */
-		memset(ddb->plane, 0, sizeof(ddb->plane));
-		memset(ddb->uv_plane, 0, sizeof(ddb->uv_plane));
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index e5da2fe3bdae..32df604e90b6 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -542,6 +542,8 @@ skl_program_plane(struct intel_plane *plane,
 	if (fb->format->is_yuv && icl_is_hdr_plane(plane))
 		icl_program_input_csc_coeff(crtc_state, plane_state);
 
+	skl_write_plane_wm(plane, crtc_state);
+
 	I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
 	I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk);
 	I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax);
@@ -604,6 +606,8 @@ skl_disable_plane(struct intel_plane *plane,
 
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
+	skl_write_plane_wm(plane, crtc_state);
+
 	I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
 	I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
 
-- 
2.18.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 10/13] drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+

[Matt Roper]

On Wed, Nov 14, 2018 at 11:07:26PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On SKL+ the plane WM/BUF_CFG registers are a proper part of each
> plane's register set. That means accessing them will cancel any
> pending plane update, and we would need a PLANE_SURF register write
> to arm the wm/ddb change as well.
> 
> To avoid all the problems with that let's just move the wm/ddb
> programming into the plane update/disable hooks. Now all plane
> registers get written in one (hopefully atomic) operation.
> 
> To make that feasible we'll move the plane ddb tracking into
> the crtc state. Watermarks were already tracked there.
> 
> v2: Rebase due to input CSC
> v3: Split out a bunch of junk (Matt)
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c  |  21 +-
>  drivers/gpu/drm/i915/i915_drv.h      |   3 -
>  drivers/gpu/drm/i915/intel_display.c |  16 +-
>  drivers/gpu/drm/i915/intel_display.h |  11 +-
>  drivers/gpu/drm/i915/intel_drv.h     |   9 +
>  drivers/gpu/drm/i915/intel_pm.c      | 317 ++++++++++++---------------
>  drivers/gpu/drm/i915/intel_sprite.c  |   4 +
>  7 files changed, 181 insertions(+), 200 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 670db5073d70..f8b2200947cf 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3437,31 +3437,32 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
>  {
>  	struct drm_i915_private *dev_priv = node_to_i915(m->private);
>  	struct drm_device *dev = &dev_priv->drm;
> -	struct skl_ddb_allocation *ddb;
>  	struct skl_ddb_entry *entry;
> -	enum pipe pipe;
> -	int plane;
> +	struct intel_crtc *crtc;
>  
>  	if (INTEL_GEN(dev_priv) < 9)
>  		return -ENODEV;
>  
>  	drm_modeset_lock_all(dev);
>  
> -	ddb = &dev_priv->wm.skl_hw.ddb;
> -
>  	seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
>  
> -	for_each_pipe(dev_priv, pipe) {
> +	for_each_intel_crtc(&dev_priv->drm, crtc) {
> +		struct intel_crtc_state *crtc_state =
> +			to_intel_crtc_state(crtc->base.state);
> +		enum pipe pipe = crtc->pipe;
> +		enum plane_id plane_id;
> +
>  		seq_printf(m, "Pipe %c\n", pipe_name(pipe));
>  
> -		for_each_universal_plane(dev_priv, pipe, plane) {
> -			entry = &ddb->plane[pipe][plane];
> -			seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
> +		for_each_plane_id_on_crtc(crtc, plane_id) {
> +			entry = &crtc_state->wm.skl.plane_ddb_y[plane_id];
> +			seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane_id + 1,
>  				   entry->start, entry->end,
>  				   skl_ddb_entry_size(entry));
>  		}
>  
> -		entry = &ddb->plane[pipe][PLANE_CURSOR];
> +		entry = &crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
>  		seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
>  			   entry->end, skl_ddb_entry_size(entry));
>  	}
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5d686b585a95..89af64fe90a5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1241,9 +1241,6 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
>  }
>  
>  struct skl_ddb_allocation {
> -	/* packed/y */
> -	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
> -	struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
>  	u8 enabled_slices; /* GEN11 has configurable 2 slices */
>  };
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0caba7258fee..2981cea3704a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10083,6 +10083,10 @@ static void i9xx_update_cursor(struct intel_plane *plane,
>  	 * except when the plane is getting enabled at which time
>  	 * the CURCNTR write arms the update.
>  	 */
> +
> +	if (INTEL_GEN(dev_priv) >= 9)
> +		skl_write_cursor_wm(plane, crtc_state);
> +
>  	if (plane->cursor.base != base ||
>  	    plane->cursor.size != fbc_ctl ||
>  	    plane->cursor.cntl != cntl) {
> @@ -11872,6 +11876,8 @@ static void verify_wm_state(struct drm_crtc *crtc,
>  	struct skl_pipe_wm hw_wm, *sw_wm;
>  	struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
>  	struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
> +	struct skl_ddb_entry hw_ddb_y[I915_MAX_PLANES];
> +	struct skl_ddb_entry hw_ddb_uv[I915_MAX_PLANES];
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	const enum pipe pipe = intel_crtc->pipe;
>  	int plane, level, max_level = ilk_wm_max_level(dev_priv);
> @@ -11882,6 +11888,8 @@ static void verify_wm_state(struct drm_crtc *crtc,
>  	skl_pipe_wm_get_hw_state(crtc, &hw_wm);
>  	sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
>  
> +	skl_pipe_ddb_get_hw_state(intel_crtc, hw_ddb_y, hw_ddb_uv);
> +
>  	skl_ddb_get_hw_state(dev_priv, &hw_ddb);
>  	sw_ddb = &dev_priv->wm.skl_hw.ddb;
>  
> @@ -11924,8 +11932,8 @@ static void verify_wm_state(struct drm_crtc *crtc,
>  		}
>  
>  		/* DDB */
> -		hw_ddb_entry = &hw_ddb.plane[pipe][plane];
> -		sw_ddb_entry = &sw_ddb->plane[pipe][plane];
> +		hw_ddb_entry = &hw_ddb_y[plane];
> +		sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[plane];
>  
>  		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
>  			DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
> @@ -11974,8 +11982,8 @@ static void verify_wm_state(struct drm_crtc *crtc,
>  		}
>  
>  		/* DDB */
> -		hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
> -		sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
> +		hw_ddb_entry = &hw_ddb_y[PLANE_CURSOR];
> +		sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[PLANE_CURSOR];
>  
>  		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
>  			DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
> diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
> index df9e6ebb27de..078406dc65e5 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -319,7 +319,7 @@ struct intel_link_m_n {
>  			    &(dev)->mode_config.plane_list,		\
>  			    base.head)					\
>  		for_each_if((plane_mask) &				\
> -			    drm_plane_mask(&intel_plane->base)))
> +			    drm_plane_mask(&intel_plane->base))
>  
>  #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
>  	list_for_each_entry(intel_plane,				\
> @@ -415,6 +415,15 @@ struct intel_link_m_n {
>  	     (__i)++) \
>  		for_each_if(plane)
>  
> +#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
> +	for ((__i) = 0; \
> +	     (__i) < (__state)->base.dev->mode_config.num_crtc && \
> +		     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
> +		      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
> +		      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
> +	     (__i)++) \
> +		for_each_if(crtc)
> +
>  void intel_link_compute_m_n(int bpp, int nlanes,
>  			    int pixel_clock, int link_clock,
>  			    struct intel_link_m_n *m_n,
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 23b33970db17..4a9af09c483a 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -705,6 +705,8 @@ struct intel_crtc_wm_state {
>  			/* gen9+ only needs 1-step wm programming */
>  			struct skl_pipe_wm optimal;
>  			struct skl_ddb_entry ddb;
> +			struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
> +			struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];

I feel like naming these _y and _uv is going to cause confusion.  The Y
and UV are backwards half the time (based on the swap we have to do
farther down), and doesn't have meaning at all for RGB.  Maybe name
these something like "plane_ddb_main" and "plane_ddb_extra" to somewhat
disassociate it with the actual type of data it's supposed to represent?

If you want to keep the _y and _uv (which are nice and short), I think
we at least need some warning comments here explaining the behavior.

>  		} skl;
>  
>  		struct {
> @@ -2183,6 +2185,9 @@ void g4x_wm_get_hw_state(struct drm_device *dev);
>  void vlv_wm_get_hw_state(struct drm_device *dev);
>  void ilk_wm_get_hw_state(struct drm_device *dev);
>  void skl_wm_get_hw_state(struct drm_device *dev);
> +void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
> +			       struct skl_ddb_entry *ddb_y,
> +			       struct skl_ddb_entry *ddb_uv);
>  void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
>  			  struct skl_ddb_allocation *ddb /* out */);
>  void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
> @@ -2197,6 +2202,10 @@ bool skl_wm_level_equals(const struct skl_wm_level *l1,
>  bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
>  				 const struct skl_ddb_entry entries[],
>  				 int num_entries, int ignore_idx);
> +void skl_write_plane_wm(struct intel_plane *plane,
> +			const struct intel_crtc_state *crtc_state);
> +void skl_write_cursor_wm(struct intel_plane *plane,
> +			 const struct intel_crtc_state *crtc_state);
>  bool ilk_disable_lp_wm(struct drm_device *dev);
>  int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
>  				  struct intel_crtc_state *cstate);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a21654c974ba..1b337004054a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3912,68 +3912,70 @@ static void
>  skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
>  			   const enum pipe pipe,
>  			   const enum plane_id plane_id,
> -			   struct skl_ddb_allocation *ddb /* out */)
> +			   struct skl_ddb_entry *ddb_y,
> +			   struct skl_ddb_entry *ddb_uv)
>  {
> -	u32 val, val2 = 0;
> -	int fourcc, pixel_format;
> +	u32 val, val2;
> +	u32 fourcc = 0;
>  
>  	/* Cursor doesn't support NV12/planar, so no extra calculation needed */
>  	if (plane_id == PLANE_CURSOR) {
>  		val = I915_READ(CUR_BUF_CFG(pipe));
> -		skl_ddb_entry_init_from_hw(dev_priv,
> -					   &ddb->plane[pipe][plane_id], val);
> +		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
>  		return;
>  	}
>  
>  	val = I915_READ(PLANE_CTL(pipe, plane_id));
>  
>  	/* No DDB allocated for disabled planes */
> -	if (!(val & PLANE_CTL_ENABLE))
> -		return;

I think we should mention the readout behavior change in the commit
message (i.e., we now read out DDB even if we think the plane is
disabled).  Either that or move the behavior change to a separate patch.

We should also drop the comment line since I don't think it really makes
sense anymore.

> +	if (val & PLANE_CTL_ENABLE)
> +		fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK,
> +					      val & PLANE_CTL_ORDER_RGBX,
> +					      val & PLANE_CTL_ALPHA_MASK);
>  
> -	pixel_format = val & PLANE_CTL_FORMAT_MASK;
> -	fourcc = skl_format_to_fourcc(pixel_format,
> -				      val & PLANE_CTL_ORDER_RGBX,
> -				      val & PLANE_CTL_ALPHA_MASK);
> -
> -	val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
> -	if (fourcc == DRM_FORMAT_NV12 && INTEL_GEN(dev_priv) < 11) {
> +	if (INTEL_GEN(dev_priv) >= 11) {
> +		val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
> +		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
> +	} else {
> +		val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
>  		val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
>  
> -		skl_ddb_entry_init_from_hw(dev_priv,
> -					   &ddb->plane[pipe][plane_id], val2);
> -		skl_ddb_entry_init_from_hw(dev_priv,
> -					   &ddb->uv_plane[pipe][plane_id], val);
> -	} else {
> -		skl_ddb_entry_init_from_hw(dev_priv,
> -					   &ddb->plane[pipe][plane_id], val);
> +		if (fourcc == DRM_FORMAT_NV12)
> +			swap(val, val2);
> +
> +		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
> +		skl_ddb_entry_init_from_hw(dev_priv, ddb_uv, val2);
>  	}
>  }
>  
> +void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
> +			       struct skl_ddb_entry *ddb_y,
> +			       struct skl_ddb_entry *ddb_uv)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	enum intel_display_power_domain power_domain;
> +	enum pipe pipe = crtc->pipe;
> +	enum plane_id plane_id;
> +
> +	power_domain = POWER_DOMAIN_PIPE(pipe);
> +	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
> +		return;
> +
> +	for_each_plane_id_on_crtc(crtc, plane_id)
> +		skl_ddb_get_hw_plane_state(dev_priv, pipe,
> +					   plane_id,
> +					   &ddb_y[plane_id],
> +					   &ddb_uv[plane_id]);
> +
> +	intel_display_power_put(dev_priv, power_domain);
> +}
> +
>  void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
>  			  struct skl_ddb_allocation *ddb /* out */)
>  {
> -	struct intel_crtc *crtc;
> -
>  	memset(ddb, 0, sizeof(*ddb));

We can drop the memset.  The entire structure is only 1 byte now, and we
set its only remaining field on the next line.

>  
>  	ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
> -
> -	for_each_intel_crtc(&dev_priv->drm, crtc) {
> -		enum intel_display_power_domain power_domain;
> -		enum plane_id plane_id;
> -		enum pipe pipe = crtc->pipe;
> -
> -		power_domain = POWER_DOMAIN_PIPE(pipe);
> -		if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
> -			continue;
> -
> -		for_each_plane_id_on_crtc(crtc, plane_id)
> -			skl_ddb_get_hw_plane_state(dev_priv, pipe,
> -						   plane_id, ddb);
> -
> -		intel_display_power_put(dev_priv, power_domain);
> -	}
>  }
>  
>  /*
> @@ -4371,7 +4373,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
>  	struct drm_crtc *crtc = cstate->base.crtc;
>  	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	enum pipe pipe = intel_crtc->pipe;
>  	struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
>  	uint16_t alloc_size, start;
>  	uint16_t minimum[I915_MAX_PLANES] = {};
> @@ -4384,8 +4385,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
>  	uint16_t total_min_blocks = 0;
>  
>  	/* Clear the partitioning for disabled planes. */
> -	memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
> -	memset(ddb->uv_plane[pipe], 0, sizeof(ddb->uv_plane[pipe]));
> +	memset(cstate->wm.skl.plane_ddb_y, 0, sizeof(cstate->wm.skl.plane_ddb_y));
> +	memset(cstate->wm.skl.plane_ddb_uv, 0, sizeof(cstate->wm.skl.plane_ddb_uv));
>  
>  	if (WARN_ON(!state))
>  		return 0;
> @@ -4432,8 +4433,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
>  	}
>  
>  	alloc_size -= total_min_blocks;
> -	ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
> -	ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
> +	cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
> +	cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
>  
>  	/*
>  	 * 2. Distribute the remaining space in proportion to the amount of
> @@ -4464,8 +4465,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
>  
>  		/* Leave disabled planes at (0,0) */
>  		if (data_rate) {
> -			ddb->plane[pipe][plane_id].start = start;
> -			ddb->plane[pipe][plane_id].end = start + plane_blocks;
> +			cstate->wm.skl.plane_ddb_y[plane_id].start = start;
> +			cstate->wm.skl.plane_ddb_y[plane_id].end = start + plane_blocks;
>  		}
>  
>  		start += plane_blocks;
> @@ -4480,8 +4481,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
>  		WARN_ON(INTEL_GEN(dev_priv) >= 11 && uv_plane_blocks);
>  
>  		if (uv_data_rate) {
> -			ddb->uv_plane[pipe][plane_id].start = start;
> -			ddb->uv_plane[pipe][plane_id].end =
> +			cstate->wm.skl.plane_ddb_uv[plane_id].start = start;
> +			cstate->wm.skl.plane_ddb_uv[plane_id].end =
>  				start + uv_plane_blocks;
>  		}
>  
> @@ -4939,16 +4940,13 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
>  	}
>  }
>  
> -static int skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
> -				     struct intel_crtc_state *crtc_state,
> +static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
>  				     const struct intel_plane_state *plane_state,
>  				     enum plane_id plane_id, int color_plane)
>  {
> -	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>  	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
> +	u16 ddb_blocks = skl_ddb_entry_size(&crtc_state->wm.skl.plane_ddb_y[plane_id]);
>  	struct skl_wm_params wm_params;
> -	enum pipe pipe = plane->pipe;
> -	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
>  	int ret;
>  
>  	ret = skl_compute_plane_wm_params(crtc_state, plane_state,
> @@ -4966,16 +4964,13 @@ static int skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
>  	return 0;
>  }
>  
> -static int skl_build_plane_wm_uv(struct skl_ddb_allocation *ddb,
> -				 struct intel_crtc_state *crtc_state,
> +static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
>  				 const struct intel_plane_state *plane_state,
>  				 enum plane_id plane_id)
>  {
> -	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>  	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
> +	u16 ddb_blocks = skl_ddb_entry_size(&crtc_state->wm.skl.plane_ddb_uv[plane_id]);
>  	struct skl_wm_params wm_params;
> -	enum pipe pipe = plane->pipe;
> -	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->uv_plane[pipe][plane_id]);
>  	int ret;
>  
>  	wm->is_planar = true;
> @@ -4994,8 +4989,7 @@ static int skl_build_plane_wm_uv(struct skl_ddb_allocation *ddb,
>  	return 0;
>  }
>  
> -static int skl_build_plane_wm(struct skl_ddb_allocation *ddb,
> -			      struct skl_pipe_wm *pipe_wm,
> +static int skl_build_plane_wm(struct skl_pipe_wm *pipe_wm,
>  			      struct intel_crtc_state *crtc_state,
>  			      const struct intel_plane_state *plane_state)
>  {
> @@ -5007,13 +5001,13 @@ static int skl_build_plane_wm(struct skl_ddb_allocation *ddb,
>  	if (!intel_wm_plane_visible(crtc_state, plane_state))
>  		return 0;
>  
> -	ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
> +	ret = skl_build_plane_wm_single(crtc_state, plane_state,
>  					plane_id, 0);
>  	if (ret)
>  		return ret;
>  
>  	if (fb->format->is_yuv && fb->format->num_planes > 1) {
> -		ret = skl_build_plane_wm_uv(ddb, crtc_state, plane_state,
> +		ret = skl_build_plane_wm_uv(crtc_state, plane_state,
>  					    plane_id);
>  		if (ret)
>  			return ret;
> @@ -5022,8 +5016,7 @@ static int skl_build_plane_wm(struct skl_ddb_allocation *ddb,
>  	return 0;
>  }
>  
> -static int icl_build_plane_wm(struct skl_ddb_allocation *ddb,
> -			      struct skl_pipe_wm *pipe_wm,
> +static int icl_build_plane_wm(struct skl_pipe_wm *pipe_wm,
>  			      struct intel_crtc_state *crtc_state,
>  			      const struct intel_plane_state *plane_state)
>  {
> @@ -5041,17 +5034,17 @@ static int icl_build_plane_wm(struct skl_ddb_allocation *ddb,
>  		WARN_ON(!fb->format->is_yuv ||
>  			fb->format->num_planes == 1);
>  
> -		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
> +		ret = skl_build_plane_wm_single(crtc_state, plane_state,
>  						y_plane_id, 0);
>  		if (ret)
>  			return ret;
>  
> -		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
> +		ret = skl_build_plane_wm_single(crtc_state, plane_state,
>  						plane_id, 1);
>  		if (ret)
>  			return ret;
>  	} else if (intel_wm_plane_visible(crtc_state, plane_state)) {
> -		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
> +		ret = skl_build_plane_wm_single(crtc_state, plane_state,
>  						plane_id, 0);
>  		if (ret)
>  			return ret;
> @@ -5061,7 +5054,6 @@ static int icl_build_plane_wm(struct skl_ddb_allocation *ddb,
>  }
>  
>  static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
> -			     struct skl_ddb_allocation *ddb,
>  			     struct skl_pipe_wm *pipe_wm)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
> @@ -5081,10 +5073,10 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
>  						to_intel_plane_state(pstate);
>  
>  		if (INTEL_GEN(dev_priv) >= 11)
> -			ret = icl_build_plane_wm(ddb, pipe_wm,
> +			ret = icl_build_plane_wm(pipe_wm,
>  						 cstate, intel_pstate);
>  		else
> -			ret = skl_build_plane_wm(ddb, pipe_wm,
> +			ret = skl_build_plane_wm(pipe_wm,
>  						 cstate, intel_pstate);
>  		if (ret)
>  			return ret;
> @@ -5100,9 +5092,9 @@ static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
>  				const struct skl_ddb_entry *entry)
>  {
>  	if (entry->end)
> -		I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
> +		I915_WRITE_FW(reg, (entry->end - 1) << 16 | entry->start);
>  	else
> -		I915_WRITE(reg, 0);
> +		I915_WRITE_FW(reg, 0);
>  }
>  
>  static void skl_write_wm_level(struct drm_i915_private *dev_priv,
> @@ -5117,19 +5109,22 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv,
>  		val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
>  	}
>  
> -	I915_WRITE(reg, val);
> +	I915_WRITE_FW(reg, val);
>  }
>  
> -static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
> -			       const struct skl_plane_wm *wm,
> -			       const struct skl_ddb_allocation *ddb,
> -			       enum plane_id plane_id)
> +void skl_write_plane_wm(struct intel_plane *plane,
> +			const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_crtc *crtc = &intel_crtc->base;
> -	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	int level, max_level = ilk_wm_max_level(dev_priv);
> -	enum pipe pipe = intel_crtc->pipe;
> +	enum plane_id plane_id = plane->id;
> +	enum pipe pipe = plane->pipe;
> +	const struct skl_plane_wm *wm =
> +		&crtc_state->wm.skl.optimal.planes[plane_id];
> +	const struct skl_ddb_entry *ddb_y =
> +		&crtc_state->wm.skl.plane_ddb_y[plane_id];
> +	const struct skl_ddb_entry *ddb_uv =
> +		&crtc_state->wm.skl.plane_ddb_uv[plane_id];
>  
>  	for (level = 0; level <= max_level; level++) {
>  		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
> @@ -5138,29 +5133,32 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
>  	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
>  			   &wm->trans_wm);
>  
> -	if (wm->is_planar && INTEL_GEN(dev_priv) < 11) {
> -		skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
> -				    &ddb->uv_plane[pipe][plane_id]);
> +	if (INTEL_GEN(dev_priv) >= 11) {
>  		skl_ddb_entry_write(dev_priv,
> -				    PLANE_NV12_BUF_CFG(pipe, plane_id),
> -				    &ddb->plane[pipe][plane_id]);
> -	} else {
> -		skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
> -				    &ddb->plane[pipe][plane_id]);
> -		if (INTEL_GEN(dev_priv) < 11)
> -			I915_WRITE(PLANE_NV12_BUF_CFG(pipe, plane_id), 0x0);
> +				    PLANE_BUF_CFG(pipe, plane_id), ddb_y);
> +		return;
>  	}
> +
> +	if (wm->is_planar)
> +		swap(ddb_y, ddb_uv);

As noted above, I understand why this is, but it sure looks confusing at
a casual glance...


Matt

> +
> +	skl_ddb_entry_write(dev_priv,
> +			    PLANE_BUF_CFG(pipe, plane_id), ddb_y);
> +	skl_ddb_entry_write(dev_priv,
> +			    PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_uv);
>  }
>  
> -static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
> -				const struct skl_plane_wm *wm,
> -				const struct skl_ddb_allocation *ddb)
> +void skl_write_cursor_wm(struct intel_plane *plane,
> +			 const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_crtc *crtc = &intel_crtc->base;
> -	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	int level, max_level = ilk_wm_max_level(dev_priv);
> -	enum pipe pipe = intel_crtc->pipe;
> +	enum plane_id plane_id = plane->id;
> +	enum pipe pipe = plane->pipe;
> +	const struct skl_plane_wm *wm =
> +		&crtc_state->wm.skl.optimal.planes[plane_id];
> +	const struct skl_ddb_entry *ddb =
> +		&crtc_state->wm.skl.plane_ddb_y[plane_id];
>  
>  	for (level = 0; level <= max_level; level++) {
>  		skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
> @@ -5168,8 +5166,7 @@ static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
>  	}
>  	skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
>  
> -	skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
> -			    &ddb->plane[pipe][PLANE_CURSOR]);
> +	skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), ddb);
>  }
>  
>  bool skl_wm_level_equals(const struct skl_wm_level *l1,
> @@ -5210,13 +5207,12 @@ bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
>  static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
>  			      const struct skl_pipe_wm *old_pipe_wm,
>  			      struct skl_pipe_wm *pipe_wm, /* out */
> -			      struct skl_ddb_allocation *ddb, /* out */
>  			      bool *changed /* out */)
>  {
>  	struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
>  	int ret;
>  
> -	ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
> +	ret = skl_build_pipe_wm(intel_cstate, pipe_wm);
>  	if (ret)
>  		return ret;
>  
> @@ -5242,42 +5238,29 @@ pipes_modified(struct drm_atomic_state *state)
>  }
>  
>  static int
> -skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
> +skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
> +			    struct intel_crtc_state *new_crtc_state)
>  {
> -	struct drm_atomic_state *state = cstate->base.state;
> -	struct drm_device *dev = state->dev;
> -	struct drm_crtc *crtc = cstate->base.crtc;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> -	struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
> -	struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
> -	struct drm_plane *plane;
> -	enum pipe pipe = intel_crtc->pipe;
> +	struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->base.state);
> +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct intel_plane *plane;
>  
> -	drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
> -		struct drm_plane_state *plane_state;
> -		struct intel_plane *linked;
> -		enum plane_id plane_id = to_intel_plane(plane)->id;
> +	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> +		struct intel_plane_state *plane_state;
> +		enum plane_id plane_id = plane->id;
>  
> -		if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
> -					&new_ddb->plane[pipe][plane_id]) &&
> -		    skl_ddb_entry_equal(&cur_ddb->uv_plane[pipe][plane_id],
> -					&new_ddb->uv_plane[pipe][plane_id]))
> +		if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
> +					&new_crtc_state->wm.skl.plane_ddb_y[plane_id]) &&
> +		    skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_uv[plane_id],
> +					&new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
>  			continue;
>  
> -		plane_state = drm_atomic_get_plane_state(state, plane);
> +		plane_state = intel_atomic_get_plane_state(state, plane);
>  		if (IS_ERR(plane_state))
>  			return PTR_ERR(plane_state);
>  
> -		/* Make sure linked plane is updated too */
> -		linked = to_intel_plane_state(plane_state)->linked_plane;
> -		if (!linked)
> -			continue;
> -
> -		plane_state = drm_atomic_get_plane_state(state, &linked->base);
> -		if (IS_ERR(plane_state))
> -			return PTR_ERR(plane_state);
> +		new_crtc_state->update_planes |= BIT(plane_id);
>  	}
>  
>  	return 0;
> @@ -5289,18 +5272,21 @@ skl_compute_ddb(struct drm_atomic_state *state)
>  	const struct drm_i915_private *dev_priv = to_i915(state->dev);
>  	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
>  	struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
> +	struct intel_crtc_state *old_crtc_state;
> +	struct intel_crtc_state *new_crtc_state;
>  	struct intel_crtc *crtc;
> -	struct intel_crtc_state *cstate;
>  	int ret, i;
>  
>  	memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
>  
> -	for_each_new_intel_crtc_in_state(intel_state, crtc, cstate, i) {
> -		ret = skl_allocate_pipe_ddb(cstate, ddb);
> +	for_each_oldnew_intel_crtc_in_state(intel_state, crtc, old_crtc_state,
> +					    new_crtc_state, i) {
> +		ret = skl_allocate_pipe_ddb(new_crtc_state, ddb);
>  		if (ret)
>  			return ret;
>  
> -		ret = skl_ddb_add_affected_planes(cstate);
> +		ret = skl_ddb_add_affected_planes(old_crtc_state,
> +						  new_crtc_state);
>  		if (ret)
>  			return ret;
>  	}
> @@ -5309,36 +5295,29 @@ skl_compute_ddb(struct drm_atomic_state *state)
>  }
>  
>  static void
> -skl_print_wm_changes(const struct drm_atomic_state *state)
> +skl_print_wm_changes(struct intel_atomic_state *state)
>  {
> -	const struct drm_device *dev = state->dev;
> -	const struct drm_i915_private *dev_priv = to_i915(dev);
> -	const struct intel_atomic_state *intel_state =
> -		to_intel_atomic_state(state);
> -	const struct drm_crtc *crtc;
> -	const struct drm_crtc_state *cstate;
> -	const struct intel_plane *intel_plane;
> -	const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
> -	const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +	const struct intel_crtc_state *old_crtc_state;
> +	const struct intel_crtc_state *new_crtc_state;
> +	struct intel_plane *plane;
> +	struct intel_crtc *crtc;
>  	int i;
>  
> -	for_each_new_crtc_in_state(state, crtc, cstate, i) {
> -		const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -		enum pipe pipe = intel_crtc->pipe;
> -
> -		for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
> -			enum plane_id plane_id = intel_plane->id;
> +	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> +					    new_crtc_state, i) {
> +		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> +			enum plane_id plane_id = plane->id;
>  			const struct skl_ddb_entry *old, *new;
>  
> -			old = &old_ddb->plane[pipe][plane_id];
> -			new = &new_ddb->plane[pipe][plane_id];
> +			old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];
> +			new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];
>  
>  			if (skl_ddb_entry_equal(old, new))
>  				continue;
>  
>  			DRM_DEBUG_KMS("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
> -				      intel_plane->base.base.id,
> -				      intel_plane->base.name,
> +				      plane->base.base.id, plane->base.name,
>  				      old->start, old->end,
>  				      new->start, new->end);
>  		}
> @@ -5474,8 +5453,7 @@ skl_compute_wm(struct drm_atomic_state *state)
>  			&to_intel_crtc_state(crtc->state)->wm.skl.optimal;
>  
>  		pipe_wm = &intel_cstate->wm.skl.optimal;
> -		ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
> -					 &results->ddb, &changed);
> +		ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm, &changed);
>  		if (ret)
>  			return ret;
>  
> @@ -5489,7 +5467,7 @@ skl_compute_wm(struct drm_atomic_state *state)
>  		intel_cstate->update_wm_pre = true;
>  	}
>  
> -	skl_print_wm_changes(state);
> +	skl_print_wm_changes(intel_state);
>  
>  	return 0;
>  }
> @@ -5500,23 +5478,12 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
>  	struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>  	struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
> -	const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
>  	enum pipe pipe = crtc->pipe;
> -	enum plane_id plane_id;
>  
>  	if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
>  		return;
>  
>  	I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
> -
> -	for_each_plane_id_on_crtc(crtc, plane_id) {
> -		if (plane_id != PLANE_CURSOR)
> -			skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id],
> -					   ddb, plane_id);
> -		else
> -			skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id],
> -					    ddb);
> -	}
>  }
>  
>  static void skl_initial_wm(struct intel_atomic_state *state,
> @@ -5526,8 +5493,6 @@ static void skl_initial_wm(struct intel_atomic_state *state,
>  	struct drm_device *dev = intel_crtc->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct skl_ddb_values *results = &state->wm_results;
> -	struct skl_ddb_values *hw_vals = &dev_priv->wm.skl_hw;
> -	enum pipe pipe = intel_crtc->pipe;
>  
>  	if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
>  		return;
> @@ -5537,11 +5502,6 @@ static void skl_initial_wm(struct intel_atomic_state *state,
>  	if (cstate->base.active_changed)
>  		skl_atomic_update_crtc_wm(state, cstate);
>  
> -	memcpy(hw_vals->ddb.uv_plane[pipe], results->ddb.uv_plane[pipe],
> -	       sizeof(hw_vals->ddb.uv_plane[pipe]));
> -	memcpy(hw_vals->ddb.plane[pipe], results->ddb.plane[pipe],
> -	       sizeof(hw_vals->ddb.plane[pipe]));
> -
>  	mutex_unlock(&dev_priv->wm.wm_mutex);
>  }
>  
> @@ -5692,13 +5652,6 @@ void skl_wm_get_hw_state(struct drm_device *dev)
>  	if (dev_priv->active_crtcs) {
>  		/* Fully recompute DDB on first atomic commit */
>  		dev_priv->wm.distrust_bios_wm = true;
> -	} else {
> -		/*
> -		 * Easy/common case; just sanitize DDB now if everything off
> -		 * Keep dbuf slice info intact
> -		 */
> -		memset(ddb->plane, 0, sizeof(ddb->plane));
> -		memset(ddb->uv_plane, 0, sizeof(ddb->uv_plane));
>  	}
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 74d904a49bf9..0262159e7084 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -542,6 +542,8 @@ skl_program_plane(struct intel_plane *plane,
>  	if (fb->format->is_yuv && icl_is_hdr_plane(plane))
>  		icl_program_input_csc_coeff(crtc_state, plane_state);
>  
> +	skl_write_plane_wm(plane, crtc_state);
> +
>  	I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
>  	I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk);
>  	I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax);
> @@ -604,6 +606,8 @@ skl_disable_plane(struct intel_plane *plane,
>  
>  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>  
> +	skl_write_plane_wm(plane, crtc_state);
> +
>  	I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
>  	I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
>  
> -- 
> 2.18.1
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 10/13] drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+

[Ville Syrjälä]

On Tue, Nov 20, 2018 at 04:48:39PM -0800, Matt Roper wrote:
> On Wed, Nov 14, 2018 at 11:07:26PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > On SKL+ the plane WM/BUF_CFG registers are a proper part of each
> > plane's register set. That means accessing them will cancel any
> > pending plane update, and we would need a PLANE_SURF register write
> > to arm the wm/ddb change as well.
> > 
> > To avoid all the problems with that let's just move the wm/ddb
> > programming into the plane update/disable hooks. Now all plane
> > registers get written in one (hopefully atomic) operation.
> > 
> > To make that feasible we'll move the plane ddb tracking into
> > the crtc state. Watermarks were already tracked there.
> > 
> > v2: Rebase due to input CSC
> > v3: Split out a bunch of junk (Matt)
> > 
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_debugfs.c  |  21 +-
> >  drivers/gpu/drm/i915/i915_drv.h      |   3 -
> >  drivers/gpu/drm/i915/intel_display.c |  16 +-
> >  drivers/gpu/drm/i915/intel_display.h |  11 +-
> >  drivers/gpu/drm/i915/intel_drv.h     |   9 +
> >  drivers/gpu/drm/i915/intel_pm.c      | 317 ++++++++++++---------------
> >  drivers/gpu/drm/i915/intel_sprite.c  |   4 +
> >  7 files changed, 181 insertions(+), 200 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 670db5073d70..f8b2200947cf 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -3437,31 +3437,32 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
> >  {
> >  	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> >  	struct drm_device *dev = &dev_priv->drm;
> > -	struct skl_ddb_allocation *ddb;
> >  	struct skl_ddb_entry *entry;
> > -	enum pipe pipe;
> > -	int plane;
> > +	struct intel_crtc *crtc;
> >  
> >  	if (INTEL_GEN(dev_priv) < 9)
> >  		return -ENODEV;
> >  
> >  	drm_modeset_lock_all(dev);
> >  
> > -	ddb = &dev_priv->wm.skl_hw.ddb;
> > -
> >  	seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
> >  
> > -	for_each_pipe(dev_priv, pipe) {
> > +	for_each_intel_crtc(&dev_priv->drm, crtc) {
> > +		struct intel_crtc_state *crtc_state =
> > +			to_intel_crtc_state(crtc->base.state);
> > +		enum pipe pipe = crtc->pipe;
> > +		enum plane_id plane_id;
> > +
> >  		seq_printf(m, "Pipe %c\n", pipe_name(pipe));
> >  
> > -		for_each_universal_plane(dev_priv, pipe, plane) {
> > -			entry = &ddb->plane[pipe][plane];
> > -			seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
> > +		for_each_plane_id_on_crtc(crtc, plane_id) {
> > +			entry = &crtc_state->wm.skl.plane_ddb_y[plane_id];
> > +			seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane_id + 1,
> >  				   entry->start, entry->end,
> >  				   skl_ddb_entry_size(entry));
> >  		}
> >  
> > -		entry = &ddb->plane[pipe][PLANE_CURSOR];
> > +		entry = &crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
> >  		seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
> >  			   entry->end, skl_ddb_entry_size(entry));
> >  	}
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 5d686b585a95..89af64fe90a5 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1241,9 +1241,6 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
> >  }
> >  
> >  struct skl_ddb_allocation {
> > -	/* packed/y */
> > -	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
> > -	struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
> >  	u8 enabled_slices; /* GEN11 has configurable 2 slices */
> >  };
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 0caba7258fee..2981cea3704a 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -10083,6 +10083,10 @@ static void i9xx_update_cursor(struct intel_plane *plane,
> >  	 * except when the plane is getting enabled at which time
> >  	 * the CURCNTR write arms the update.
> >  	 */
> > +
> > +	if (INTEL_GEN(dev_priv) >= 9)
> > +		skl_write_cursor_wm(plane, crtc_state);
> > +
> >  	if (plane->cursor.base != base ||
> >  	    plane->cursor.size != fbc_ctl ||
> >  	    plane->cursor.cntl != cntl) {
> > @@ -11872,6 +11876,8 @@ static void verify_wm_state(struct drm_crtc *crtc,
> >  	struct skl_pipe_wm hw_wm, *sw_wm;
> >  	struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
> >  	struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
> > +	struct skl_ddb_entry hw_ddb_y[I915_MAX_PLANES];
> > +	struct skl_ddb_entry hw_ddb_uv[I915_MAX_PLANES];
> >  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> >  	const enum pipe pipe = intel_crtc->pipe;
> >  	int plane, level, max_level = ilk_wm_max_level(dev_priv);
> > @@ -11882,6 +11888,8 @@ static void verify_wm_state(struct drm_crtc *crtc,
> >  	skl_pipe_wm_get_hw_state(crtc, &hw_wm);
> >  	sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
> >  
> > +	skl_pipe_ddb_get_hw_state(intel_crtc, hw_ddb_y, hw_ddb_uv);
> > +
> >  	skl_ddb_get_hw_state(dev_priv, &hw_ddb);
> >  	sw_ddb = &dev_priv->wm.skl_hw.ddb;
> >  
> > @@ -11924,8 +11932,8 @@ static void verify_wm_state(struct drm_crtc *crtc,
> >  		}
> >  
> >  		/* DDB */
> > -		hw_ddb_entry = &hw_ddb.plane[pipe][plane];
> > -		sw_ddb_entry = &sw_ddb->plane[pipe][plane];
> > +		hw_ddb_entry = &hw_ddb_y[plane];
> > +		sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[plane];
> >  
> >  		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
> >  			DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
> > @@ -11974,8 +11982,8 @@ static void verify_wm_state(struct drm_crtc *crtc,
> >  		}
> >  
> >  		/* DDB */
> > -		hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
> > -		sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
> > +		hw_ddb_entry = &hw_ddb_y[PLANE_CURSOR];
> > +		sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[PLANE_CURSOR];
> >  
> >  		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
> >  			DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
> > diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
> > index df9e6ebb27de..078406dc65e5 100644
> > --- a/drivers/gpu/drm/i915/intel_display.h
> > +++ b/drivers/gpu/drm/i915/intel_display.h
> > @@ -319,7 +319,7 @@ struct intel_link_m_n {
> >  			    &(dev)->mode_config.plane_list,		\
> >  			    base.head)					\
> >  		for_each_if((plane_mask) &				\
> > -			    drm_plane_mask(&intel_plane->base)))
> > +			    drm_plane_mask(&intel_plane->base))
> >  
> >  #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
> >  	list_for_each_entry(intel_plane,				\
> > @@ -415,6 +415,15 @@ struct intel_link_m_n {
> >  	     (__i)++) \
> >  		for_each_if(plane)
> >  
> > +#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
> > +	for ((__i) = 0; \
> > +	     (__i) < (__state)->base.dev->mode_config.num_crtc && \
> > +		     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
> > +		      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
> > +		      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
> > +	     (__i)++) \
> > +		for_each_if(crtc)
> > +
> >  void intel_link_compute_m_n(int bpp, int nlanes,
> >  			    int pixel_clock, int link_clock,
> >  			    struct intel_link_m_n *m_n,
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 23b33970db17..4a9af09c483a 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -705,6 +705,8 @@ struct intel_crtc_wm_state {
> >  			/* gen9+ only needs 1-step wm programming */
> >  			struct skl_pipe_wm optimal;
> >  			struct skl_ddb_entry ddb;
> > +			struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
> > +			struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
> 
> I feel like naming these _y and _uv is going to cause confusion.  The Y
> and UV are backwards half the time (based on the swap we have to do
> farther down), and doesn't have meaning at all for RGB.  Maybe name
> these something like "plane_ddb_main" and "plane_ddb_extra" to somewhat
> disassociate it with the actual type of data it's supposed to represent?
> 
> If you want to keep the _y and _uv (which are nice and short), I think
> we at least need some warning comments here explaining the behavior.

Yeah, I was also thinking we might want to just start following the
hardware convention with these and get rid of the swap()s. My initial
idea was just something like ddb[] and ddb_nv12[] to match the
register names.

But let's do that as a followup maybe?

> 
> >  		} skl;
> >  
> >  		struct {
> > @@ -2183,6 +2185,9 @@ void g4x_wm_get_hw_state(struct drm_device *dev);
> >  void vlv_wm_get_hw_state(struct drm_device *dev);
> >  void ilk_wm_get_hw_state(struct drm_device *dev);
> >  void skl_wm_get_hw_state(struct drm_device *dev);
> > +void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
> > +			       struct skl_ddb_entry *ddb_y,
> > +			       struct skl_ddb_entry *ddb_uv);
> >  void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
> >  			  struct skl_ddb_allocation *ddb /* out */);
> >  void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
> > @@ -2197,6 +2202,10 @@ bool skl_wm_level_equals(const struct skl_wm_level *l1,
> >  bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
> >  				 const struct skl_ddb_entry entries[],
> >  				 int num_entries, int ignore_idx);
> > +void skl_write_plane_wm(struct intel_plane *plane,
> > +			const struct intel_crtc_state *crtc_state);
> > +void skl_write_cursor_wm(struct intel_plane *plane,
> > +			 const struct intel_crtc_state *crtc_state);
> >  bool ilk_disable_lp_wm(struct drm_device *dev);
> >  int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
> >  				  struct intel_crtc_state *cstate);
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index a21654c974ba..1b337004054a 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3912,68 +3912,70 @@ static void
> >  skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
> >  			   const enum pipe pipe,
> >  			   const enum plane_id plane_id,
> > -			   struct skl_ddb_allocation *ddb /* out */)
> > +			   struct skl_ddb_entry *ddb_y,
> > +			   struct skl_ddb_entry *ddb_uv)
> >  {
> > -	u32 val, val2 = 0;
> > -	int fourcc, pixel_format;
> > +	u32 val, val2;
> > +	u32 fourcc = 0;
> >  
> >  	/* Cursor doesn't support NV12/planar, so no extra calculation needed */
> >  	if (plane_id == PLANE_CURSOR) {
> >  		val = I915_READ(CUR_BUF_CFG(pipe));
> > -		skl_ddb_entry_init_from_hw(dev_priv,
> > -					   &ddb->plane[pipe][plane_id], val);
> > +		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
> >  		return;
> >  	}
> >  
> >  	val = I915_READ(PLANE_CTL(pipe, plane_id));
> >  
> >  	/* No DDB allocated for disabled planes */
> > -	if (!(val & PLANE_CTL_ENABLE))
> > -		return;
> 
> I think we should mention the readout behavior change in the commit
> message (i.e., we now read out DDB even if we think the plane is
> disabled).  Either that or move the behavior change to a separate patch.
> 
> We should also drop the comment line since I don't think it really makes
> sense anymore.

Sure.

> 
> > +	if (val & PLANE_CTL_ENABLE)
> > +		fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK,
> > +					      val & PLANE_CTL_ORDER_RGBX,
> > +					      val & PLANE_CTL_ALPHA_MASK);
> >  
> > -	pixel_format = val & PLANE_CTL_FORMAT_MASK;
> > -	fourcc = skl_format_to_fourcc(pixel_format,
> > -				      val & PLANE_CTL_ORDER_RGBX,
> > -				      val & PLANE_CTL_ALPHA_MASK);
> > -
> > -	val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
> > -	if (fourcc == DRM_FORMAT_NV12 && INTEL_GEN(dev_priv) < 11) {
> > +	if (INTEL_GEN(dev_priv) >= 11) {
> > +		val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
> > +		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
> > +	} else {
> > +		val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
> >  		val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
> >  
> > -		skl_ddb_entry_init_from_hw(dev_priv,
> > -					   &ddb->plane[pipe][plane_id], val2);
> > -		skl_ddb_entry_init_from_hw(dev_priv,
> > -					   &ddb->uv_plane[pipe][plane_id], val);
> > -	} else {
> > -		skl_ddb_entry_init_from_hw(dev_priv,
> > -					   &ddb->plane[pipe][plane_id], val);
> > +		if (fourcc == DRM_FORMAT_NV12)
> > +			swap(val, val2);
> > +
> > +		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
> > +		skl_ddb_entry_init_from_hw(dev_priv, ddb_uv, val2);
> >  	}
> >  }
> >  
> > +void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
> > +			       struct skl_ddb_entry *ddb_y,
> > +			       struct skl_ddb_entry *ddb_uv)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +	enum intel_display_power_domain power_domain;
> > +	enum pipe pipe = crtc->pipe;
> > +	enum plane_id plane_id;
> > +
> > +	power_domain = POWER_DOMAIN_PIPE(pipe);
> > +	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
> > +		return;
> > +
> > +	for_each_plane_id_on_crtc(crtc, plane_id)
> > +		skl_ddb_get_hw_plane_state(dev_priv, pipe,
> > +					   plane_id,
> > +					   &ddb_y[plane_id],
> > +					   &ddb_uv[plane_id]);
> > +
> > +	intel_display_power_put(dev_priv, power_domain);
> > +}
> > +
> >  void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
> >  			  struct skl_ddb_allocation *ddb /* out */)
> >  {
> > -	struct intel_crtc *crtc;
> > -
> >  	memset(ddb, 0, sizeof(*ddb));
> 
> We can drop the memset.  The entire structure is only 1 byte now, and we
> set its only remaining field on the next line.

Ack.

> 
> >  
> >  	ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
> > -
> > -	for_each_intel_crtc(&dev_priv->drm, crtc) {
> > -		enum intel_display_power_domain power_domain;
> > -		enum plane_id plane_id;
> > -		enum pipe pipe = crtc->pipe;
> > -
> > -		power_domain = POWER_DOMAIN_PIPE(pipe);
> > -		if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
> > -			continue;
> > -
> > -		for_each_plane_id_on_crtc(crtc, plane_id)
> > -			skl_ddb_get_hw_plane_state(dev_priv, pipe,
> > -						   plane_id, ddb);
> > -
> > -		intel_display_power_put(dev_priv, power_domain);
> > -	}
> >  }
> >  
> >  /*
> > @@ -4371,7 +4373,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> >  	struct drm_crtc *crtc = cstate->base.crtc;
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> >  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > -	enum pipe pipe = intel_crtc->pipe;
> >  	struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
> >  	uint16_t alloc_size, start;
> >  	uint16_t minimum[I915_MAX_PLANES] = {};
> > @@ -4384,8 +4385,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> >  	uint16_t total_min_blocks = 0;
> >  
> >  	/* Clear the partitioning for disabled planes. */
> > -	memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
> > -	memset(ddb->uv_plane[pipe], 0, sizeof(ddb->uv_plane[pipe]));
> > +	memset(cstate->wm.skl.plane_ddb_y, 0, sizeof(cstate->wm.skl.plane_ddb_y));
> > +	memset(cstate->wm.skl.plane_ddb_uv, 0, sizeof(cstate->wm.skl.plane_ddb_uv));
> >  
> >  	if (WARN_ON(!state))
> >  		return 0;
> > @@ -4432,8 +4433,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> >  	}
> >  
> >  	alloc_size -= total_min_blocks;
> > -	ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
> > -	ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
> > +	cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
> > +	cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
> >  
> >  	/*
> >  	 * 2. Distribute the remaining space in proportion to the amount of
> > @@ -4464,8 +4465,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> >  
> >  		/* Leave disabled planes at (0,0) */
> >  		if (data_rate) {
> > -			ddb->plane[pipe][plane_id].start = start;
> > -			ddb->plane[pipe][plane_id].end = start + plane_blocks;
> > +			cstate->wm.skl.plane_ddb_y[plane_id].start = start;
> > +			cstate->wm.skl.plane_ddb_y[plane_id].end = start + plane_blocks;
> >  		}
> >  
> >  		start += plane_blocks;
> > @@ -4480,8 +4481,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> >  		WARN_ON(INTEL_GEN(dev_priv) >= 11 && uv_plane_blocks);
> >  
> >  		if (uv_data_rate) {
> > -			ddb->uv_plane[pipe][plane_id].start = start;
> > -			ddb->uv_plane[pipe][plane_id].end =
> > +			cstate->wm.skl.plane_ddb_uv[plane_id].start = start;
> > +			cstate->wm.skl.plane_ddb_uv[plane_id].end =
> >  				start + uv_plane_blocks;
> >  		}
> >  
> > @@ -4939,16 +4940,13 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
> >  	}
> >  }
> >  
> > -static int skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
> > -				     struct intel_crtc_state *crtc_state,
> > +static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
> >  				     const struct intel_plane_state *plane_state,
> >  				     enum plane_id plane_id, int color_plane)
> >  {
> > -	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> >  	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
> > +	u16 ddb_blocks = skl_ddb_entry_size(&crtc_state->wm.skl.plane_ddb_y[plane_id]);
> >  	struct skl_wm_params wm_params;
> > -	enum pipe pipe = plane->pipe;
> > -	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
> >  	int ret;
> >  
> >  	ret = skl_compute_plane_wm_params(crtc_state, plane_state,
> > @@ -4966,16 +4964,13 @@ static int skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
> >  	return 0;
> >  }
> >  
> > -static int skl_build_plane_wm_uv(struct skl_ddb_allocation *ddb,
> > -				 struct intel_crtc_state *crtc_state,
> > +static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
> >  				 const struct intel_plane_state *plane_state,
> >  				 enum plane_id plane_id)
> >  {
> > -	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> >  	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
> > +	u16 ddb_blocks = skl_ddb_entry_size(&crtc_state->wm.skl.plane_ddb_uv[plane_id]);
> >  	struct skl_wm_params wm_params;
> > -	enum pipe pipe = plane->pipe;
> > -	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->uv_plane[pipe][plane_id]);
> >  	int ret;
> >  
> >  	wm->is_planar = true;
> > @@ -4994,8 +4989,7 @@ static int skl_build_plane_wm_uv(struct skl_ddb_allocation *ddb,
> >  	return 0;
> >  }
> >  
> > -static int skl_build_plane_wm(struct skl_ddb_allocation *ddb,
> > -			      struct skl_pipe_wm *pipe_wm,
> > +static int skl_build_plane_wm(struct skl_pipe_wm *pipe_wm,
> >  			      struct intel_crtc_state *crtc_state,
> >  			      const struct intel_plane_state *plane_state)
> >  {
> > @@ -5007,13 +5001,13 @@ static int skl_build_plane_wm(struct skl_ddb_allocation *ddb,
> >  	if (!intel_wm_plane_visible(crtc_state, plane_state))
> >  		return 0;
> >  
> > -	ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
> > +	ret = skl_build_plane_wm_single(crtc_state, plane_state,
> >  					plane_id, 0);
> >  	if (ret)
> >  		return ret;
> >  
> >  	if (fb->format->is_yuv && fb->format->num_planes > 1) {
> > -		ret = skl_build_plane_wm_uv(ddb, crtc_state, plane_state,
> > +		ret = skl_build_plane_wm_uv(crtc_state, plane_state,
> >  					    plane_id);
> >  		if (ret)
> >  			return ret;
> > @@ -5022,8 +5016,7 @@ static int skl_build_plane_wm(struct skl_ddb_allocation *ddb,
> >  	return 0;
> >  }
> >  
> > -static int icl_build_plane_wm(struct skl_ddb_allocation *ddb,
> > -			      struct skl_pipe_wm *pipe_wm,
> > +static int icl_build_plane_wm(struct skl_pipe_wm *pipe_wm,
> >  			      struct intel_crtc_state *crtc_state,
> >  			      const struct intel_plane_state *plane_state)
> >  {
> > @@ -5041,17 +5034,17 @@ static int icl_build_plane_wm(struct skl_ddb_allocation *ddb,
> >  		WARN_ON(!fb->format->is_yuv ||
> >  			fb->format->num_planes == 1);
> >  
> > -		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
> > +		ret = skl_build_plane_wm_single(crtc_state, plane_state,
> >  						y_plane_id, 0);
> >  		if (ret)
> >  			return ret;
> >  
> > -		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
> > +		ret = skl_build_plane_wm_single(crtc_state, plane_state,
> >  						plane_id, 1);
> >  		if (ret)
> >  			return ret;
> >  	} else if (intel_wm_plane_visible(crtc_state, plane_state)) {
> > -		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
> > +		ret = skl_build_plane_wm_single(crtc_state, plane_state,
> >  						plane_id, 0);
> >  		if (ret)
> >  			return ret;
> > @@ -5061,7 +5054,6 @@ static int icl_build_plane_wm(struct skl_ddb_allocation *ddb,
> >  }
> >  
> >  static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
> > -			     struct skl_ddb_allocation *ddb,
> >  			     struct skl_pipe_wm *pipe_wm)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
> > @@ -5081,10 +5073,10 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
> >  						to_intel_plane_state(pstate);
> >  
> >  		if (INTEL_GEN(dev_priv) >= 11)
> > -			ret = icl_build_plane_wm(ddb, pipe_wm,
> > +			ret = icl_build_plane_wm(pipe_wm,
> >  						 cstate, intel_pstate);
> >  		else
> > -			ret = skl_build_plane_wm(ddb, pipe_wm,
> > +			ret = skl_build_plane_wm(pipe_wm,
> >  						 cstate, intel_pstate);
> >  		if (ret)
> >  			return ret;
> > @@ -5100,9 +5092,9 @@ static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
> >  				const struct skl_ddb_entry *entry)
> >  {
> >  	if (entry->end)
> > -		I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
> > +		I915_WRITE_FW(reg, (entry->end - 1) << 16 | entry->start);
> >  	else
> > -		I915_WRITE(reg, 0);
> > +		I915_WRITE_FW(reg, 0);
> >  }
> >  
> >  static void skl_write_wm_level(struct drm_i915_private *dev_priv,
> > @@ -5117,19 +5109,22 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv,
> >  		val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
> >  	}
> >  
> > -	I915_WRITE(reg, val);
> > +	I915_WRITE_FW(reg, val);
> >  }
> >  
> > -static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
> > -			       const struct skl_plane_wm *wm,
> > -			       const struct skl_ddb_allocation *ddb,
> > -			       enum plane_id plane_id)
> > +void skl_write_plane_wm(struct intel_plane *plane,
> > +			const struct intel_crtc_state *crtc_state)
> >  {
> > -	struct drm_crtc *crtc = &intel_crtc->base;
> > -	struct drm_device *dev = crtc->dev;
> > -	struct drm_i915_private *dev_priv = to_i915(dev);
> > +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> >  	int level, max_level = ilk_wm_max_level(dev_priv);
> > -	enum pipe pipe = intel_crtc->pipe;
> > +	enum plane_id plane_id = plane->id;
> > +	enum pipe pipe = plane->pipe;
> > +	const struct skl_plane_wm *wm =
> > +		&crtc_state->wm.skl.optimal.planes[plane_id];
> > +	const struct skl_ddb_entry *ddb_y =
> > +		&crtc_state->wm.skl.plane_ddb_y[plane_id];
> > +	const struct skl_ddb_entry *ddb_uv =
> > +		&crtc_state->wm.skl.plane_ddb_uv[plane_id];
> >  
> >  	for (level = 0; level <= max_level; level++) {
> >  		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
> > @@ -5138,29 +5133,32 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
> >  	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
> >  			   &wm->trans_wm);
> >  
> > -	if (wm->is_planar && INTEL_GEN(dev_priv) < 11) {
> > -		skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
> > -				    &ddb->uv_plane[pipe][plane_id]);
> > +	if (INTEL_GEN(dev_priv) >= 11) {
> >  		skl_ddb_entry_write(dev_priv,
> > -				    PLANE_NV12_BUF_CFG(pipe, plane_id),
> > -				    &ddb->plane[pipe][plane_id]);
> > -	} else {
> > -		skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
> > -				    &ddb->plane[pipe][plane_id]);
> > -		if (INTEL_GEN(dev_priv) < 11)
> > -			I915_WRITE(PLANE_NV12_BUF_CFG(pipe, plane_id), 0x0);
> > +				    PLANE_BUF_CFG(pipe, plane_id), ddb_y);
> > +		return;
> >  	}
> > +
> > +	if (wm->is_planar)
> > +		swap(ddb_y, ddb_uv);
> 
> As noted above, I understand why this is, but it sure looks confusing at
> a casual glance...
> 
> 
> Matt
> 
> > +
> > +	skl_ddb_entry_write(dev_priv,
> > +			    PLANE_BUF_CFG(pipe, plane_id), ddb_y);
> > +	skl_ddb_entry_write(dev_priv,
> > +			    PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_uv);
> >  }
> >  
> > -static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
> > -				const struct skl_plane_wm *wm,
> > -				const struct skl_ddb_allocation *ddb)
> > +void skl_write_cursor_wm(struct intel_plane *plane,
> > +			 const struct intel_crtc_state *crtc_state)
> >  {
> > -	struct drm_crtc *crtc = &intel_crtc->base;
> > -	struct drm_device *dev = crtc->dev;
> > -	struct drm_i915_private *dev_priv = to_i915(dev);
> > +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> >  	int level, max_level = ilk_wm_max_level(dev_priv);
> > -	enum pipe pipe = intel_crtc->pipe;
> > +	enum plane_id plane_id = plane->id;
> > +	enum pipe pipe = plane->pipe;
> > +	const struct skl_plane_wm *wm =
> > +		&crtc_state->wm.skl.optimal.planes[plane_id];
> > +	const struct skl_ddb_entry *ddb =
> > +		&crtc_state->wm.skl.plane_ddb_y[plane_id];
> >  
> >  	for (level = 0; level <= max_level; level++) {
> >  		skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
> > @@ -5168,8 +5166,7 @@ static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
> >  	}
> >  	skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
> >  
> > -	skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
> > -			    &ddb->plane[pipe][PLANE_CURSOR]);
> > +	skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), ddb);
> >  }
> >  
> >  bool skl_wm_level_equals(const struct skl_wm_level *l1,
> > @@ -5210,13 +5207,12 @@ bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
> >  static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
> >  			      const struct skl_pipe_wm *old_pipe_wm,
> >  			      struct skl_pipe_wm *pipe_wm, /* out */
> > -			      struct skl_ddb_allocation *ddb, /* out */
> >  			      bool *changed /* out */)
> >  {
> >  	struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
> >  	int ret;
> >  
> > -	ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
> > +	ret = skl_build_pipe_wm(intel_cstate, pipe_wm);
> >  	if (ret)
> >  		return ret;
> >  
> > @@ -5242,42 +5238,29 @@ pipes_modified(struct drm_atomic_state *state)
> >  }
> >  
> >  static int
> > -skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
> > +skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
> > +			    struct intel_crtc_state *new_crtc_state)
> >  {
> > -	struct drm_atomic_state *state = cstate->base.state;
> > -	struct drm_device *dev = state->dev;
> > -	struct drm_crtc *crtc = cstate->base.crtc;
> > -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > -	struct drm_i915_private *dev_priv = to_i915(dev);
> > -	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> > -	struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
> > -	struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
> > -	struct drm_plane *plane;
> > -	enum pipe pipe = intel_crtc->pipe;
> > +	struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->base.state);
> > +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +	struct intel_plane *plane;
> >  
> > -	drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
> > -		struct drm_plane_state *plane_state;
> > -		struct intel_plane *linked;
> > -		enum plane_id plane_id = to_intel_plane(plane)->id;
> > +	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> > +		struct intel_plane_state *plane_state;
> > +		enum plane_id plane_id = plane->id;
> >  
> > -		if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
> > -					&new_ddb->plane[pipe][plane_id]) &&
> > -		    skl_ddb_entry_equal(&cur_ddb->uv_plane[pipe][plane_id],
> > -					&new_ddb->uv_plane[pipe][plane_id]))
> > +		if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
> > +					&new_crtc_state->wm.skl.plane_ddb_y[plane_id]) &&
> > +		    skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_uv[plane_id],
> > +					&new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
> >  			continue;
> >  
> > -		plane_state = drm_atomic_get_plane_state(state, plane);
> > +		plane_state = intel_atomic_get_plane_state(state, plane);
> >  		if (IS_ERR(plane_state))
> >  			return PTR_ERR(plane_state);
> >  
> > -		/* Make sure linked plane is updated too */
> > -		linked = to_intel_plane_state(plane_state)->linked_plane;
> > -		if (!linked)
> > -			continue;
> > -
> > -		plane_state = drm_atomic_get_plane_state(state, &linked->base);
> > -		if (IS_ERR(plane_state))
> > -			return PTR_ERR(plane_state);
> > +		new_crtc_state->update_planes |= BIT(plane_id);
> >  	}
> >  
> >  	return 0;
> > @@ -5289,18 +5272,21 @@ skl_compute_ddb(struct drm_atomic_state *state)
> >  	const struct drm_i915_private *dev_priv = to_i915(state->dev);
> >  	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> >  	struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
> > +	struct intel_crtc_state *old_crtc_state;
> > +	struct intel_crtc_state *new_crtc_state;
> >  	struct intel_crtc *crtc;
> > -	struct intel_crtc_state *cstate;
> >  	int ret, i;
> >  
> >  	memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
> >  
> > -	for_each_new_intel_crtc_in_state(intel_state, crtc, cstate, i) {
> > -		ret = skl_allocate_pipe_ddb(cstate, ddb);
> > +	for_each_oldnew_intel_crtc_in_state(intel_state, crtc, old_crtc_state,
> > +					    new_crtc_state, i) {
> > +		ret = skl_allocate_pipe_ddb(new_crtc_state, ddb);
> >  		if (ret)
> >  			return ret;
> >  
> > -		ret = skl_ddb_add_affected_planes(cstate);
> > +		ret = skl_ddb_add_affected_planes(old_crtc_state,
> > +						  new_crtc_state);
> >  		if (ret)
> >  			return ret;
> >  	}
> > @@ -5309,36 +5295,29 @@ skl_compute_ddb(struct drm_atomic_state *state)
> >  }
> >  
> >  static void
> > -skl_print_wm_changes(const struct drm_atomic_state *state)
> > +skl_print_wm_changes(struct intel_atomic_state *state)
> >  {
> > -	const struct drm_device *dev = state->dev;
> > -	const struct drm_i915_private *dev_priv = to_i915(dev);
> > -	const struct intel_atomic_state *intel_state =
> > -		to_intel_atomic_state(state);
> > -	const struct drm_crtc *crtc;
> > -	const struct drm_crtc_state *cstate;
> > -	const struct intel_plane *intel_plane;
> > -	const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
> > -	const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
> > +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > +	const struct intel_crtc_state *old_crtc_state;
> > +	const struct intel_crtc_state *new_crtc_state;
> > +	struct intel_plane *plane;
> > +	struct intel_crtc *crtc;
> >  	int i;
> >  
> > -	for_each_new_crtc_in_state(state, crtc, cstate, i) {
> > -		const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > -		enum pipe pipe = intel_crtc->pipe;
> > -
> > -		for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
> > -			enum plane_id plane_id = intel_plane->id;
> > +	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> > +					    new_crtc_state, i) {
> > +		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> > +			enum plane_id plane_id = plane->id;
> >  			const struct skl_ddb_entry *old, *new;
> >  
> > -			old = &old_ddb->plane[pipe][plane_id];
> > -			new = &new_ddb->plane[pipe][plane_id];
> > +			old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];
> > +			new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];
> >  
> >  			if (skl_ddb_entry_equal(old, new))
> >  				continue;
> >  
> >  			DRM_DEBUG_KMS("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
> > -				      intel_plane->base.base.id,
> > -				      intel_plane->base.name,
> > +				      plane->base.base.id, plane->base.name,
> >  				      old->start, old->end,
> >  				      new->start, new->end);
> >  		}
> > @@ -5474,8 +5453,7 @@ skl_compute_wm(struct drm_atomic_state *state)
> >  			&to_intel_crtc_state(crtc->state)->wm.skl.optimal;
> >  
> >  		pipe_wm = &intel_cstate->wm.skl.optimal;
> > -		ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
> > -					 &results->ddb, &changed);
> > +		ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm, &changed);
> >  		if (ret)
> >  			return ret;
> >  
> > @@ -5489,7 +5467,7 @@ skl_compute_wm(struct drm_atomic_state *state)
> >  		intel_cstate->update_wm_pre = true;
> >  	}
> >  
> > -	skl_print_wm_changes(state);
> > +	skl_print_wm_changes(intel_state);
> >  
> >  	return 0;
> >  }
> > @@ -5500,23 +5478,12 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
> >  	struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
> >  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> >  	struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
> > -	const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
> >  	enum pipe pipe = crtc->pipe;
> > -	enum plane_id plane_id;
> >  
> >  	if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
> >  		return;
> >  
> >  	I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
> > -
> > -	for_each_plane_id_on_crtc(crtc, plane_id) {
> > -		if (plane_id != PLANE_CURSOR)
> > -			skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id],
> > -					   ddb, plane_id);
> > -		else
> > -			skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id],
> > -					    ddb);
> > -	}
> >  }
> >  
> >  static void skl_initial_wm(struct intel_atomic_state *state,
> > @@ -5526,8 +5493,6 @@ static void skl_initial_wm(struct intel_atomic_state *state,
> >  	struct drm_device *dev = intel_crtc->base.dev;
> >  	struct drm_i915_private *dev_priv = to_i915(dev);
> >  	struct skl_ddb_values *results = &state->wm_results;
> > -	struct skl_ddb_values *hw_vals = &dev_priv->wm.skl_hw;
> > -	enum pipe pipe = intel_crtc->pipe;
> >  
> >  	if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
> >  		return;
> > @@ -5537,11 +5502,6 @@ static void skl_initial_wm(struct intel_atomic_state *state,
> >  	if (cstate->base.active_changed)
> >  		skl_atomic_update_crtc_wm(state, cstate);
> >  
> > -	memcpy(hw_vals->ddb.uv_plane[pipe], results->ddb.uv_plane[pipe],
> > -	       sizeof(hw_vals->ddb.uv_plane[pipe]));
> > -	memcpy(hw_vals->ddb.plane[pipe], results->ddb.plane[pipe],
> > -	       sizeof(hw_vals->ddb.plane[pipe]));
> > -
> >  	mutex_unlock(&dev_priv->wm.wm_mutex);
> >  }
> >  
> > @@ -5692,13 +5652,6 @@ void skl_wm_get_hw_state(struct drm_device *dev)
> >  	if (dev_priv->active_crtcs) {
> >  		/* Fully recompute DDB on first atomic commit */
> >  		dev_priv->wm.distrust_bios_wm = true;
> > -	} else {
> > -		/*
> > -		 * Easy/common case; just sanitize DDB now if everything off
> > -		 * Keep dbuf slice info intact
> > -		 */
> > -		memset(ddb->plane, 0, sizeof(ddb->plane));
> > -		memset(ddb->uv_plane, 0, sizeof(ddb->uv_plane));
> >  	}
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > index 74d904a49bf9..0262159e7084 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -542,6 +542,8 @@ skl_program_plane(struct intel_plane *plane,
> >  	if (fb->format->is_yuv && icl_is_hdr_plane(plane))
> >  		icl_program_input_csc_coeff(crtc_state, plane_state);
> >  
> > +	skl_write_plane_wm(plane, crtc_state);
> > +
> >  	I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
> >  	I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk);
> >  	I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax);
> > @@ -604,6 +606,8 @@ skl_disable_plane(struct intel_plane *plane,
> >  
> >  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> >  
> > +	skl_write_plane_wm(plane, crtc_state);
> > +
> >  	I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
> >  	I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
> >  
> > -- 
> > 2.18.1
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v5 10/13] drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On SKL+ the plane WM/BUF_CFG registers are a proper part of each
plane's register set. That means accessing them will cancel any
pending plane update, and we would need a PLANE_SURF register write
to arm the wm/ddb change as well.

To avoid all the problems with that let's just move the wm/ddb
programming into the plane update/disable hooks. Now all plane
registers get written in one (hopefully atomic) operation.

To make that feasible we'll move the plane ddb tracking into
the crtc state. Watermarks were already tracked there.

v2: Rebase due to input CSC
v3: Split out a bunch of junk (Matt)
v4: Add skl_wm_add_affected_planes() to deal with
    cursor special case and non-zero wm register reset value
v5: Drop the unrelated for_each_intel_plane_mask() fix (Matt)
    Remove the redundant ddb memset() (Matt)

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> #v3
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  21 +-
 drivers/gpu/drm/i915/i915_drv.h      |   3 -
 drivers/gpu/drm/i915/intel_display.c |  16 +-
 drivers/gpu/drm/i915/intel_display.h |   9 +
 drivers/gpu/drm/i915/intel_drv.h     |   9 +
 drivers/gpu/drm/i915/intel_pm.c      | 405 ++++++++++++++-------------
 drivers/gpu/drm/i915/intel_sprite.c  |   4 +
 7 files changed, 260 insertions(+), 207 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 596810e0cfe8..129b9a6f8309 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3441,31 +3441,32 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
 	struct drm_device *dev = &dev_priv->drm;
-	struct skl_ddb_allocation *ddb;
 	struct skl_ddb_entry *entry;
-	enum pipe pipe;
-	int plane;
+	struct intel_crtc *crtc;
 
 	if (INTEL_GEN(dev_priv) < 9)
 		return -ENODEV;
 
 	drm_modeset_lock_all(dev);
 
-	ddb = &dev_priv->wm.skl_hw.ddb;
-
 	seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
 
-	for_each_pipe(dev_priv, pipe) {
+	for_each_intel_crtc(&dev_priv->drm, crtc) {
+		struct intel_crtc_state *crtc_state =
+			to_intel_crtc_state(crtc->base.state);
+		enum pipe pipe = crtc->pipe;
+		enum plane_id plane_id;
+
 		seq_printf(m, "Pipe %c\n", pipe_name(pipe));
 
-		for_each_universal_plane(dev_priv, pipe, plane) {
-			entry = &ddb->plane[pipe][plane];
-			seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
+		for_each_plane_id_on_crtc(crtc, plane_id) {
+			entry = &crtc_state->wm.skl.plane_ddb_y[plane_id];
+			seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane_id + 1,
 				   entry->start, entry->end,
 				   skl_ddb_entry_size(entry));
 		}
 
-		entry = &ddb->plane[pipe][PLANE_CURSOR];
+		entry = &crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
 		seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
 			   entry->end, skl_ddb_entry_size(entry));
 	}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f763b30f98d9..645c2bbdcdfa 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1095,9 +1095,6 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
 }
 
 struct skl_ddb_allocation {
-	/* packed/y */
-	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
-	struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
 	u8 enabled_slices; /* GEN11 has configurable 2 slices */
 };
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d088ffd9f542..6c5d71b44740 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10114,6 +10114,10 @@ static void i9xx_update_cursor(struct intel_plane *plane,
 	 * except when the plane is getting enabled at which time
 	 * the CURCNTR write arms the update.
 	 */
+
+	if (INTEL_GEN(dev_priv) >= 9)
+		skl_write_cursor_wm(plane, crtc_state);
+
 	if (plane->cursor.base != base ||
 	    plane->cursor.size != fbc_ctl ||
 	    plane->cursor.cntl != cntl) {
@@ -11903,6 +11907,8 @@ static void verify_wm_state(struct drm_crtc *crtc,
 	struct skl_pipe_wm hw_wm, *sw_wm;
 	struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
 	struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
+	struct skl_ddb_entry hw_ddb_y[I915_MAX_PLANES];
+	struct skl_ddb_entry hw_ddb_uv[I915_MAX_PLANES];
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	const enum pipe pipe = intel_crtc->pipe;
 	int plane, level, max_level = ilk_wm_max_level(dev_priv);
@@ -11913,6 +11919,8 @@ static void verify_wm_state(struct drm_crtc *crtc,
 	skl_pipe_wm_get_hw_state(crtc, &hw_wm);
 	sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
 
+	skl_pipe_ddb_get_hw_state(intel_crtc, hw_ddb_y, hw_ddb_uv);
+
 	skl_ddb_get_hw_state(dev_priv, &hw_ddb);
 	sw_ddb = &dev_priv->wm.skl_hw.ddb;
 
@@ -11955,8 +11963,8 @@ static void verify_wm_state(struct drm_crtc *crtc,
 		}
 
 		/* DDB */
-		hw_ddb_entry = &hw_ddb.plane[pipe][plane];
-		sw_ddb_entry = &sw_ddb->plane[pipe][plane];
+		hw_ddb_entry = &hw_ddb_y[plane];
+		sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[plane];
 
 		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
 			DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
@@ -12005,8 +12013,8 @@ static void verify_wm_state(struct drm_crtc *crtc,
 		}
 
 		/* DDB */
-		hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
-		sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
+		hw_ddb_entry = &hw_ddb_y[PLANE_CURSOR];
+		sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[PLANE_CURSOR];
 
 		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
 			DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index a9a181aa4587..a7ceb8f904f7 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -431,6 +431,15 @@ struct intel_link_m_n {
 	     (__i)++) \
 		for_each_if(plane)
 
+#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.dev->mode_config.num_crtc && \
+		     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+		      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+		      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)++) \
+		for_each_if(crtc)
+
 void intel_link_compute_m_n(int bpp, int nlanes,
 			    int pixel_clock, int link_clock,
 			    struct intel_link_m_n *m_n,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7842d193ac44..1a3a396862d1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -706,6 +706,8 @@ struct intel_crtc_wm_state {
 			/* gen9+ only needs 1-step wm programming */
 			struct skl_pipe_wm optimal;
 			struct skl_ddb_entry ddb;
+			struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
+			struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
 		} skl;
 
 		struct {
@@ -2185,6 +2187,9 @@ void g4x_wm_get_hw_state(struct drm_device *dev);
 void vlv_wm_get_hw_state(struct drm_device *dev);
 void ilk_wm_get_hw_state(struct drm_device *dev);
 void skl_wm_get_hw_state(struct drm_device *dev);
+void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
+			       struct skl_ddb_entry *ddb_y,
+			       struct skl_ddb_entry *ddb_uv);
 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
 			  struct skl_ddb_allocation *ddb /* out */);
 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
@@ -2199,6 +2204,10 @@ bool skl_wm_level_equals(const struct skl_wm_level *l1,
 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
 				 const struct skl_ddb_entry entries[],
 				 int num_entries, int ignore_idx);
+void skl_write_plane_wm(struct intel_plane *plane,
+			const struct intel_crtc_state *crtc_state);
+void skl_write_cursor_wm(struct intel_plane *plane,
+			 const struct intel_crtc_state *crtc_state);
 bool ilk_disable_lp_wm(struct drm_device *dev);
 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
 				  struct intel_crtc_state *cstate);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a5891f7a9f9d..b1f30d56b747 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3951,68 +3951,68 @@ static void
 skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
 			   const enum pipe pipe,
 			   const enum plane_id plane_id,
-			   struct skl_ddb_allocation *ddb /* out */)
+			   struct skl_ddb_entry *ddb_y,
+			   struct skl_ddb_entry *ddb_uv)
 {
-	u32 val, val2 = 0;
-	int fourcc, pixel_format;
+	u32 val, val2;
+	u32 fourcc = 0;
 
 	/* Cursor doesn't support NV12/planar, so no extra calculation needed */
 	if (plane_id == PLANE_CURSOR) {
 		val = I915_READ(CUR_BUF_CFG(pipe));
-		skl_ddb_entry_init_from_hw(dev_priv,
-					   &ddb->plane[pipe][plane_id], val);
+		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
 		return;
 	}
 
 	val = I915_READ(PLANE_CTL(pipe, plane_id));
 
 	/* No DDB allocated for disabled planes */
-	if (!(val & PLANE_CTL_ENABLE))
-		return;
-
-	pixel_format = val & PLANE_CTL_FORMAT_MASK;
-	fourcc = skl_format_to_fourcc(pixel_format,
-				      val & PLANE_CTL_ORDER_RGBX,
-				      val & PLANE_CTL_ALPHA_MASK);
+	if (val & PLANE_CTL_ENABLE)
+		fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK,
+					      val & PLANE_CTL_ORDER_RGBX,
+					      val & PLANE_CTL_ALPHA_MASK);
 
-	val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
-	if (fourcc == DRM_FORMAT_NV12 && INTEL_GEN(dev_priv) < 11) {
+	if (INTEL_GEN(dev_priv) >= 11) {
+		val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
+		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
+	} else {
+		val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
 		val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
 
-		skl_ddb_entry_init_from_hw(dev_priv,
-					   &ddb->plane[pipe][plane_id], val2);
-		skl_ddb_entry_init_from_hw(dev_priv,
-					   &ddb->uv_plane[pipe][plane_id], val);
-	} else {
-		skl_ddb_entry_init_from_hw(dev_priv,
-					   &ddb->plane[pipe][plane_id], val);
+		if (fourcc == DRM_FORMAT_NV12)
+			swap(val, val2);
+
+		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
+		skl_ddb_entry_init_from_hw(dev_priv, ddb_uv, val2);
 	}
 }
 
-void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
-			  struct skl_ddb_allocation *ddb /* out */)
+void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
+			       struct skl_ddb_entry *ddb_y,
+			       struct skl_ddb_entry *ddb_uv)
 {
-	struct intel_crtc *crtc;
-
-	memset(ddb, 0, sizeof(*ddb));
-
-	ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum intel_display_power_domain power_domain;
+	enum pipe pipe = crtc->pipe;
+	enum plane_id plane_id;
 
-	for_each_intel_crtc(&dev_priv->drm, crtc) {
-		enum intel_display_power_domain power_domain;
-		enum plane_id plane_id;
-		enum pipe pipe = crtc->pipe;
+	power_domain = POWER_DOMAIN_PIPE(pipe);
+	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
+		return;
 
-		power_domain = POWER_DOMAIN_PIPE(pipe);
-		if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
-			continue;
+	for_each_plane_id_on_crtc(crtc, plane_id)
+		skl_ddb_get_hw_plane_state(dev_priv, pipe,
+					   plane_id,
+					   &ddb_y[plane_id],
+					   &ddb_uv[plane_id]);
 
-		for_each_plane_id_on_crtc(crtc, plane_id)
-			skl_ddb_get_hw_plane_state(dev_priv, pipe,
-						   plane_id, ddb);
+	intel_display_power_put(dev_priv, power_domain);
+}
 
-		intel_display_power_put(dev_priv, power_domain);
-	}
+void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
+			  struct skl_ddb_allocation *ddb /* out */)
+{
+	ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
 }
 
 /*
@@ -4410,7 +4410,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 	struct drm_crtc *crtc = cstate->base.crtc;
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	enum pipe pipe = intel_crtc->pipe;
 	struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
 	uint16_t alloc_size, start;
 	uint16_t minimum[I915_MAX_PLANES] = {};
@@ -4423,8 +4422,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 	uint16_t total_min_blocks = 0;
 
 	/* Clear the partitioning for disabled planes. */
-	memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
-	memset(ddb->uv_plane[pipe], 0, sizeof(ddb->uv_plane[pipe]));
+	memset(cstate->wm.skl.plane_ddb_y, 0, sizeof(cstate->wm.skl.plane_ddb_y));
+	memset(cstate->wm.skl.plane_ddb_uv, 0, sizeof(cstate->wm.skl.plane_ddb_uv));
 
 	if (WARN_ON(!state))
 		return 0;
@@ -4471,8 +4470,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 	}
 
 	alloc_size -= total_min_blocks;
-	ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
-	ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
+	cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
+	cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
 
 	/*
 	 * 2. Distribute the remaining space in proportion to the amount of
@@ -4503,8 +4502,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 
 		/* Leave disabled planes at (0,0) */
 		if (data_rate) {
-			ddb->plane[pipe][plane_id].start = start;
-			ddb->plane[pipe][plane_id].end = start + plane_blocks;
+			cstate->wm.skl.plane_ddb_y[plane_id].start = start;
+			cstate->wm.skl.plane_ddb_y[plane_id].end = start + plane_blocks;
 		}
 
 		start += plane_blocks;
@@ -4519,8 +4518,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 		WARN_ON(INTEL_GEN(dev_priv) >= 11 && uv_plane_blocks);
 
 		if (uv_data_rate) {
-			ddb->uv_plane[pipe][plane_id].start = start;
-			ddb->uv_plane[pipe][plane_id].end =
+			cstate->wm.skl.plane_ddb_uv[plane_id].start = start;
+			cstate->wm.skl.plane_ddb_uv[plane_id].end =
 				start + uv_plane_blocks;
 		}
 
@@ -4978,16 +4977,13 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
 	}
 }
 
-static int skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
-				     struct intel_crtc_state *crtc_state,
+static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
 				     const struct intel_plane_state *plane_state,
 				     enum plane_id plane_id, int color_plane)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
+	u16 ddb_blocks = skl_ddb_entry_size(&crtc_state->wm.skl.plane_ddb_y[plane_id]);
 	struct skl_wm_params wm_params;
-	enum pipe pipe = plane->pipe;
-	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
 	int ret;
 
 	ret = skl_compute_plane_wm_params(crtc_state, plane_state,
@@ -5005,16 +5001,13 @@ static int skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
 	return 0;
 }
 
-static int skl_build_plane_wm_uv(struct skl_ddb_allocation *ddb,
-				 struct intel_crtc_state *crtc_state,
+static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
 				 const struct intel_plane_state *plane_state,
 				 enum plane_id plane_id)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
+	u16 ddb_blocks = skl_ddb_entry_size(&crtc_state->wm.skl.plane_ddb_uv[plane_id]);
 	struct skl_wm_params wm_params;
-	enum pipe pipe = plane->pipe;
-	uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->uv_plane[pipe][plane_id]);
 	int ret;
 
 	wm->is_planar = true;
@@ -5033,8 +5026,7 @@ static int skl_build_plane_wm_uv(struct skl_ddb_allocation *ddb,
 	return 0;
 }
 
-static int skl_build_plane_wm(struct skl_ddb_allocation *ddb,
-			      struct skl_pipe_wm *pipe_wm,
+static int skl_build_plane_wm(struct skl_pipe_wm *pipe_wm,
 			      struct intel_crtc_state *crtc_state,
 			      const struct intel_plane_state *plane_state)
 {
@@ -5046,13 +5038,13 @@ static int skl_build_plane_wm(struct skl_ddb_allocation *ddb,
 	if (!intel_wm_plane_visible(crtc_state, plane_state))
 		return 0;
 
-	ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
+	ret = skl_build_plane_wm_single(crtc_state, plane_state,
 					plane_id, 0);
 	if (ret)
 		return ret;
 
 	if (fb->format->is_yuv && fb->format->num_planes > 1) {
-		ret = skl_build_plane_wm_uv(ddb, crtc_state, plane_state,
+		ret = skl_build_plane_wm_uv(crtc_state, plane_state,
 					    plane_id);
 		if (ret)
 			return ret;
@@ -5061,8 +5053,7 @@ static int skl_build_plane_wm(struct skl_ddb_allocation *ddb,
 	return 0;
 }
 
-static int icl_build_plane_wm(struct skl_ddb_allocation *ddb,
-			      struct skl_pipe_wm *pipe_wm,
+static int icl_build_plane_wm(struct skl_pipe_wm *pipe_wm,
 			      struct intel_crtc_state *crtc_state,
 			      const struct intel_plane_state *plane_state)
 {
@@ -5081,17 +5072,17 @@ static int icl_build_plane_wm(struct skl_ddb_allocation *ddb,
 		WARN_ON(!fb->format->is_yuv ||
 			fb->format->num_planes == 1);
 
-		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
+		ret = skl_build_plane_wm_single(crtc_state, plane_state,
 						y_plane_id, 0);
 		if (ret)
 			return ret;
 
-		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
+		ret = skl_build_plane_wm_single(crtc_state, plane_state,
 						plane_id, 1);
 		if (ret)
 			return ret;
 	} else if (intel_wm_plane_visible(crtc_state, plane_state)) {
-		ret = skl_build_plane_wm_single(ddb, crtc_state, plane_state,
+		ret = skl_build_plane_wm_single(crtc_state, plane_state,
 						plane_id, 0);
 		if (ret)
 			return ret;
@@ -5101,7 +5092,6 @@ static int icl_build_plane_wm(struct skl_ddb_allocation *ddb,
 }
 
 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
-			     struct skl_ddb_allocation *ddb,
 			     struct skl_pipe_wm *pipe_wm)
 {
 	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
@@ -5121,10 +5111,10 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
 						to_intel_plane_state(pstate);
 
 		if (INTEL_GEN(dev_priv) >= 11)
-			ret = icl_build_plane_wm(ddb, pipe_wm,
+			ret = icl_build_plane_wm(pipe_wm,
 						 cstate, intel_pstate);
 		else
-			ret = skl_build_plane_wm(ddb, pipe_wm,
+			ret = skl_build_plane_wm(pipe_wm,
 						 cstate, intel_pstate);
 		if (ret)
 			return ret;
@@ -5140,9 +5130,9 @@ static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
 				const struct skl_ddb_entry *entry)
 {
 	if (entry->end)
-		I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
+		I915_WRITE_FW(reg, (entry->end - 1) << 16 | entry->start);
 	else
-		I915_WRITE(reg, 0);
+		I915_WRITE_FW(reg, 0);
 }
 
 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
@@ -5157,19 +5147,22 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv,
 		val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
 	}
 
-	I915_WRITE(reg, val);
+	I915_WRITE_FW(reg, val);
 }
 
-static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
-			       const struct skl_plane_wm *wm,
-			       const struct skl_ddb_allocation *ddb,
-			       enum plane_id plane_id)
+void skl_write_plane_wm(struct intel_plane *plane,
+			const struct intel_crtc_state *crtc_state)
 {
-	struct drm_crtc *crtc = &intel_crtc->base;
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	int level, max_level = ilk_wm_max_level(dev_priv);
-	enum pipe pipe = intel_crtc->pipe;
+	enum plane_id plane_id = plane->id;
+	enum pipe pipe = plane->pipe;
+	const struct skl_plane_wm *wm =
+		&crtc_state->wm.skl.optimal.planes[plane_id];
+	const struct skl_ddb_entry *ddb_y =
+		&crtc_state->wm.skl.plane_ddb_y[plane_id];
+	const struct skl_ddb_entry *ddb_uv =
+		&crtc_state->wm.skl.plane_ddb_uv[plane_id];
 
 	for (level = 0; level <= max_level; level++) {
 		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
@@ -5178,29 +5171,32 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
 	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
 			   &wm->trans_wm);
 
-	if (wm->is_planar && INTEL_GEN(dev_priv) < 11) {
-		skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
-				    &ddb->uv_plane[pipe][plane_id]);
+	if (INTEL_GEN(dev_priv) >= 11) {
 		skl_ddb_entry_write(dev_priv,
-				    PLANE_NV12_BUF_CFG(pipe, plane_id),
-				    &ddb->plane[pipe][plane_id]);
-	} else {
-		skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
-				    &ddb->plane[pipe][plane_id]);
-		if (INTEL_GEN(dev_priv) < 11)
-			I915_WRITE(PLANE_NV12_BUF_CFG(pipe, plane_id), 0x0);
+				    PLANE_BUF_CFG(pipe, plane_id), ddb_y);
+		return;
 	}
+
+	if (wm->is_planar)
+		swap(ddb_y, ddb_uv);
+
+	skl_ddb_entry_write(dev_priv,
+			    PLANE_BUF_CFG(pipe, plane_id), ddb_y);
+	skl_ddb_entry_write(dev_priv,
+			    PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_uv);
 }
 
-static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
-				const struct skl_plane_wm *wm,
-				const struct skl_ddb_allocation *ddb)
+void skl_write_cursor_wm(struct intel_plane *plane,
+			 const struct intel_crtc_state *crtc_state)
 {
-	struct drm_crtc *crtc = &intel_crtc->base;
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	int level, max_level = ilk_wm_max_level(dev_priv);
-	enum pipe pipe = intel_crtc->pipe;
+	enum plane_id plane_id = plane->id;
+	enum pipe pipe = plane->pipe;
+	const struct skl_plane_wm *wm =
+		&crtc_state->wm.skl.optimal.planes[plane_id];
+	const struct skl_ddb_entry *ddb =
+		&crtc_state->wm.skl.plane_ddb_y[plane_id];
 
 	for (level = 0; level <= max_level; level++) {
 		skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
@@ -5208,22 +5204,30 @@ static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
 	}
 	skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
 
-	skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
-			    &ddb->plane[pipe][PLANE_CURSOR]);
+	skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), ddb);
 }
 
 bool skl_wm_level_equals(const struct skl_wm_level *l1,
 			 const struct skl_wm_level *l2)
 {
-	if (l1->plane_en != l2->plane_en)
-		return false;
+	return l1->plane_en == l2->plane_en &&
+		l1->plane_res_l == l2->plane_res_l &&
+		l1->plane_res_b == l2->plane_res_b;
+}
 
-	/* If both planes aren't enabled, the rest shouldn't matter */
-	if (!l1->plane_en)
-		return true;
+static bool skl_plane_wm_equals(struct drm_i915_private *dev_priv,
+				const struct skl_plane_wm *wm1,
+				const struct skl_plane_wm *wm2)
+{
+	int level, max_level = ilk_wm_max_level(dev_priv);
 
-	return (l1->plane_res_l == l2->plane_res_l &&
-		l1->plane_res_b == l2->plane_res_b);
+	for (level = 0; level <= max_level; level++) {
+		if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level]) ||
+		    !skl_wm_level_equals(&wm1->uv_wm[level], &wm2->uv_wm[level]))
+			return false;
+	}
+
+	return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm);
 }
 
 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
@@ -5250,13 +5254,12 @@ bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
 			      const struct skl_pipe_wm *old_pipe_wm,
 			      struct skl_pipe_wm *pipe_wm, /* out */
-			      struct skl_ddb_allocation *ddb, /* out */
 			      bool *changed /* out */)
 {
 	struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
 	int ret;
 
-	ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
+	ret = skl_build_pipe_wm(intel_cstate, pipe_wm);
 	if (ret)
 		return ret;
 
@@ -5282,42 +5285,29 @@ pipes_modified(struct drm_atomic_state *state)
 }
 
 static int
-skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
+skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
+			    struct intel_crtc_state *new_crtc_state)
 {
-	struct drm_atomic_state *state = cstate->base.state;
-	struct drm_device *dev = state->dev;
-	struct drm_crtc *crtc = cstate->base.crtc;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-	struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
-	struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
-	struct drm_plane *plane;
-	enum pipe pipe = intel_crtc->pipe;
+	struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->base.state);
+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_plane *plane;
 
-	drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
-		struct drm_plane_state *plane_state;
-		struct intel_plane *linked;
-		enum plane_id plane_id = to_intel_plane(plane)->id;
+	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+		struct intel_plane_state *plane_state;
+		enum plane_id plane_id = plane->id;
 
-		if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
-					&new_ddb->plane[pipe][plane_id]) &&
-		    skl_ddb_entry_equal(&cur_ddb->uv_plane[pipe][plane_id],
-					&new_ddb->uv_plane[pipe][plane_id]))
+		if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
+					&new_crtc_state->wm.skl.plane_ddb_y[plane_id]) &&
+		    skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_uv[plane_id],
+					&new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
 			continue;
 
-		plane_state = drm_atomic_get_plane_state(state, plane);
+		plane_state = intel_atomic_get_plane_state(state, plane);
 		if (IS_ERR(plane_state))
 			return PTR_ERR(plane_state);
 
-		/* Make sure linked plane is updated too */
-		linked = to_intel_plane_state(plane_state)->linked_plane;
-		if (!linked)
-			continue;
-
-		plane_state = drm_atomic_get_plane_state(state, &linked->base);
-		if (IS_ERR(plane_state))
-			return PTR_ERR(plane_state);
+		new_crtc_state->update_planes |= BIT(plane_id);
 	}
 
 	return 0;
@@ -5329,18 +5319,21 @@ skl_compute_ddb(struct drm_atomic_state *state)
 	const struct drm_i915_private *dev_priv = to_i915(state->dev);
 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
 	struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
+	struct intel_crtc_state *old_crtc_state;
+	struct intel_crtc_state *new_crtc_state;
 	struct intel_crtc *crtc;
-	struct intel_crtc_state *cstate;
 	int ret, i;
 
 	memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
 
-	for_each_new_intel_crtc_in_state(intel_state, crtc, cstate, i) {
-		ret = skl_allocate_pipe_ddb(cstate, ddb);
+	for_each_oldnew_intel_crtc_in_state(intel_state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		ret = skl_allocate_pipe_ddb(new_crtc_state, ddb);
 		if (ret)
 			return ret;
 
-		ret = skl_ddb_add_affected_planes(cstate);
+		ret = skl_ddb_add_affected_planes(old_crtc_state,
+						  new_crtc_state);
 		if (ret)
 			return ret;
 	}
@@ -5349,36 +5342,29 @@ skl_compute_ddb(struct drm_atomic_state *state)
 }
 
 static void
-skl_print_wm_changes(const struct drm_atomic_state *state)
+skl_print_wm_changes(struct intel_atomic_state *state)
 {
-	const struct drm_device *dev = state->dev;
-	const struct drm_i915_private *dev_priv = to_i915(dev);
-	const struct intel_atomic_state *intel_state =
-		to_intel_atomic_state(state);
-	const struct drm_crtc *crtc;
-	const struct drm_crtc_state *cstate;
-	const struct intel_plane *intel_plane;
-	const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
-	const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	const struct intel_crtc_state *old_crtc_state;
+	const struct intel_crtc_state *new_crtc_state;
+	struct intel_plane *plane;
+	struct intel_crtc *crtc;
 	int i;
 
-	for_each_new_crtc_in_state(state, crtc, cstate, i) {
-		const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-		enum pipe pipe = intel_crtc->pipe;
-
-		for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
-			enum plane_id plane_id = intel_plane->id;
+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+			enum plane_id plane_id = plane->id;
 			const struct skl_ddb_entry *old, *new;
 
-			old = &old_ddb->plane[pipe][plane_id];
-			new = &new_ddb->plane[pipe][plane_id];
+			old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];
+			new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];
 
 			if (skl_ddb_entry_equal(old, new))
 				continue;
 
 			DRM_DEBUG_KMS("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
-				      intel_plane->base.base.id,
-				      intel_plane->base.name,
+				      plane->base.base.id, plane->base.name,
 				      old->start, old->end,
 				      new->start, new->end);
 		}
@@ -5475,6 +5461,66 @@ skl_ddb_add_affected_pipes(struct drm_atomic_state *state, bool *changed)
 	return 0;
 }
 
+/*
+ * To make sure the cursor watermark registers are always consistent
+ * with our computed state the following scenario needs special
+ * treatment:
+ *
+ * 1. enable cursor
+ * 2. move cursor entirely offscreen
+ * 3. disable cursor
+ *
+ * Step 2. does call .disable_plane() but does not zero the watermarks
+ * (since we consider an offscreen cursor still active for the purposes
+ * of watermarks). Step 3. would not normally call .disable_plane()
+ * because the actual plane visibility isn't changing, and we don't
+ * deallocate the cursor ddb until the pipe gets disabled. So we must
+ * force step 3. to call .disable_plane() to update the watermark
+ * registers properly.
+ *
+ * Other planes do not suffer from this issues as their watermarks are
+ * calculated based on the actual plane visibility. The only time this
+ * can trigger for the other planes is during the initial readout as the
+ * default value of the watermarks registers is not zero.
+ */
+static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
+				      struct intel_crtc *crtc)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct intel_crtc_state *old_crtc_state =
+		intel_atomic_get_old_crtc_state(state, crtc);
+	struct intel_crtc_state *new_crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	struct intel_plane *plane;
+
+	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+		struct intel_plane_state *plane_state;
+		enum plane_id plane_id = plane->id;
+
+		/*
+		 * Force a full wm update for every plane on modeset.
+		 * Required because the reset value of the wm registers
+		 * is non-zero, whereas we want all disabled planes to
+		 * have zero watermarks. So if we turn off the relevant
+		 * power well the hardware state will go out of sync
+		 * with the software state.
+		 */
+		if (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) &&
+		    skl_plane_wm_equals(dev_priv,
+					&old_crtc_state->wm.skl.optimal.planes[plane_id],
+					&new_crtc_state->wm.skl.optimal.planes[plane_id]))
+			continue;
+
+		plane_state = intel_atomic_get_plane_state(state, plane);
+		if (IS_ERR(plane_state))
+			return PTR_ERR(plane_state);
+
+		new_crtc_state->update_planes |= BIT(plane_id);
+	}
+
+	return 0;
+}
+
 static int
 skl_compute_wm(struct drm_atomic_state *state)
 {
@@ -5514,8 +5560,12 @@ skl_compute_wm(struct drm_atomic_state *state)
 			&to_intel_crtc_state(crtc->state)->wm.skl.optimal;
 
 		pipe_wm = &intel_cstate->wm.skl.optimal;
-		ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
-					 &results->ddb, &changed);
+		ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm, &changed);
+		if (ret)
+			return ret;
+
+		ret = skl_wm_add_affected_planes(intel_state,
+						 to_intel_crtc(crtc));
 		if (ret)
 			return ret;
 
@@ -5529,7 +5579,7 @@ skl_compute_wm(struct drm_atomic_state *state)
 		intel_cstate->update_wm_pre = true;
 	}
 
-	skl_print_wm_changes(state);
+	skl_print_wm_changes(intel_state);
 
 	return 0;
 }
@@ -5540,23 +5590,12 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
 	struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
-	const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
 	enum pipe pipe = crtc->pipe;
-	enum plane_id plane_id;
 
 	if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
 		return;
 
 	I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
-
-	for_each_plane_id_on_crtc(crtc, plane_id) {
-		if (plane_id != PLANE_CURSOR)
-			skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id],
-					   ddb, plane_id);
-		else
-			skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id],
-					    ddb);
-	}
 }
 
 static void skl_initial_wm(struct intel_atomic_state *state,
@@ -5566,8 +5605,6 @@ static void skl_initial_wm(struct intel_atomic_state *state,
 	struct drm_device *dev = intel_crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct skl_ddb_values *results = &state->wm_results;
-	struct skl_ddb_values *hw_vals = &dev_priv->wm.skl_hw;
-	enum pipe pipe = intel_crtc->pipe;
 
 	if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
 		return;
@@ -5577,11 +5614,6 @@ static void skl_initial_wm(struct intel_atomic_state *state,
 	if (cstate->base.active_changed)
 		skl_atomic_update_crtc_wm(state, cstate);
 
-	memcpy(hw_vals->ddb.uv_plane[pipe], results->ddb.uv_plane[pipe],
-	       sizeof(hw_vals->ddb.uv_plane[pipe]));
-	memcpy(hw_vals->ddb.plane[pipe], results->ddb.plane[pipe],
-	       sizeof(hw_vals->ddb.plane[pipe]));
-
 	mutex_unlock(&dev_priv->wm.wm_mutex);
 }
 
@@ -5732,13 +5764,6 @@ void skl_wm_get_hw_state(struct drm_device *dev)
 	if (dev_priv->active_crtcs) {
 		/* Fully recompute DDB on first atomic commit */
 		dev_priv->wm.distrust_bios_wm = true;
-	} else {
-		/*
-		 * Easy/common case; just sanitize DDB now if everything off
-		 * Keep dbuf slice info intact
-		 */
-		memset(ddb->plane, 0, sizeof(ddb->plane));
-		memset(ddb->uv_plane, 0, sizeof(ddb->uv_plane));
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index e5da2fe3bdae..32df604e90b6 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -542,6 +542,8 @@ skl_program_plane(struct intel_plane *plane,
 	if (fb->format->is_yuv && icl_is_hdr_plane(plane))
 		icl_program_input_csc_coeff(crtc_state, plane_state);
 
+	skl_write_plane_wm(plane, crtc_state);
+
 	I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
 	I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk);
 	I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax);
@@ -604,6 +606,8 @@ skl_disable_plane(struct intel_plane *plane,
 
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
+	skl_write_plane_wm(plane, crtc_state);
+
 	I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
 	I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
 
-- 
2.18.1

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[PATCH v2 11/13] drm/i915: Commit skl+ planes in an order that avoids ddb overlaps

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

skl+ can go belly up if there are overlapping ddb allocations between
planes. If we could absolutely guarantee that we can perform the atomic
update within a single frame we shouldn't have to worry about this. But
we can't rely on that so let's steal the ddb overlap check trick from
skl_update_crtcs() and apply it to the plane updates. Since each step
of the sequence is free from ddb overlaps we don't have to worry about
a vblank sneaking up on us in the middle of the sequence. The partial
state that gets latched by the hardware will be safe. And unlike
skl_update_crtcs() we don't have to intoduce any extra vblank waits
on accoung of only having to worry about a single pipe.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_atomic_plane.c | 96 ++++++++++++++++++++---
 drivers/gpu/drm/i915/intel_display.c      |  7 +-
 drivers/gpu/drm/i915/intel_drv.h          |  8 +-
 3 files changed, 93 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 69fc7010190c..ff8d3e577bbf 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -169,24 +169,75 @@ static int intel_plane_atomic_check(struct drm_plane *plane,
 						   to_intel_plane_state(new_plane_state));
 }
 
-void intel_update_planes_on_crtc(struct intel_atomic_state *old_state,
-				 struct intel_crtc *crtc,
-				 struct intel_crtc_state *old_crtc_state,
-				 struct intel_crtc_state *new_crtc_state)
+static struct intel_plane *
+skl_next_plane_to_commit(struct intel_atomic_state *state,
+			 struct intel_crtc *crtc,
+			 struct skl_ddb_entry entries_y[I915_MAX_PLANES],
+			 struct skl_ddb_entry entries_uv[I915_MAX_PLANES],
+			 unsigned int *update_mask)
 {
-	u32 update_mask = new_crtc_state->update_planes;
-	struct intel_plane_state *new_plane_state;
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	struct intel_plane_state *plane_state;
 	struct intel_plane *plane;
 	int i;
 
-	for_each_new_intel_plane_in_state(old_state, plane, new_plane_state, i) {
+	if (*update_mask == 0)
+		return NULL;
+
+	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+		enum plane_id plane_id = plane->id;
+
 		if (crtc->pipe != plane->pipe ||
-		    !(update_mask & BIT(plane->id)))
+		    !(*update_mask & BIT(plane_id)))
 			continue;
 
+		if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
+						entries_y,
+						I915_MAX_PLANES, plane_id) ||
+		    skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_uv[plane_id],
+						entries_uv,
+						I915_MAX_PLANES, plane_id))
+			continue;
+
+		*update_mask &= ~BIT(plane_id);
+		entries_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
+		entries_uv[plane_id] = crtc_state->wm.skl.plane_ddb_uv[plane_id];
+
+		return plane;
+	}
+
+	/* should never happen */
+	WARN_ON(1);
+
+	return NULL;
+}
+
+void skl_update_planes_on_crtc(struct intel_atomic_state *state,
+			       struct intel_crtc *crtc)
+{
+	struct intel_crtc_state *old_crtc_state =
+		intel_atomic_get_old_crtc_state(state, crtc);
+	struct intel_crtc_state *new_crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	struct skl_ddb_entry entries_y[I915_MAX_PLANES];
+	struct skl_ddb_entry entries_uv[I915_MAX_PLANES];
+	u32 update_mask = new_crtc_state->update_planes;
+	struct intel_plane *plane;
+
+	memcpy(entries_y, old_crtc_state->wm.skl.plane_ddb_y,
+	       sizeof(old_crtc_state->wm.skl.plane_ddb_y));
+	memcpy(entries_uv, old_crtc_state->wm.skl.plane_ddb_uv,
+	       sizeof(old_crtc_state->wm.skl.plane_ddb_uv));
+
+	while ((plane = skl_next_plane_to_commit(state, crtc,
+						 entries_y, entries_uv,
+						 &update_mask))) {
+		struct intel_plane_state *new_plane_state =
+			intel_atomic_get_new_plane_state(state, plane);
+
 		if (new_plane_state->base.visible) {
 			trace_intel_update_plane(&plane->base, crtc);
-
 			plane->update_plane(plane, new_crtc_state, new_plane_state);
 		} else if (new_plane_state->slave) {
 			struct intel_plane *master =
@@ -202,14 +253,37 @@ void intel_update_planes_on_crtc(struct intel_atomic_state *old_state,
 			 * plane_state.
 			 */
 			new_plane_state =
-				intel_atomic_get_new_plane_state(old_state, master);
+				intel_atomic_get_new_plane_state(state, master);
 
 			trace_intel_update_plane(&plane->base, crtc);
-
 			plane->update_slave(plane, new_crtc_state, new_plane_state);
 		} else {
 			trace_intel_disable_plane(&plane->base, crtc);
+			plane->disable_plane(plane, new_crtc_state);
+		}
+	}
+}
 
+void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
+				struct intel_crtc *crtc)
+{
+	struct intel_crtc_state *new_crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	u32 update_mask = new_crtc_state->update_planes;
+	struct intel_plane_state *new_plane_state;
+	struct intel_plane *plane;
+	int i;
+
+	for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
+		if (crtc->pipe != plane->pipe ||
+		    !(update_mask & BIT(plane->id)))
+			continue;
+
+		if (new_plane_state->base.visible) {
+			trace_intel_update_plane(&plane->base, crtc);
+			plane->update_plane(plane, new_crtc_state, new_plane_state);
+		} else {
+			trace_intel_disable_plane(&plane->base, crtc);
 			plane->disable_plane(plane, new_crtc_state);
 		}
 	}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2981cea3704a..114b2f3c6274 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12661,7 +12661,6 @@ static void intel_update_crtc(struct drm_crtc *crtc,
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct intel_crtc_state *old_intel_cstate = to_intel_crtc_state(old_crtc_state);
 	struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
 	bool modeset = needs_modeset(new_crtc_state);
 	struct intel_plane_state *new_plane_state =
@@ -12684,8 +12683,10 @@ static void intel_update_crtc(struct drm_crtc *crtc,
 
 	intel_begin_crtc_commit(crtc, old_crtc_state);
 
-	intel_update_planes_on_crtc(to_intel_atomic_state(state), intel_crtc,
-				    old_intel_cstate, pipe_config);
+	if (INTEL_GEN(dev_priv) >= 9)
+		skl_update_planes_on_crtc(to_intel_atomic_state(state), intel_crtc);
+	else
+		i9xx_update_planes_on_crtc(to_intel_atomic_state(state), intel_crtc);
 
 	intel_finish_crtc_commit(crtc, old_crtc_state);
 }
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 4a9af09c483a..2af994942fa7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2299,10 +2299,10 @@ struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
 void intel_plane_destroy_state(struct drm_plane *plane,
 			       struct drm_plane_state *state);
 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
-void intel_update_planes_on_crtc(struct intel_atomic_state *old_state,
-				 struct intel_crtc *crtc,
-				 struct intel_crtc_state *old_crtc_state,
-				 struct intel_crtc_state *new_crtc_state);
+void skl_update_planes_on_crtc(struct intel_atomic_state *state,
+			       struct intel_crtc *crtc);
+void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
+				struct intel_crtc *crtc);
 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
 					struct intel_crtc_state *crtc_state,
 					const struct intel_plane_state *old_plane_state,
-- 
2.18.1

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Re: [PATCH v2 11/13] drm/i915: Commit skl+ planes in an order that avoids ddb overlaps

[Matt Roper]

On Wed, Nov 14, 2018 at 11:07:27PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> skl+ can go belly up if there are overlapping ddb allocations between
> planes. If we could absolutely guarantee that we can perform the atomic
> update within a single frame we shouldn't have to worry about this. But
> we can't rely on that so let's steal the ddb overlap check trick from
> skl_update_crtcs() and apply it to the plane updates. Since each step
> of the sequence is free from ddb overlaps we don't have to worry about
> a vblank sneaking up on us in the middle of the sequence. The partial
> state that gets latched by the hardware will be safe. And unlike
> skl_update_crtcs() we don't have to intoduce any extra vblank waits
> on accoung of only having to worry about a single pipe.

Minor typo on 'account' here.

Otherwise, patch looks good.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_atomic_plane.c | 96 ++++++++++++++++++++---
>  drivers/gpu/drm/i915/intel_display.c      |  7 +-
>  drivers/gpu/drm/i915/intel_drv.h          |  8 +-
>  3 files changed, 93 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index 69fc7010190c..ff8d3e577bbf 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -169,24 +169,75 @@ static int intel_plane_atomic_check(struct drm_plane *plane,
>  						   to_intel_plane_state(new_plane_state));
>  }
>  
> -void intel_update_planes_on_crtc(struct intel_atomic_state *old_state,
> -				 struct intel_crtc *crtc,
> -				 struct intel_crtc_state *old_crtc_state,
> -				 struct intel_crtc_state *new_crtc_state)
> +static struct intel_plane *
> +skl_next_plane_to_commit(struct intel_atomic_state *state,
> +			 struct intel_crtc *crtc,
> +			 struct skl_ddb_entry entries_y[I915_MAX_PLANES],
> +			 struct skl_ddb_entry entries_uv[I915_MAX_PLANES],
> +			 unsigned int *update_mask)
>  {
> -	u32 update_mask = new_crtc_state->update_planes;
> -	struct intel_plane_state *new_plane_state;
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	struct intel_plane_state *plane_state;
>  	struct intel_plane *plane;
>  	int i;
>  
> -	for_each_new_intel_plane_in_state(old_state, plane, new_plane_state, i) {
> +	if (*update_mask == 0)
> +		return NULL;
> +
> +	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> +		enum plane_id plane_id = plane->id;
> +
>  		if (crtc->pipe != plane->pipe ||
> -		    !(update_mask & BIT(plane->id)))
> +		    !(*update_mask & BIT(plane_id)))
>  			continue;
>  
> +		if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
> +						entries_y,
> +						I915_MAX_PLANES, plane_id) ||
> +		    skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_uv[plane_id],
> +						entries_uv,
> +						I915_MAX_PLANES, plane_id))
> +			continue;
> +
> +		*update_mask &= ~BIT(plane_id);
> +		entries_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
> +		entries_uv[plane_id] = crtc_state->wm.skl.plane_ddb_uv[plane_id];
> +
> +		return plane;
> +	}
> +
> +	/* should never happen */
> +	WARN_ON(1);
> +
> +	return NULL;
> +}
> +
> +void skl_update_planes_on_crtc(struct intel_atomic_state *state,
> +			       struct intel_crtc *crtc)
> +{
> +	struct intel_crtc_state *old_crtc_state =
> +		intel_atomic_get_old_crtc_state(state, crtc);
> +	struct intel_crtc_state *new_crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	struct skl_ddb_entry entries_y[I915_MAX_PLANES];
> +	struct skl_ddb_entry entries_uv[I915_MAX_PLANES];
> +	u32 update_mask = new_crtc_state->update_planes;
> +	struct intel_plane *plane;
> +
> +	memcpy(entries_y, old_crtc_state->wm.skl.plane_ddb_y,
> +	       sizeof(old_crtc_state->wm.skl.plane_ddb_y));
> +	memcpy(entries_uv, old_crtc_state->wm.skl.plane_ddb_uv,
> +	       sizeof(old_crtc_state->wm.skl.plane_ddb_uv));
> +
> +	while ((plane = skl_next_plane_to_commit(state, crtc,
> +						 entries_y, entries_uv,
> +						 &update_mask))) {
> +		struct intel_plane_state *new_plane_state =
> +			intel_atomic_get_new_plane_state(state, plane);
> +
>  		if (new_plane_state->base.visible) {
>  			trace_intel_update_plane(&plane->base, crtc);
> -
>  			plane->update_plane(plane, new_crtc_state, new_plane_state);
>  		} else if (new_plane_state->slave) {
>  			struct intel_plane *master =
> @@ -202,14 +253,37 @@ void intel_update_planes_on_crtc(struct intel_atomic_state *old_state,
>  			 * plane_state.
>  			 */
>  			new_plane_state =
> -				intel_atomic_get_new_plane_state(old_state, master);
> +				intel_atomic_get_new_plane_state(state, master);
>  
>  			trace_intel_update_plane(&plane->base, crtc);
> -
>  			plane->update_slave(plane, new_crtc_state, new_plane_state);
>  		} else {
>  			trace_intel_disable_plane(&plane->base, crtc);
> +			plane->disable_plane(plane, new_crtc_state);
> +		}
> +	}
> +}
>  
> +void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
> +				struct intel_crtc *crtc)
> +{
> +	struct intel_crtc_state *new_crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	u32 update_mask = new_crtc_state->update_planes;
> +	struct intel_plane_state *new_plane_state;
> +	struct intel_plane *plane;
> +	int i;
> +
> +	for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
> +		if (crtc->pipe != plane->pipe ||
> +		    !(update_mask & BIT(plane->id)))
> +			continue;
> +
> +		if (new_plane_state->base.visible) {
> +			trace_intel_update_plane(&plane->base, crtc);
> +			plane->update_plane(plane, new_crtc_state, new_plane_state);
> +		} else {
> +			trace_intel_disable_plane(&plane->base, crtc);
>  			plane->disable_plane(plane, new_crtc_state);
>  		}
>  	}
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2981cea3704a..114b2f3c6274 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12661,7 +12661,6 @@ static void intel_update_crtc(struct drm_crtc *crtc,
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	struct intel_crtc_state *old_intel_cstate = to_intel_crtc_state(old_crtc_state);
>  	struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
>  	bool modeset = needs_modeset(new_crtc_state);
>  	struct intel_plane_state *new_plane_state =
> @@ -12684,8 +12683,10 @@ static void intel_update_crtc(struct drm_crtc *crtc,
>  
>  	intel_begin_crtc_commit(crtc, old_crtc_state);
>  
> -	intel_update_planes_on_crtc(to_intel_atomic_state(state), intel_crtc,
> -				    old_intel_cstate, pipe_config);
> +	if (INTEL_GEN(dev_priv) >= 9)
> +		skl_update_planes_on_crtc(to_intel_atomic_state(state), intel_crtc);
> +	else
> +		i9xx_update_planes_on_crtc(to_intel_atomic_state(state), intel_crtc);
>  
>  	intel_finish_crtc_commit(crtc, old_crtc_state);
>  }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 4a9af09c483a..2af994942fa7 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -2299,10 +2299,10 @@ struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
>  void intel_plane_destroy_state(struct drm_plane *plane,
>  			       struct drm_plane_state *state);
>  extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
> -void intel_update_planes_on_crtc(struct intel_atomic_state *old_state,
> -				 struct intel_crtc *crtc,
> -				 struct intel_crtc_state *old_crtc_state,
> -				 struct intel_crtc_state *new_crtc_state);
> +void skl_update_planes_on_crtc(struct intel_atomic_state *state,
> +			       struct intel_crtc *crtc);
> +void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
> +				struct intel_crtc *crtc);
>  int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
>  					struct intel_crtc_state *crtc_state,
>  					const struct intel_plane_state *old_plane_state,
> -- 
> 2.18.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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[PATCH v2 12/13] drm/i915: Rename the confusing 'plane_id' to 'color_plane'

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

A variable whose name is 'plane_id' is expected to be of the
enum plane_id type. In this case we have a raw int, which turns
out to refer to the plane of the framebuffer. Rename the variable
to 'color_plane' in line with the trend started earlier.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1b337004054a..395c11b8a212 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4581,7 +4581,7 @@ skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
 static int
 skl_compute_plane_wm_params(const struct intel_crtc_state *cstate,
 			    const struct intel_plane_state *intel_pstate,
-			    struct skl_wm_params *wp, int plane_id)
+			    struct skl_wm_params *wp, int color_plane)
 {
 	struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
@@ -4593,7 +4593,7 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *cstate,
 	bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
 
 	/* only NV12 format has two planes */
-	if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
+	if (color_plane == 1 && fb->format->format != DRM_FORMAT_NV12) {
 		DRM_DEBUG_KMS("Non NV12 format have single plane\n");
 		return -EINVAL;
 	}
@@ -4618,10 +4618,10 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *cstate,
 		wp->width = drm_rect_width(&intel_pstate->base.src) >> 16;
 	}
 
-	if (plane_id == 1 && wp->is_planar)
+	if (color_plane == 1 && wp->is_planar)
 		wp->width /= 2;
 
-	wp->cpp = fb->format->cpp[plane_id];
+	wp->cpp = fb->format->cpp[color_plane];
 	wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
 							     intel_pstate);
 
-- 
2.18.1

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Re: [PATCH v2 12/13] drm/i915: Rename the confusing 'plane_id' to 'color_plane'

[Matt Roper]

On Wed, Nov 14, 2018 at 11:07:28PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> A variable whose name is 'plane_id' is expected to be of the
> enum plane_id type. In this case we have a raw int, which turns
> out to refer to the plane of the framebuffer. Rename the variable
> to 'color_plane' in line with the trend started earlier.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1b337004054a..395c11b8a212 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4581,7 +4581,7 @@ skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
>  static int
>  skl_compute_plane_wm_params(const struct intel_crtc_state *cstate,
>  			    const struct intel_plane_state *intel_pstate,
> -			    struct skl_wm_params *wp, int plane_id)
> +			    struct skl_wm_params *wp, int color_plane)
>  {
>  	struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
>  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> @@ -4593,7 +4593,7 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *cstate,
>  	bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
>  
>  	/* only NV12 format has two planes */
> -	if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
> +	if (color_plane == 1 && fb->format->format != DRM_FORMAT_NV12) {
>  		DRM_DEBUG_KMS("Non NV12 format have single plane\n");
>  		return -EINVAL;
>  	}
> @@ -4618,10 +4618,10 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *cstate,
>  		wp->width = drm_rect_width(&intel_pstate->base.src) >> 16;
>  	}
>  
> -	if (plane_id == 1 && wp->is_planar)
> +	if (color_plane == 1 && wp->is_planar)
>  		wp->width /= 2;
>  
> -	wp->cpp = fb->format->cpp[plane_id];
> +	wp->cpp = fb->format->cpp[color_plane];
>  	wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
>  							     intel_pstate);
>  
> -- 
> 2.18.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
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[PATCH v2 13/13] drm/i915: Pass the plane to icl_program_input_csc_coeff()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On icl+ the plane state that gets passed to update_slave() is not
the plane state of the plane we're programming. With NV12 the
plane state would be coming from the master (UV) plane whereas
the plane we're programming is the slave (Y) plane. For that reason
we need to explicitly pass around the slave plane (or we'd have to
otherwise deduce it by checking whether we were called via
.update_plane() or .update_slave()).

In the case of icl_program_input_csc_coeff() it's actually OK to
assume that we are always the master plane because the input CSC
only exists on HDR planes which can never be a slave plane. But
for consistency let's pass in the plane explicitly anyway.

While at it drop the "_coeff" from the function name since it's
kinda redundant, and this makes the name a bit shorter :)

Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_sprite.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 0262159e7084..ee4c37a613f7 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -373,14 +373,12 @@ skl_program_scaler(struct intel_plane *plane,
 #define  BOFF(x)          (((x) & 0xffff) << 16)
 
 static void
-icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
-			    const struct intel_plane_state *plane_state)
+icl_program_input_csc(struct intel_plane *plane,
+		      const struct intel_crtc_state *crtc_state,
+		      const struct intel_plane_state *plane_state)
 {
-	struct drm_i915_private *dev_priv =
-		to_i915(plane_state->base.plane->dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
-	enum pipe pipe = crtc->pipe;
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+	enum pipe pipe = plane->pipe;
 	enum plane_id plane_id = plane->id;
 
 	static const u16 input_csc_matrix[][9] = {
@@ -540,7 +538,7 @@ skl_program_plane(struct intel_plane *plane,
 			      plane_state->color_ctl);
 
 	if (fb->format->is_yuv && icl_is_hdr_plane(plane))
-		icl_program_input_csc_coeff(crtc_state, plane_state);
+		icl_program_input_csc(plane, crtc_state, plane_state);
 
 	skl_write_plane_wm(plane, crtc_state);
 
-- 
2.18.1

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Re: [PATCH v2 13/13] drm/i915: Pass the plane to icl_program_input_csc_coeff()

[Shankar, Uma]

>-----Original Message-----
>From: Ville Syrjala [mailto:ville.syrjala@linux.intel.com]
>Sent: Thursday, November 15, 2018 2:37 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Shankar, Uma <uma.shankar@intel.com>; Maarten Lankhorst
><maarten.lankhorst@linux.intel.com>
>Subject: [PATCH v2 13/13] drm/i915: Pass the plane to
>icl_program_input_csc_coeff()
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>On icl+ the plane state that gets passed to update_slave() is not the plane state of
>the plane we're programming. With NV12 the plane state would be coming from
>the master (UV) plane whereas the plane we're programming is the slave (Y)
>plane. For that reason we need to explicitly pass around the slave plane (or we'd
>have to otherwise deduce it by checking whether we were called via
>.update_plane() or .update_slave()).
>
>In the case of icl_program_input_csc_coeff() it's actually OK to assume that we
>are always the master plane because the input CSC only exists on HDR planes
>which can never be a slave plane. But for consistency let's pass in the plane
>explicitly anyway.
>
>While at it drop the "_coeff" from the function name since it's kinda redundant,
>and this makes the name a bit shorter :)


Changes look ok to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>Cc: Uma Shankar <uma.shankar@intel.com>
>Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/intel_sprite.c | 14 ++++++--------
> 1 file changed, 6 insertions(+), 8 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_sprite.c
>b/drivers/gpu/drm/i915/intel_sprite.c
>index 0262159e7084..ee4c37a613f7 100644
>--- a/drivers/gpu/drm/i915/intel_sprite.c
>+++ b/drivers/gpu/drm/i915/intel_sprite.c
>@@ -373,14 +373,12 @@ skl_program_scaler(struct intel_plane *plane,
> #define  BOFF(x)          (((x) & 0xffff) << 16)
>
> static void
>-icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
>-			    const struct intel_plane_state *plane_state)
>+icl_program_input_csc(struct intel_plane *plane,
>+		      const struct intel_crtc_state *crtc_state,
>+		      const struct intel_plane_state *plane_state)
> {
>-	struct drm_i915_private *dev_priv =
>-		to_i915(plane_state->base.plane->dev);
>-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>-	enum pipe pipe = crtc->pipe;
>-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>+	enum pipe pipe = plane->pipe;
> 	enum plane_id plane_id = plane->id;
>
> 	static const u16 input_csc_matrix[][9] = { @@ -540,7 +538,7 @@
>skl_program_plane(struct intel_plane *plane,
> 			      plane_state->color_ctl);
>
> 	if (fb->format->is_yuv && icl_is_hdr_plane(plane))
>-		icl_program_input_csc_coeff(crtc_state, plane_state);
>+		icl_program_input_csc(plane, crtc_state, plane_state);
>
> 	skl_write_plane_wm(plane, crtc_state);
>
>--
>2.18.1

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Re: [PATCH v2 13/13] drm/i915: Pass the plane to icl_program_input_csc_coeff()

[Maarten Lankhorst]

Op 14-11-18 om 22:07 schreef Ville Syrjala:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> On icl+ the plane state that gets passed to update_slave() is not
> the plane state of the plane we're programming. With NV12 the
> plane state would be coming from the master (UV) plane whereas
> the plane we're programming is the slave (Y) plane. For that reason
> we need to explicitly pass around the slave plane (or we'd have to
> otherwise deduce it by checking whether we were called via
> .update_plane() or .update_slave()).
>
> In the case of icl_program_input_csc_coeff() it's actually OK to
> assume that we are always the master plane because the input CSC
> only exists on HDR planes which can never be a slave plane. But
> for consistency let's pass in the plane explicitly anyway.
>
> While at it drop the "_coeff" from the function name since it's
> kinda redundant, and this makes the name a bit shorter :)
>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_sprite.c | 14 ++++++--------
>  1 file changed, 6 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 0262159e7084..ee4c37a613f7 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -373,14 +373,12 @@ skl_program_scaler(struct intel_plane *plane,
>  #define  BOFF(x)          (((x) & 0xffff) << 16)
>  
>  static void
> -icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
> -			    const struct intel_plane_state *plane_state)
> +icl_program_input_csc(struct intel_plane *plane,
> +		      const struct intel_crtc_state *crtc_state,
> +		      const struct intel_plane_state *plane_state)
>  {
> -	struct drm_i915_private *dev_priv =
> -		to_i915(plane_state->base.plane->dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> -	enum pipe pipe = crtc->pipe;
> -	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +	enum pipe pipe = plane->pipe;
>  	enum plane_id plane_id = plane->id;
>  
>  	static const u16 input_csc_matrix[][9] = {
> @@ -540,7 +538,7 @@ skl_program_plane(struct intel_plane *plane,
>  			      plane_state->color_ctl);
>  
>  	if (fb->format->is_yuv && icl_is_hdr_plane(plane))
> -		icl_program_input_csc_coeff(crtc_state, plane_state);
> +		icl_program_input_csc(plane, crtc_state, plane_state);
>  
>  	skl_write_plane_wm(plane, crtc_state);
>  

Whole series looks good to me.

Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

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Re: [PATCH v2 13/13] drm/i915: Pass the plane to icl_program_input_csc_coeff()

[Matt Roper]

On Wed, Nov 14, 2018 at 11:07:29PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On icl+ the plane state that gets passed to update_slave() is not
> the plane state of the plane we're programming. With NV12 the
> plane state would be coming from the master (UV) plane whereas
> the plane we're programming is the slave (Y) plane. For that reason
> we need to explicitly pass around the slave plane (or we'd have to
> otherwise deduce it by checking whether we were called via
> .update_plane() or .update_slave()).
> 
> In the case of icl_program_input_csc_coeff() it's actually OK to
> assume that we are always the master plane because the input CSC
> only exists on HDR planes which can never be a slave plane. But
> for consistency let's pass in the plane explicitly anyway.
> 
> While at it drop the "_coeff" from the function name since it's
> kinda redundant, and this makes the name a bit shorter :)
> 
> Cc: Uma Shankar <uma.shankar@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_sprite.c | 14 ++++++--------
>  1 file changed, 6 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 0262159e7084..ee4c37a613f7 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -373,14 +373,12 @@ skl_program_scaler(struct intel_plane *plane,
>  #define  BOFF(x)          (((x) & 0xffff) << 16)
>  
>  static void
> -icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
> -			    const struct intel_plane_state *plane_state)
> +icl_program_input_csc(struct intel_plane *plane,
> +		      const struct intel_crtc_state *crtc_state,
> +		      const struct intel_plane_state *plane_state)
>  {
> -	struct drm_i915_private *dev_priv =
> -		to_i915(plane_state->base.plane->dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> -	enum pipe pipe = crtc->pipe;
> -	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +	enum pipe pipe = plane->pipe;
>  	enum plane_id plane_id = plane->id;
>  
>  	static const u16 input_csc_matrix[][9] = {
> @@ -540,7 +538,7 @@ skl_program_plane(struct intel_plane *plane,
>  			      plane_state->color_ctl);
>  
>  	if (fb->format->is_yuv && icl_is_hdr_plane(plane))
> -		icl_program_input_csc_coeff(crtc_state, plane_state);
> +		icl_program_input_csc(plane, crtc_state, plane_state);
>  
>  	skl_write_plane_wm(plane, crtc_state);
>  
> -- 
> 2.18.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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✗ Fi.CI.CHECKPATCH: warning for drm/i915: Program SKL+ watermarks/ddb more carefully (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev7)
URL   : https://patchwork.freedesktop.org/series/51878/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
5a11dbcbd5cb drm/i915: Reorganize plane register writes to make them more atomic
eb3c2f394649 drm/i915: Move single buffered plane register writes to the end
29f4a4966a76 drm/i915: Introduce crtc_state->update_planes bitmask
eae12eaba5ea drm/i915: Pass the new crtc_state to ->disable_plane()
-:153: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#153: FILE: drivers/gpu/drm/i915/intel_display.h:385:
+#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
+		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
+		      (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
+	     (__i)++) \
+		for_each_if(plane)

-:153: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'plane' - possible side-effects?
#153: FILE: drivers/gpu/drm/i915/intel_display.h:385:
+#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
+		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
+		      (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
+	     (__i)++) \
+		for_each_if(plane)

-:153: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#153: FILE: drivers/gpu/drm/i915/intel_display.h:385:
+#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
+		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
+		      (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
+	     (__i)++) \
+		for_each_if(plane)

-:157: WARNING:LONG_LINE: line over 100 characters
#157: FILE: drivers/gpu/drm/i915/intel_display.h:389:
+		      (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \

total: 0 errors, 1 warnings, 3 checks, 159 lines checked
b38354b977bd drm/i915: Fix latency==0 handling for level 0 watermark on skl+
5217f4a8480a drm/i915: Remove some useless zeroing on skl+ wm calculations
81ef2cb52f82 drm/i915: Pass the entire skl_plane_wm to skl_compute_transition_wm()
35935ddd1f7b drm/i915: Clean up skl+ vs. icl+ watermark computation
d52e2e45814c drm/i915: Don't pass dev_priv around so much
b340dfdc7c50 drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+
-:161: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#161: FILE: drivers/gpu/drm/i915/intel_display.h:418:
+#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.dev->mode_config.num_crtc && \
+		     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+		      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+		      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)++) \
+		for_each_if(crtc)

-:161: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'crtc' - possible side-effects?
#161: FILE: drivers/gpu/drm/i915/intel_display.h:418:
+#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.dev->mode_config.num_crtc && \
+		     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+		      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+		      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)++) \
+		for_each_if(crtc)

-:161: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#161: FILE: drivers/gpu/drm/i915/intel_display.h:418:
+#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.dev->mode_config.num_crtc && \
+		     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+		      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+		      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)++) \
+		for_each_if(crtc)

-:165: WARNING:LONG_LINE: line over 100 characters
#165: FILE: drivers/gpu/drm/i915/intel_display.h:422:
+		      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \

-:166: WARNING:LONG_LINE: line over 100 characters
#166: FILE: drivers/gpu/drm/i915/intel_display.h:423:
+		      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \

total: 0 errors, 2 warnings, 3 checks, 744 lines checked
21fb8c0a9512 drm/i915: Commit skl+ planes in an order that avoids ddb overlaps
cb22c9ec683c drm/i915: Rename the confusing 'plane_id' to 'color_plane'
f21a10597270 drm/i915: Pass the plane to icl_program_input_csc_coeff()

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✗ Fi.CI.SPARSE: warning for drm/i915: Program SKL+ watermarks/ddb more carefully (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev7)
URL   : https://patchwork.freedesktop.org/series/51878/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Reorganize plane register writes to make them more atomic
Okay!

Commit: drm/i915: Move single buffered plane register writes to the end
Okay!

Commit: drm/i915: Introduce crtc_state->update_planes bitmask
Okay!

Commit: drm/i915: Pass the new crtc_state to ->disable_plane()
Okay!

Commit: drm/i915: Fix latency==0 handling for level 0 watermark on skl+
Okay!

Commit: drm/i915: Remove some useless zeroing on skl+ wm calculations
Okay!

Commit: drm/i915: Pass the entire skl_plane_wm to skl_compute_transition_wm()
Okay!

Commit: drm/i915: Clean up skl+ vs. icl+ watermark computation
Okay!

Commit: drm/i915: Don't pass dev_priv around so much
Okay!

Commit: drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3716:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3713:16: warning: expression using sizeof(void)

Commit: drm/i915: Commit skl+ planes in an order that avoids ddb overlaps
Okay!

Commit: drm/i915: Rename the confusing 'plane_id' to 'color_plane'
Okay!

Commit: drm/i915: Pass the plane to icl_program_input_csc_coeff()
Okay!

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✓ Fi.CI.BAT: success for drm/i915: Program SKL+ watermarks/ddb more carefully (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev7)
URL   : https://patchwork.freedesktop.org/series/51878/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_5140 -> Patchwork_10827 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/51878/revisions/7/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10827:

  === IGT changes ===

    ==== Possible regressions ====

    igt@kms_chamelium@hdmi-edid-read:
      {fi-kbl-7567u}:     SKIP -> FAIL +3

    
    ==== Warnings ====

    igt@kms_busy@basic-flip-a:
      {fi-kbl-7567u}:     SKIP -> PASS +36

    
== Known issues ==

  Here are the changes found in Patchwork_10827 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_module_reload@basic-reload-inject:
      fi-byt-clapper:     PASS -> WARN (fdo#108688)

    igt@gem_ctx_create@basic-files:
      fi-icl-u2:          PASS -> DMESG-WARN (fdo#107724)

    igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
      fi-byt-clapper:     PASS -> FAIL (fdo#107362, fdo#103191) +1

    igt@pm_rpm@module-reload:
      fi-byt-clapper:     PASS -> FAIL (fdo#108675)

    
    ==== Possible fixes ====

    igt@debugfs_test@read_all_entries:
      {fi-kbl-7567u}:     DMESG-WARN (fdo#105602) -> PASS

    igt@drv_module_reload@basic-reload:
      fi-blb-e6850:       INCOMPLETE (fdo#107718) -> PASS

    igt@drv_module_reload@basic-reload-inject:
      {fi-kbl-7567u}:     DMESG-WARN (fdo#105602, fdo#108529) -> PASS +1

    igt@drv_selftest@live_hangcheck:
      fi-icl-u:           INCOMPLETE (fdo#108315) -> PASS

    igt@gem_exec_suspend@basic-s3:
      {fi-kbl-7567u}:     DMESG-WARN (fdo#105602, fdo#105079) -> PASS
      fi-icl-u2:          DMESG-WARN (fdo#107724) -> PASS

    igt@kms_frontbuffer_tracking@basic:
      fi-icl-u2:          FAIL (fdo#103167) -> PASS

    igt@pm_rpm@module-reload:
      {fi-kbl-7567u}:     DMESG-WARN (fdo#108529) -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#105079 https://bugs.freedesktop.org/show_bug.cgi?id=105079
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
  fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724
  fdo#108315 https://bugs.freedesktop.org/show_bug.cgi?id=108315
  fdo#108529 https://bugs.freedesktop.org/show_bug.cgi?id=108529
  fdo#108675 https://bugs.freedesktop.org/show_bug.cgi?id=108675
  fdo#108688 https://bugs.freedesktop.org/show_bug.cgi?id=108688


== Participating hosts (52 -> 47) ==

  Missing    (5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 


== Build changes ==

    * Linux: CI_DRM_5140 -> Patchwork_10827

  CI_DRM_5140: 68c169139ed5a6ab2aa72f84a0a7dcd0f1576717 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4714: cab148ca3ec904a94d0cd43476cf7e1f8663f906 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10827: f21a10597270010e0c529eb87d911d9b4a4ec1c1 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

f21a10597270 drm/i915: Pass the plane to icl_program_input_csc_coeff()
cb22c9ec683c drm/i915: Rename the confusing 'plane_id' to 'color_plane'
21fb8c0a9512 drm/i915: Commit skl+ planes in an order that avoids ddb overlaps
b340dfdc7c50 drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+
d52e2e45814c drm/i915: Don't pass dev_priv around so much
35935ddd1f7b drm/i915: Clean up skl+ vs. icl+ watermark computation
81ef2cb52f82 drm/i915: Pass the entire skl_plane_wm to skl_compute_transition_wm()
5217f4a8480a drm/i915: Remove some useless zeroing on skl+ wm calculations
b38354b977bd drm/i915: Fix latency==0 handling for level 0 watermark on skl+
eae12eaba5ea drm/i915: Pass the new crtc_state to ->disable_plane()
29f4a4966a76 drm/i915: Introduce crtc_state->update_planes bitmask
eb3c2f394649 drm/i915: Move single buffered plane register writes to the end
5a11dbcbd5cb drm/i915: Reorganize plane register writes to make them more atomic

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10827/issues.html
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✗ Fi.CI.IGT: failure for drm/i915: Program SKL+ watermarks/ddb more carefully (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev7)
URL   : https://patchwork.freedesktop.org/series/51878/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_5140_full -> Patchwork_10827_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10827_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10827_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10827_full:

  === IGT changes ===

    ==== Possible regressions ====

    igt@prime_vgem@basic-fence-flip:
      shard-apl:          PASS -> DMESG-WARN
      shard-kbl:          PASS -> DMESG-WARN

    
    ==== Warnings ====

    igt@pm_rc6_residency@rc6-accuracy:
      shard-snb:          SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Patchwork_10827_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_cpu_reloc@full:
      shard-skl:          NOTRUN -> INCOMPLETE (fdo#108073)

    igt@gem_ctx_isolation@vecs0-s3:
      shard-skl:          PASS -> INCOMPLETE (fdo#107773, fdo#104108)

    igt@kms_busy@extended-pageflip-hang-newfb-render-a:
      shard-apl:          PASS -> DMESG-WARN (fdo#107956)

    igt@kms_cursor_crc@cursor-256x256-suspend:
      shard-apl:          PASS -> FAIL (fdo#103232, fdo#103191)

    igt@kms_fbcon_fbt@psr-suspend:
      shard-skl:          NOTRUN -> FAIL (fdo#107882)

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
      shard-apl:          PASS -> FAIL (fdo#103167) +1

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
      shard-glk:          PASS -> FAIL (fdo#103167) +1

    igt@kms_frontbuffer_tracking@fbc-stridechange:
      shard-skl:          NOTRUN -> FAIL (fdo#105683)

    igt@kms_plane@pixel-format-pipe-c-planes:
      shard-glk:          PASS -> FAIL (fdo#103166)

    igt@kms_plane@plane-position-covered-pipe-b-planes:
      shard-apl:          PASS -> FAIL (fdo#103166)

    igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
      shard-skl:          NOTRUN -> FAIL (fdo#107815, fdo#108145)

    igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
      shard-apl:          NOTRUN -> FAIL (fdo#108145)

    igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
      shard-glk:          PASS -> FAIL (fdo#108145)

    igt@kms_setmode@basic:
      shard-apl:          PASS -> FAIL (fdo#99912)

    igt@pm_rpm@gem-execbuf:
      shard-skl:          PASS -> INCOMPLETE (fdo#107807, fdo#107803)

    igt@pm_rpm@pc8-residency:
      shard-skl:          SKIP -> INCOMPLETE (fdo#107807)

    
    ==== Possible fixes ====

    igt@drv_suspend@shrink:
      shard-apl:          INCOMPLETE (fdo#103927, fdo#106886) -> PASS

    igt@kms_cursor_crc@cursor-128x128-sliding:
      shard-apl:          FAIL (fdo#103232) -> PASS +1

    igt@kms_flip@flip-vs-expired-vblank-interruptible:
      shard-skl:          FAIL (fdo#105363) -> PASS

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt:
      shard-apl:          FAIL (fdo#103167) -> PASS +1

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
      shard-glk:          FAIL (fdo#103167) -> PASS +1

    igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
      shard-glk:          FAIL (fdo#103166) -> PASS

    igt@pm_rpm@dpms-non-lpsp:
      shard-skl:          INCOMPLETE (fdo#107807) -> SKIP

    igt@pm_rpm@gem-pread:
      shard-skl:          INCOMPLETE (fdo#107807) -> PASS

    
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105683 https://bugs.freedesktop.org/show_bug.cgi?id=105683
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
  fdo#107803 https://bugs.freedesktop.org/show_bug.cgi?id=107803
  fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
  fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815
  fdo#107882 https://bugs.freedesktop.org/show_bug.cgi?id=107882
  fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
  fdo#108073 https://bugs.freedesktop.org/show_bug.cgi?id=108073
  fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_5140 -> Patchwork_10827

  CI_DRM_5140: 68c169139ed5a6ab2aa72f84a0a7dcd0f1576717 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4714: cab148ca3ec904a94d0cd43476cf7e1f8663f906 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10827: f21a10597270010e0c529eb87d911d9b4a4ec1c1 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10827/shards.html
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Re: ✗ Fi.CI.IGT: failure for drm/i915: Program SKL+ watermarks/ddb more carefully (rev7)

[Ville Syrjälä]

On Thu, Nov 15, 2018 at 05:21:46AM -0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev7)
> URL   : https://patchwork.freedesktop.org/series/51878/
> State : failure
> 
> == Summary ==
> 
> = CI Bug Log - changes from CI_DRM_5140_full -> Patchwork_10827_full =
> 
> == Summary - FAILURE ==
> 
>   Serious unknown changes coming with Patchwork_10827_full absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_10827_full, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> == Possible new issues ==
> 
>   Here are the unknown changes that may have been introduced in Patchwork_10827_full:
> 
>   === IGT changes ===
> 
>     ==== Possible regressions ====
> 
>     igt@prime_vgem@basic-fence-flip:
>       shard-apl:          PASS -> DMESG-WARN
>       shard-kbl:          PASS -> DMESG-WARN


<3> [72.612353] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 0 (expected e=0 b=0 l=0, got e=1 b=3 l=1)
<3> [72.612661] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 1 (expected e=0 b=0 l=0, got e=1 b=4 l=1)
<3> [72.612784] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 2 (expected e=0 b=0 l=0, got e=1 b=4 l=1)
<3> [72.612905] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 3 (expected e=0 b=0 l=0, got e=1 b=6 l=2)
<3> [72.613026] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 4 (expected e=0 b=0 l=0, got e=1 b=6 l=2)
<3> [72.613147] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 5 (expected e=0 b=0 l=0, got e=1 b=6 l=2)
<3> [72.613267] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 6 (expected e=0 b=0 l=0, got e=1 b=6 l=2)
<3> [72.613388] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 7 (expected e=0 b=0 l=0, got e=1 b=6 l=2)

I suspect this would be caused by the cursor becoming fully clipped 
but still logically enabled (fb != NULL) during the  previous test
(kms_chv_cursor_fail). And then when it comes time to turn off the
pipe we won't reprogram the cursor because its visibility didn't
change and thus we won't clear its watermarks either. I think I'm
going to write a targeted test for that just to make sure my
analysis is correct.

-- 
Ville Syrjälä
Intel
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Re: ✗ Fi.CI.IGT: failure for drm/i915: Program SKL+ watermarks/ddb more carefully (rev7)

[Ville Syrjälä]

On Thu, Nov 15, 2018 at 04:23:46PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 15, 2018 at 05:21:46AM -0000, Patchwork wrote:
> > == Series Details ==
> > 
> > Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev7)
> > URL   : https://patchwork.freedesktop.org/series/51878/
> > State : failure
> > 
> > == Summary ==
> > 
> > = CI Bug Log - changes from CI_DRM_5140_full -> Patchwork_10827_full =
> > 
> > == Summary - FAILURE ==
> > 
> >   Serious unknown changes coming with Patchwork_10827_full absolutely need to be
> >   verified manually.
> >   
> >   If you think the reported changes have nothing to do with the changes
> >   introduced in Patchwork_10827_full, please notify your bug team to allow them
> >   to document this new failure mode, which will reduce false positives in CI.
> > 
> >   
> > 
> > == Possible new issues ==
> > 
> >   Here are the unknown changes that may have been introduced in Patchwork_10827_full:
> > 
> >   === IGT changes ===
> > 
> >     ==== Possible regressions ====
> > 
> >     igt@prime_vgem@basic-fence-flip:
> >       shard-apl:          PASS -> DMESG-WARN
> >       shard-kbl:          PASS -> DMESG-WARN
> 
> 
> <3> [72.612353] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 0 (expected e=0 b=0 l=0, got e=1 b=3 l=1)
> <3> [72.612661] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 1 (expected e=0 b=0 l=0, got e=1 b=4 l=1)
> <3> [72.612784] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 2 (expected e=0 b=0 l=0, got e=1 b=4 l=1)
> <3> [72.612905] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 3 (expected e=0 b=0 l=0, got e=1 b=6 l=2)
> <3> [72.613026] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 4 (expected e=0 b=0 l=0, got e=1 b=6 l=2)
> <3> [72.613147] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 5 (expected e=0 b=0 l=0, got e=1 b=6 l=2)
> <3> [72.613267] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 6 (expected e=0 b=0 l=0, got e=1 b=6 l=2)
> <3> [72.613388] [drm:verify_wm_state [i915]] *ERROR* mismatch in WM pipe A cursor level 7 (expected e=0 b=0 l=0, got e=1 b=6 l=2)
> 
> I suspect this would be caused by the cursor becoming fully clipped 
> but still logically enabled (fb != NULL) during the  previous test
> (kms_chv_cursor_fail). And then when it comes time to turn off the
> pipe we won't reprogram the cursor because its visibility didn't
> change and thus we won't clear its watermarks either. I think I'm
> going to write a targeted test for that just to make sure my
> analysis is correct.

Actually that can't be it I think. There was no complaint about a
non-zero DDB allocation left behind, so somehow we've got non-zero
watermarks with no DDB allocated. That doesn't quite make sense.

-- 
Ville Syrjälä
Intel
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✗ Fi.CI.CHECKPATCH: warning for drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)

[Patchwork]

== Series Details ==

Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)
URL   : https://patchwork.freedesktop.org/series/51878/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
8bd133c09121 drm/i915: Reorganize plane register writes to make them more atomic
aacf9460a2ab drm/i915: Move single buffered plane register writes to the end
76b702a28cf6 drm/i915: Introduce crtc_state->update_planes bitmask
a3f9718005f5 drm/i915: Pass the new crtc_state to ->disable_plane()
-:153: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#153: FILE: drivers/gpu/drm/i915/intel_display.h:385:
+#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
+		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
+		      (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
+	     (__i)++) \
+		for_each_if(plane)

-:153: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'plane' - possible side-effects?
#153: FILE: drivers/gpu/drm/i915/intel_display.h:385:
+#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
+		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
+		      (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
+	     (__i)++) \
+		for_each_if(plane)

-:153: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#153: FILE: drivers/gpu/drm/i915/intel_display.h:385:
+#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
+		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
+		      (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
+	     (__i)++) \
+		for_each_if(plane)

-:157: WARNING:LONG_LINE: line over 100 characters
#157: FILE: drivers/gpu/drm/i915/intel_display.h:389:
+		      (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \

total: 0 errors, 1 warnings, 3 checks, 159 lines checked
3fabcfdc4b40 drm/i915: Fix latency==0 handling for level 0 watermark on skl+
bd9a257fc86f drm/i915: Remove some useless zeroing on skl+ wm calculations
3ce3fec74105 drm/i915: Pass the entire skl_plane_wm to skl_compute_transition_wm()
b4194def78ee drm/i915: Clean up skl+ vs. icl+ watermark computation
1624810c3727 drm/i915: Don't pass dev_priv around so much
593ff87703a3 drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+
-:165: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#165: FILE: drivers/gpu/drm/i915/intel_display.h:418:
+#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.dev->mode_config.num_crtc && \
+		     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+		      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+		      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)++) \
+		for_each_if(crtc)

-:165: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'crtc' - possible side-effects?
#165: FILE: drivers/gpu/drm/i915/intel_display.h:418:
+#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.dev->mode_config.num_crtc && \
+		     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+		      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+		      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)++) \
+		for_each_if(crtc)

-:165: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#165: FILE: drivers/gpu/drm/i915/intel_display.h:418:
+#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.dev->mode_config.num_crtc && \
+		     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+		      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+		      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)++) \
+		for_each_if(crtc)

-:169: WARNING:LONG_LINE: line over 100 characters
#169: FILE: drivers/gpu/drm/i915/intel_display.h:422:
+		      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \

-:170: WARNING:LONG_LINE: line over 100 characters
#170: FILE: drivers/gpu/drm/i915/intel_display.h:423:
+		      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \

total: 0 errors, 2 warnings, 3 checks, 845 lines checked
d8ab70da1a46 drm/i915: Commit skl+ planes in an order that avoids ddb overlaps
063d7c684691 drm/i915: Rename the confusing 'plane_id' to 'color_plane'
1a9bea4b3b0e drm/i915: Pass the plane to icl_program_input_csc_coeff()

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✗ Fi.CI.SPARSE: warning for drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)

[Patchwork]

== Series Details ==

Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)
URL   : https://patchwork.freedesktop.org/series/51878/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Reorganize plane register writes to make them more atomic
Okay!

Commit: drm/i915: Move single buffered plane register writes to the end
Okay!

Commit: drm/i915: Introduce crtc_state->update_planes bitmask
Okay!

Commit: drm/i915: Pass the new crtc_state to ->disable_plane()
Okay!

Commit: drm/i915: Fix latency==0 handling for level 0 watermark on skl+
Okay!

Commit: drm/i915: Remove some useless zeroing on skl+ wm calculations
Okay!

Commit: drm/i915: Pass the entire skl_plane_wm to skl_compute_transition_wm()
Okay!

Commit: drm/i915: Clean up skl+ vs. icl+ watermark computation
Okay!

Commit: drm/i915: Don't pass dev_priv around so much
Okay!

Commit: drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3704:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3701:16: warning: expression using sizeof(void)

Commit: drm/i915: Commit skl+ planes in an order that avoids ddb overlaps
Okay!

Commit: drm/i915: Rename the confusing 'plane_id' to 'color_plane'
Okay!

Commit: drm/i915: Pass the plane to icl_program_input_csc_coeff()
Okay!

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✓ Fi.CI.BAT: success for drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)

[Patchwork]

== Series Details ==

Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)
URL   : https://patchwork.freedesktop.org/series/51878/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_5162 -> Patchwork_10852 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/51878/revisions/8/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10852 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@i915_selftest@live_contexts:
      fi-icl-u:           NOTRUN -> DMESG-FAIL (fdo#108569)

    igt@i915_selftest@live_hangcheck:
      fi-bwr-2160:        PASS -> DMESG-FAIL (fdo#108735)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-byt-clapper:     PASS -> FAIL (fdo#103191, fdo#107362)

    
    ==== Possible fixes ====

    igt@gem_ctx_create@basic-files:
      fi-icl-u2:          DMESG-WARN (fdo#107724) -> PASS

    igt@i915_selftest@live_coherency:
      fi-gdg-551:         DMESG-FAIL (fdo#107164) -> PASS

    igt@i915_selftest@live_contexts:
      fi-bsw-kefka:       DMESG-FAIL (fdo#108656) -> PASS

    igt@kms_flip@basic-flip-vs-modeset:
      fi-skl-6700hq:      DMESG-WARN (fdo#105998) -> PASS

    
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
  fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724
  fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569
  fdo#108656 https://bugs.freedesktop.org/show_bug.cgi?id=108656
  fdo#108735 https://bugs.freedesktop.org/show_bug.cgi?id=108735


== Participating hosts (53 -> 47) ==

  Additional (1): fi-icl-u 
  Missing    (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-u3 


== Build changes ==

    * Linux: CI_DRM_5162 -> Patchwork_10852

  CI_DRM_5162: 30290ec858904adcb173a94adad2bf2052f95f50 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4720: c27aaca295d3ca2a38521e571c012449371e4bb5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10852: 1a9bea4b3b0e3fc0b06fdb9c07787e3bc2e264b2 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

1a9bea4b3b0e drm/i915: Pass the plane to icl_program_input_csc_coeff()
063d7c684691 drm/i915: Rename the confusing 'plane_id' to 'color_plane'
d8ab70da1a46 drm/i915: Commit skl+ planes in an order that avoids ddb overlaps
593ff87703a3 drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+
1624810c3727 drm/i915: Don't pass dev_priv around so much
b4194def78ee drm/i915: Clean up skl+ vs. icl+ watermark computation
3ce3fec74105 drm/i915: Pass the entire skl_plane_wm to skl_compute_transition_wm()
bd9a257fc86f drm/i915: Remove some useless zeroing on skl+ wm calculations
3fabcfdc4b40 drm/i915: Fix latency==0 handling for level 0 watermark on skl+
a3f9718005f5 drm/i915: Pass the new crtc_state to ->disable_plane()
76b702a28cf6 drm/i915: Introduce crtc_state->update_planes bitmask
aacf9460a2ab drm/i915: Move single buffered plane register writes to the end
8bd133c09121 drm/i915: Reorganize plane register writes to make them more atomic

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10852/issues.html
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✗ Fi.CI.IGT: failure for drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)

[Patchwork]

== Series Details ==

Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)
URL   : https://patchwork.freedesktop.org/series/51878/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_5162_full -> Patchwork_10852_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10852_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10852_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10852_full:

  === IGT changes ===

    ==== Possible regressions ====

    igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic:
      shard-skl:          NOTRUN -> FAIL

    
    ==== Warnings ====

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite:
      shard-hsw:          PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_10852_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@debugfs_test@read_all_entries_display_off:
      shard-skl:          PASS -> INCOMPLETE (fdo#104108)

    igt@gem_ctx_exec@basic-invalid-context-bsd:
      shard-apl:          PASS -> INCOMPLETE (fdo#103927)

    igt@gem_exec_schedule@pi-ringfull-blt:
      {shard-iclb}:       NOTRUN -> FAIL (fdo#103158)

    igt@gem_ppgtt@blt-vs-render-ctxn:
      shard-skl:          NOTRUN -> TIMEOUT (fdo#108039)

    igt@i915_suspend@shrink:
      shard-snb:          NOTRUN -> DMESG-WARN (fdo#108784)
      {shard-iclb}:       NOTRUN -> DMESG-WARN (fdo#108784)

    igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
      {shard-iclb}:       NOTRUN -> DMESG-WARN (fdo#107956)

    igt@kms_ccs@pipe-a-crc-primary-rotation-180:
      {shard-iclb}:       NOTRUN -> FAIL (fdo#107725) +5

    igt@kms_chv_cursor_fail@pipe-c-128x128-bottom-edge:
      shard-skl:          NOTRUN -> FAIL (fdo#104671)

    igt@kms_color@pipe-a-ctm-max:
      shard-apl:          PASS -> FAIL (fdo#108147)

    igt@kms_color@pipe-c-legacy-gamma:
      shard-apl:          PASS -> FAIL (fdo#104782)

    igt@kms_cursor_crc@cursor-256x85-random:
      shard-apl:          PASS -> FAIL (fdo#103232)

    igt@kms_cursor_crc@cursor-256x85-sliding:
      {shard-iclb}:       NOTRUN -> FAIL (fdo#103232) +9

    igt@kms_fbcon_fbt@psr:
      {shard-iclb}:       NOTRUN -> FAIL (fdo#107882)

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
      shard-apl:          PASS -> FAIL (fdo#103167)

    igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render:
      {shard-iclb}:       NOTRUN -> FAIL (fdo#103167) +1

    igt@kms_hdmi_inject@inject-audio:
      {shard-iclb}:       NOTRUN -> FAIL (fdo#102370)

    igt@kms_panel_fitting@legacy:
      shard-skl:          NOTRUN -> FAIL (fdo#105456)

    igt@kms_plane@plane-position-covered-pipe-c-planes:
      shard-glk:          PASS -> FAIL (fdo#103166) +1

    igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
      shard-glk:          PASS -> FAIL (fdo#108145)

    igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
      shard-kbl:          NOTRUN -> FAIL (fdo#108145, fdo#108590)

    igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
      shard-skl:          NOTRUN -> FAIL (fdo#108145, fdo#107815)

    igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb:
      shard-kbl:          NOTRUN -> FAIL (fdo#108145)

    igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
      shard-skl:          NOTRUN -> FAIL (fdo#108145)

    igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
      shard-apl:          PASS -> FAIL (fdo#103166) +1

    igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
      {shard-iclb}:       NOTRUN -> FAIL (fdo#103166) +5

    igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format:
      {shard-iclb}:       NOTRUN -> DMESG-WARN (fdo#107724) +1

    igt@kms_rotation_crc@primary-rotation-180:
      shard-skl:          NOTRUN -> FAIL (fdo#103925, fdo#107815)

    igt@kms_sysfs_edid_timing:
      shard-kbl:          NOTRUN -> FAIL (fdo#100047)

    igt@pm_backlight@fade_with_suspend:
      shard-skl:          NOTRUN -> FAIL (fdo#107847)

    igt@pm_rpm@gem-execbuf-stress:
      shard-skl:          PASS -> INCOMPLETE (fdo#107803, fdo#107807)

    igt@pm_rpm@modeset-non-lpsp-stress-no-wait:
      shard-skl:          SKIP -> INCOMPLETE (fdo#107807)

    igt@pm_rpm@modeset-stress-extra-wait:
      shard-skl:          PASS -> INCOMPLETE (fdo#107807) +2

    
    ==== Possible fixes ====

    igt@gem_ctx_isolation@rcs0-s3:
      shard-kbl:          DMESG-WARN (fdo#108566) -> PASS

    igt@gem_ppgtt@blt-vs-render-ctx0:
      shard-kbl:          INCOMPLETE (fdo#103665, fdo#106887, fdo#106023) -> PASS

    igt@gem_workarounds@suspend-resume-fd:
      shard-skl:          INCOMPLETE (fdo#107773, fdo#104108) -> PASS

    igt@kms_available_modes_crc@available_mode_test_crc:
      shard-apl:          FAIL (fdo#106641) -> PASS

    igt@kms_busy@extended-modeset-hang-newfb-render-c:
      shard-skl:          DMESG-WARN (fdo#107956) -> PASS

    igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
      shard-glk:          DMESG-WARN (fdo#107956) -> PASS

    igt@kms_chv_cursor_fail@pipe-c-128x128-bottom-edge:
      shard-glk:          DMESG-WARN (fdo#106538, fdo#105763) -> PASS +3

    igt@kms_cursor_crc@cursor-64x21-random:
      shard-apl:          FAIL (fdo#103232) -> PASS

    igt@kms_cursor_crc@cursor-64x64-suspend:
      shard-skl:          INCOMPLETE (fdo#104108) -> PASS

    igt@kms_flip@flip-vs-absolute-wf_vblank:
      shard-apl:          DMESG-WARN (fdo#103558, fdo#105602) -> PASS +26

    igt@kms_flip@flip-vs-expired-vblank-interruptible:
      shard-glk:          FAIL (fdo#102887, fdo#105363) -> PASS

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt:
      shard-glk:          INCOMPLETE (k.org#198133, fdo#103359) -> PASS

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
      shard-apl:          FAIL (fdo#103167) -> PASS

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
      shard-glk:          FAIL (fdo#103167) -> PASS +1

    igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-move:
      shard-glk:          DMESG-FAIL (fdo#106538, fdo#103167, fdo#105763) -> PASS

    igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
      shard-glk:          FAIL (fdo#103166) -> PASS +2
      shard-apl:          FAIL (fdo#103166) -> PASS +1

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
  fdo#102370 https://bugs.freedesktop.org/show_bug.cgi?id=102370
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
  fdo#104671 https://bugs.freedesktop.org/show_bug.cgi?id=104671
  fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105456 https://bugs.freedesktop.org/show_bug.cgi?id=105456
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
  fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
  fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
  fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641
  fdo#106887 https://bugs.freedesktop.org/show_bug.cgi?id=106887
  fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724
  fdo#107725 https://bugs.freedesktop.org/show_bug.cgi?id=107725
  fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
  fdo#107803 https://bugs.freedesktop.org/show_bug.cgi?id=107803
  fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
  fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815
  fdo#107847 https://bugs.freedesktop.org/show_bug.cgi?id=107847
  fdo#107882 https://bugs.freedesktop.org/show_bug.cgi?id=107882
  fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
  fdo#108039 https://bugs.freedesktop.org/show_bug.cgi?id=108039
  fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
  fdo#108147 https://bugs.freedesktop.org/show_bug.cgi?id=108147
  fdo#108566 https://bugs.freedesktop.org/show_bug.cgi?id=108566
  fdo#108590 https://bugs.freedesktop.org/show_bug.cgi?id=108590
  fdo#108784 https://bugs.freedesktop.org/show_bug.cgi?id=108784
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (7 -> 7) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_5162 -> Patchwork_10852

  CI_DRM_5162: 30290ec858904adcb173a94adad2bf2052f95f50 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4720: c27aaca295d3ca2a38521e571c012449371e4bb5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10852: 1a9bea4b3b0e3fc0b06fdb9c07787e3bc2e264b2 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10852/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)

[Patchwork]

== Series Details ==

Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)
URL   : https://patchwork.freedesktop.org/series/51878/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_5174 -> Patchwork_10868 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/51878/revisions/8/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10868 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@i915_selftest@live_coherency:
      fi-gdg-551:         PASS -> DMESG-FAIL (fdo#107164)

    igt@kms_frontbuffer_tracking@basic:
      fi-byt-clapper:     PASS -> FAIL (fdo#103167)

    igt@kms_pipe_crc_basic@read-crc-pipe-a:
      fi-byt-clapper:     PASS -> FAIL (fdo#107362)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      fi-byt-clapper:     PASS -> FAIL (fdo#103191, fdo#107362) +2

    
    ==== Possible fixes ====

    igt@i915_selftest@live_execlists:
      fi-apl-guc:         DMESG-WARN (fdo#108622) -> PASS

    igt@kms_flip@basic-flip-vs-dpms:
      fi-skl-6700hq:      DMESG-WARN (fdo#105998) -> PASS

    
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
  fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#108622 https://bugs.freedesktop.org/show_bug.cgi?id=108622


== Participating hosts (52 -> 46) ==

  Missing    (6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-u3 


== Build changes ==

    * Linux: CI_DRM_5174 -> Patchwork_10868

  CI_DRM_5174: 0bfa7192170c039a271ebc27222b4b91516e73f6 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4722: fdcdfa1e220c5070072d5dac9523cd105e7406c2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10868: 145a11acda90d218c1127096da2f508cc178651f @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

145a11acda90 drm/i915: Pass the plane to icl_program_input_csc_coeff()
df683fdcc903 drm/i915: Rename the confusing 'plane_id' to 'color_plane'
5fba35efbdf4 drm/i915: Commit skl+ planes in an order that avoids ddb overlaps
3af1ac36dccf drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+
9c3dd2383e13 drm/i915: Don't pass dev_priv around so much
0abaf8ab6989 drm/i915: Clean up skl+ vs. icl+ watermark computation
2fbbf2ed154f drm/i915: Pass the entire skl_plane_wm to skl_compute_transition_wm()
c65dade8d072 drm/i915: Remove some useless zeroing on skl+ wm calculations
bc734f57b05a drm/i915: Fix latency==0 handling for level 0 watermark on skl+
2d80c5958d01 drm/i915: Pass the new crtc_state to ->disable_plane()
a89fe2cf093a drm/i915: Introduce crtc_state->update_planes bitmask
bd824902b5d5 drm/i915: Move single buffered plane register writes to the end
09c8e5196e04 drm/i915: Reorganize plane register writes to make them more atomic

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10868/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.IGT: failure for drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)

[Patchwork]

== Series Details ==

Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)
URL   : https://patchwork.freedesktop.org/series/51878/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_5174_full -> Patchwork_10868_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10868_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10868_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10868_full:

  === IGT changes ===

    ==== Possible regressions ====

    igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic:
      shard-skl:          PASS -> FAIL

    igt@kms_cursor_legacy@nonblocking-modeset-vs-cursor-atomic:
      shard-apl:          PASS -> FAIL

    
    ==== Warnings ====

    igt@pm_rc6_residency@rc6-accuracy:
      shard-snb:          SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Patchwork_10868_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_exec_schedule@preempt-hang-render:
      shard-apl:          PASS -> INCOMPLETE (fdo#103927)

    igt@gem_render_copy_redux@normal:
      shard-kbl:          PASS -> INCOMPLETE (fdo#103665, fdo#106650)

    igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
      shard-glk:          PASS -> FAIL (fdo#108145)

    igt@kms_chv_cursor_fail@pipe-a-128x128-top-edge:
      shard-skl:          NOTRUN -> FAIL (fdo#104671) +1

    igt@kms_cursor_crc@cursor-256x256-suspend:
      shard-skl:          PASS -> FAIL (fdo#103191, fdo#103232)

    igt@kms_cursor_crc@cursor-256x85-onscreen:
      shard-apl:          PASS -> FAIL (fdo#103232)

    igt@kms_flip@2x-flip-vs-expired-vblank:
      shard-glk:          PASS -> FAIL (fdo#105363)

    igt@kms_flip@flip-vs-expired-vblank-interruptible:
      shard-skl:          PASS -> FAIL (fdo#105363)

    igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc:
      shard-skl:          NOTRUN -> FAIL (fdo#105682)

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
      shard-skl:          NOTRUN -> FAIL (fdo#103167) +3

    igt@kms_frontbuffer_tracking@fbc-modesetfrombusy:
      shard-glk:          PASS -> FAIL (fdo#103167) +2

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      shard-skl:          PASS -> INCOMPLETE (fdo#107773, fdo#104108) +1

    igt@kms_plane@plane-position-covered-pipe-a-planes:
      shard-skl:          NOTRUN -> FAIL (fdo#103166)

    igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
      shard-skl:          NOTRUN -> FAIL (fdo#107815, fdo#108145)

    igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
      shard-skl:          PASS -> FAIL (fdo#107815)

    igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
      shard-apl:          PASS -> FAIL (fdo#103166)

    igt@kms_universal_plane@universal-plane-pipe-c-functional:
      shard-glk:          PASS -> FAIL (fdo#103166) +1

    igt@perf@oa-exponents:
      shard-glk:          PASS -> FAIL (fdo#105483)

    
    ==== Possible fixes ====

    igt@gem_ppgtt@blt-vs-render-ctxn:
      shard-skl:          TIMEOUT (fdo#108039) -> PASS

    igt@gem_pwrite@big-gtt-backwards:
      shard-apl:          INCOMPLETE (fdo#103927) -> PASS

    igt@kms_cursor_crc@cursor-256x85-sliding:
      shard-apl:          FAIL (fdo#103232) -> PASS

    igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
      shard-glk:          DMESG-WARN (fdo#106538, fdo#105763) -> PASS

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
      shard-apl:          FAIL (fdo#103167) -> PASS +2
      shard-glk:          FAIL (fdo#103167) -> PASS +1

    igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
      shard-skl:          FAIL (fdo#107815) -> PASS

    igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
      shard-glk:          FAIL (fdo#103166) -> PASS +2

    igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
      shard-apl:          FAIL (fdo#103166) -> PASS +1

    igt@kms_setmode@basic:
      shard-hsw:          FAIL (fdo#99912) -> PASS

    
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
  fdo#104671 https://bugs.freedesktop.org/show_bug.cgi?id=104671
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105483 https://bugs.freedesktop.org/show_bug.cgi?id=105483
  fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682
  fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
  fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
  fdo#106650 https://bugs.freedesktop.org/show_bug.cgi?id=106650
  fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
  fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815
  fdo#108039 https://bugs.freedesktop.org/show_bug.cgi?id=108039
  fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (7 -> 6) ==

  Missing    (1): shard-iclb 


== Build changes ==

    * Linux: CI_DRM_5174 -> Patchwork_10868

  CI_DRM_5174: 0bfa7192170c039a271ebc27222b4b91516e73f6 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4722: fdcdfa1e220c5070072d5dac9523cd105e7406c2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10868: 145a11acda90d218c1127096da2f508cc178651f @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10868/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: ✗ Fi.CI.IGT: failure for drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)

[Ville Syrjälä]

On Wed, Nov 21, 2018 at 06:05:21AM -0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)
> URL   : https://patchwork.freedesktop.org/series/51878/
> State : failure
> 
> == Summary ==
> 
> = CI Bug Log - changes from CI_DRM_5174_full -> Patchwork_10868_full =
> 
> == Summary - FAILURE ==
> 
>   Serious unknown changes coming with Patchwork_10868_full absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_10868_full, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> == Possible new issues ==
> 
>   Here are the unknown changes that may have been introduced in Patchwork_10868_full:
> 
>   === IGT changes ===
> 
>     ==== Possible regressions ====
> 
>     igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic:
>       shard-skl:          PASS -> FAIL
> 
>     igt@kms_cursor_legacy@nonblocking-modeset-vs-cursor-atomic:
>       shard-apl:          PASS -> FAIL

Mysterious and mysteriouser.

The test does this:
1. enable_crtc
2. setcursor
3. wait_for_event
4. disable_crtc

Apparently we're not getting -EBUSY from step 4. Which would imply
that we still have an unifinished commit in the queue. The cursor ioctl
should block until everything is done, so I can't see how that is
possible. And so far I'm unable to reproduce this locally.

> 
>     
>     ==== Warnings ====
> 
>     igt@pm_rc6_residency@rc6-accuracy:
>       shard-snb:          SKIP -> PASS
> 
>     
> == Known issues ==
> 
>   Here are the changes found in Patchwork_10868_full that come from known issues:
> 
>   === IGT changes ===
> 
>     ==== Issues hit ====
> 
>     igt@gem_exec_schedule@preempt-hang-render:
>       shard-apl:          PASS -> INCOMPLETE (fdo#103927)
> 
>     igt@gem_render_copy_redux@normal:
>       shard-kbl:          PASS -> INCOMPLETE (fdo#103665, fdo#106650)
> 
>     igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
>       shard-glk:          PASS -> FAIL (fdo#108145)
> 
>     igt@kms_chv_cursor_fail@pipe-a-128x128-top-edge:
>       shard-skl:          NOTRUN -> FAIL (fdo#104671) +1
> 
>     igt@kms_cursor_crc@cursor-256x256-suspend:
>       shard-skl:          PASS -> FAIL (fdo#103191, fdo#103232)
> 
>     igt@kms_cursor_crc@cursor-256x85-onscreen:
>       shard-apl:          PASS -> FAIL (fdo#103232)
> 
>     igt@kms_flip@2x-flip-vs-expired-vblank:
>       shard-glk:          PASS -> FAIL (fdo#105363)
> 
>     igt@kms_flip@flip-vs-expired-vblank-interruptible:
>       shard-skl:          PASS -> FAIL (fdo#105363)
> 
>     igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc:
>       shard-skl:          NOTRUN -> FAIL (fdo#105682)
> 
>     igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
>       shard-skl:          NOTRUN -> FAIL (fdo#103167) +3
> 
>     igt@kms_frontbuffer_tracking@fbc-modesetfrombusy:
>       shard-glk:          PASS -> FAIL (fdo#103167) +2
> 
>     igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
>       shard-skl:          PASS -> INCOMPLETE (fdo#107773, fdo#104108) +1
> 
>     igt@kms_plane@plane-position-covered-pipe-a-planes:
>       shard-skl:          NOTRUN -> FAIL (fdo#103166)
> 
>     igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
>       shard-skl:          NOTRUN -> FAIL (fdo#107815, fdo#108145)
> 
>     igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
>       shard-skl:          PASS -> FAIL (fdo#107815)
> 
>     igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
>       shard-apl:          PASS -> FAIL (fdo#103166)
> 
>     igt@kms_universal_plane@universal-plane-pipe-c-functional:
>       shard-glk:          PASS -> FAIL (fdo#103166) +1
> 
>     igt@perf@oa-exponents:
>       shard-glk:          PASS -> FAIL (fdo#105483)
> 
>     
>     ==== Possible fixes ====
> 
>     igt@gem_ppgtt@blt-vs-render-ctxn:
>       shard-skl:          TIMEOUT (fdo#108039) -> PASS
> 
>     igt@gem_pwrite@big-gtt-backwards:
>       shard-apl:          INCOMPLETE (fdo#103927) -> PASS
> 
>     igt@kms_cursor_crc@cursor-256x85-sliding:
>       shard-apl:          FAIL (fdo#103232) -> PASS
> 
>     igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
>       shard-glk:          DMESG-WARN (fdo#106538, fdo#105763) -> PASS
> 
>     igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
>       shard-apl:          FAIL (fdo#103167) -> PASS +2
>       shard-glk:          FAIL (fdo#103167) -> PASS +1
> 
>     igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
>       shard-skl:          FAIL (fdo#107815) -> PASS
> 
>     igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
>       shard-glk:          FAIL (fdo#103166) -> PASS +2
> 
>     igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
>       shard-apl:          FAIL (fdo#103166) -> PASS +1
> 
>     igt@kms_setmode@basic:
>       shard-hsw:          FAIL (fdo#99912) -> PASS
> 
>     
>   fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
>   fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
>   fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
>   fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
>   fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
>   fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
>   fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
>   fdo#104671 https://bugs.freedesktop.org/show_bug.cgi?id=104671
>   fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
>   fdo#105483 https://bugs.freedesktop.org/show_bug.cgi?id=105483
>   fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682
>   fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
>   fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
>   fdo#106650 https://bugs.freedesktop.org/show_bug.cgi?id=106650
>   fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
>   fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815
>   fdo#108039 https://bugs.freedesktop.org/show_bug.cgi?id=108039
>   fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
>   fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
> 
> 
> == Participating hosts (7 -> 6) ==
> 
>   Missing    (1): shard-iclb 
> 
> 
> == Build changes ==
> 
>     * Linux: CI_DRM_5174 -> Patchwork_10868
> 
>   CI_DRM_5174: 0bfa7192170c039a271ebc27222b4b91516e73f6 @ git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_4722: fdcdfa1e220c5070072d5dac9523cd105e7406c2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>   Patchwork_10868: 145a11acda90d218c1127096da2f508cc178651f @ git://anongit.freedesktop.org/gfx-ci/linux
>   piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10868/shards.html

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)

[Patchwork]

== Series Details ==

Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)
URL   : https://patchwork.freedesktop.org/series/51878/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_5195 -> Patchwork_10898 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/51878/revisions/8/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10898:

  === IGT changes ===

    ==== Possible regressions ====

    {igt@runner@aborted}:
      {fi-icl-u3}:        NOTRUN -> FAIL

    
== Known issues ==

  Here are the changes found in Patchwork_10898 that come from known issues:

  === IGT changes ===

    ==== Possible fixes ====

    igt@i915_selftest@live_coherency:
      fi-gdg-551:         DMESG-FAIL (fdo#107164) -> PASS

    igt@kms_frontbuffer_tracking@basic:
      fi-byt-clapper:     FAIL (fdo#103167) -> PASS

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
      fi-byt-clapper:     FAIL (fdo#107362, fdo#103191) -> PASS

    
    ==== Warnings ====

    igt@i915_selftest@live_contexts:
      {fi-icl-u3}:        DMESG-FAIL (fdo#108569) -> INCOMPLETE (fdo#108315)

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#108315 https://bugs.freedesktop.org/show_bug.cgi?id=108315
  fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569


== Participating hosts (46 -> 42) ==

  Additional (1): fi-skl-6700hq 
  Missing    (5): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan 


== Build changes ==

    * Linux: CI_DRM_5195 -> Patchwork_10898

  CI_DRM_5195: b6df470d38bf4580c00e3f5008d795ec2a901066 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4725: 9dc7c41d1c600133d6e3e63f1941c2e75d23bd3b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10898: a696e613103193b509eca4fcb748c40e89c032d1 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

a696e6131031 drm/i915: Pass the plane to icl_program_input_csc_coeff()
513bda7ee3ea drm/i915: Rename the confusing 'plane_id' to 'color_plane'
13bfa6780458 drm/i915: Commit skl+ planes in an order that avoids ddb overlaps
83063579f5dc drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+
a637c754836e drm/i915: Don't pass dev_priv around so much
4af4b817ac1c drm/i915: Clean up skl+ vs. icl+ watermark computation
e7dff32c2760 drm/i915: Pass the entire skl_plane_wm to skl_compute_transition_wm()
ea6fe2c5a44e drm/i915: Remove some useless zeroing on skl+ wm calculations
51cc3ac84834 drm/i915: Fix latency==0 handling for level 0 watermark on skl+
4ac4a3bcb3b9 drm/i915: Pass the new crtc_state to ->disable_plane()
1fd9e5140be1 drm/i915: Introduce crtc_state->update_planes bitmask
bb160a418227 drm/i915: Move single buffered plane register writes to the end
27eecacadbab drm/i915: Reorganize plane register writes to make them more atomic

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10898/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)

[Patchwork]

== Series Details ==

Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)
URL   : https://patchwork.freedesktop.org/series/51878/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_5195_full -> Patchwork_10898_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10898_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10898_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10898_full:

  === IGT changes ===

    ==== Warnings ====

    igt@kms_cursor_legacy@short-flip-before-cursor-atomic-transitions-varying-size:
      shard-snb:          SKIP -> PASS

    igt@perf_pmu@rc6:
      shard-kbl:          SKIP -> PASS

    igt@pm_rc6_residency@rc6-accuracy:
      shard-snb:          PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_10898_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_ctx_isolation@bcs0-s3:
      shard-skl:          PASS -> INCOMPLETE (fdo#107773, fdo#104108) +1

    igt@gem_eio@suspend:
      shard-glk:          PASS -> INCOMPLETE (fdo#103359, k.org#198133)

    igt@kms_atomic_interruptible@universal-setplane-primary:
      shard-kbl:          PASS -> DMESG-WARN (fdo#103558, fdo#105602) +27

    igt@kms_available_modes_crc@available_mode_test_crc:
      shard-apl:          PASS -> FAIL (fdo#106641)

    igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
      {shard-iclb}:       PASS -> DMESG-WARN (fdo#107956) +1

    igt@kms_color@pipe-a-ctm-blue-to-red:
      shard-kbl:          PASS -> DMESG-WARN (fdo#103313, fdo#103558, fdo#105602) +3

    igt@kms_cursor_crc@cursor-64x21-random:
      shard-apl:          PASS -> FAIL (fdo#103232) +5

    igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
      shard-hsw:          PASS -> FAIL (fdo#105767)

    igt@kms_fbcon_fbt@psr-suspend:
      shard-skl:          NOTRUN -> FAIL (fdo#107882)

    igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu:
      shard-skl:          PASS -> FAIL (fdo#103167)

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
      {shard-iclb}:       PASS -> FAIL (fdo#103167) +4

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
      shard-apl:          PASS -> FAIL (fdo#103167) +1

    igt@kms_frontbuffer_tracking@fbc-1p-rte:
      shard-kbl:          PASS -> DMESG-WARN (fdo#103313, fdo#103558)

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt:
      shard-glk:          PASS -> FAIL (fdo#103167) +3

    igt@kms_plane@pixel-format-pipe-b-planes:
      shard-skl:          NOTRUN -> DMESG-WARN (fdo#106885)

    igt@kms_plane@pixel-format-pipe-c-planes:
      shard-apl:          PASS -> FAIL (fdo#103166) +1

    igt@kms_plane@plane-position-covered-pipe-b-planes:
      {shard-iclb}:       PASS -> FAIL (fdo#103166)

    igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
      shard-skl:          PASS -> FAIL (fdo#107815, fdo#108145)

    igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
      shard-skl:          NOTRUN -> FAIL (fdo#107815, fdo#108145)

    igt@kms_plane_scaling@pipe-b-plane-scaling:
      shard-apl:          PASS -> DMESG-WARN (fdo#103558, fdo#105602) +2

    igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format:
      {shard-iclb}:       NOTRUN -> DMESG-WARN (fdo#107724)

    igt@kms_setmode@basic:
      shard-apl:          PASS -> FAIL (fdo#99912)

    igt@pm_rpm@basic-pci-d3-state:
      shard-skl:          PASS -> INCOMPLETE (fdo#107807) +1

    igt@pm_rpm@gem-execbuf-stress-pc8:
      {shard-iclb}:       SKIP -> INCOMPLETE (fdo#107713)

    
    ==== Possible fixes ====

    igt@drm_import_export@import-close-race-flink:
      shard-skl:          TIMEOUT (fdo#108667) -> PASS

    igt@gem_userptr_blits@readonly-unsync:
      shard-skl:          INCOMPLETE (fdo#108074) -> PASS

    igt@kms_busy@extended-modeset-hang-newfb-render-a:
      shard-skl:          DMESG-WARN (fdo#107956) -> PASS

    igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
      shard-snb:          INCOMPLETE (fdo#105411) -> SKIP

    igt@kms_cursor_crc@cursor-128x128-suspend:
      shard-apl:          FAIL (fdo#103232, fdo#103191) -> PASS

    igt@kms_cursor_crc@cursor-256x256-random:
      shard-glk:          FAIL (fdo#103232) -> PASS +1

    igt@kms_cursor_crc@cursor-256x85-onscreen:
      shard-apl:          FAIL (fdo#103232) -> PASS +2

    igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-xtiled:
      shard-skl:          FAIL (fdo#107791) -> PASS

    igt@kms_flip@flip-vs-absolute-wf_vblank:
      shard-apl:          DMESG-WARN (fdo#103558, fdo#105602) -> PASS +17

    igt@kms_flip@flip-vs-expired-vblank:
      shard-skl:          FAIL (fdo#105363) -> PASS

    igt@kms_flip@flip-vs-expired-vblank-interruptible:
      shard-kbl:          FAIL (fdo#102887, fdo#105363) -> PASS

    igt@kms_flip@flip-vs-wf_vblank-interruptible:
      shard-skl:          FAIL (fdo#100368) -> PASS +1

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu:
      shard-apl:          FAIL (fdo#103167) -> PASS

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
      shard-glk:          FAIL (fdo#103167) -> PASS

    igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render:
      {shard-iclb}:       FAIL (fdo#103167) -> PASS +2

    igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
      shard-apl:          FAIL (fdo#103166) -> PASS +1

    igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
      shard-glk:          FAIL (fdo#103166) -> PASS
      {shard-iclb}:       FAIL (fdo#103166) -> PASS

    igt@pm_rpm@modeset-pc8-residency-stress:
      shard-skl:          INCOMPLETE (fdo#107807) -> SKIP

    
    ==== Warnings ====

    igt@i915_suspend@shrink:
      shard-snb:          DMESG-WARN (fdo#108784) -> INCOMPLETE (fdo#106886, fdo#105411)

    igt@kms_cursor_crc@cursor-128x128-random:
      shard-apl:          DMESG-FAIL (fdo#103232, fdo#103558, fdo#105602) -> FAIL (fdo#103232) +1
      shard-kbl:          FAIL (fdo#103232) -> DMESG-FAIL (fdo#103232, fdo#103558, fdo#105602)

    igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
      shard-apl:          DMESG-FAIL (fdo#108145, fdo#103558, fdo#105602) -> FAIL (fdo#108145)
      shard-kbl:          FAIL (fdo#108145, fdo#108590) -> DMESG-FAIL (fdo#108145, fdo#103558, fdo#105602)

    igt@pm_backlight@fade_with_suspend:
      {shard-iclb}:       DMESG-FAIL (fdo#107724) -> FAIL (fdo#107847)

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767
  fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641
  fdo#106885 https://bugs.freedesktop.org/show_bug.cgi?id=106885
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713
  fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724
  fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
  fdo#107791 https://bugs.freedesktop.org/show_bug.cgi?id=107791
  fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
  fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815
  fdo#107847 https://bugs.freedesktop.org/show_bug.cgi?id=107847
  fdo#107882 https://bugs.freedesktop.org/show_bug.cgi?id=107882
  fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
  fdo#108074 https://bugs.freedesktop.org/show_bug.cgi?id=108074
  fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
  fdo#108590 https://bugs.freedesktop.org/show_bug.cgi?id=108590
  fdo#108667 https://bugs.freedesktop.org/show_bug.cgi?id=108667
  fdo#108784 https://bugs.freedesktop.org/show_bug.cgi?id=108784
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (7 -> 7) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_5195 -> Patchwork_10898

  CI_DRM_5195: b6df470d38bf4580c00e3f5008d795ec2a901066 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4725: 9dc7c41d1c600133d6e3e63f1941c2e75d23bd3b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10898: a696e613103193b509eca4fcb748c40e89c032d1 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10898/shards.html
_______________________________________________
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✗ Fi.CI.CHECKPATCH: warning for drm/i915: Program SKL+ watermarks/ddb more carefully (rev11)

[Patchwork]

== Series Details ==

Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev11)
URL   : https://patchwork.freedesktop.org/series/51878/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
094cd6f80a68 drm/i915: Reorganize plane register writes to make them more atomic
ef3ad7085ebf drm/i915: Move single buffered plane register writes to the end
0384431cd12f drm/i915: Introduce crtc_state->update_planes bitmask
7107a3d9c003 drm/i915: Pass the new crtc_state to ->disable_plane()
-:154: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#154: FILE: drivers/gpu/drm/i915/intel_display.h:401:
+#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
+		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
+		      (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
+	     (__i)++) \
+		for_each_if(plane)

-:154: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'plane' - possible side-effects?
#154: FILE: drivers/gpu/drm/i915/intel_display.h:401:
+#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
+		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
+		      (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
+	     (__i)++) \
+		for_each_if(plane)

-:154: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#154: FILE: drivers/gpu/drm/i915/intel_display.h:401:
+#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
+		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
+		      (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
+	     (__i)++) \
+		for_each_if(plane)

-:158: WARNING:LONG_LINE: line over 100 characters
#158: FILE: drivers/gpu/drm/i915/intel_display.h:405:
+		      (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \

total: 0 errors, 1 warnings, 3 checks, 159 lines checked
edbc517f0a76 drm/i915: Fix latency==0 handling for level 0 watermark on skl+
ef730820a9b9 drm/i915: Remove some useless zeroing on skl+ wm calculations
c59c49fe42d5 drm/i915: Pass the entire skl_plane_wm to skl_compute_transition_wm()
900570f29731 drm/i915: Clean up skl+ vs. icl+ watermark computation
4611696fec9f drm/i915: Don't pass dev_priv around so much
378d0718daa0 drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+
-:158: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#158: FILE: drivers/gpu/drm/i915/intel_display.h:434:
+#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.dev->mode_config.num_crtc && \
+		     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+		      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+		      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)++) \
+		for_each_if(crtc)

-:158: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'crtc' - possible side-effects?
#158: FILE: drivers/gpu/drm/i915/intel_display.h:434:
+#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.dev->mode_config.num_crtc && \
+		     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+		      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+		      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)++) \
+		for_each_if(crtc)

-:158: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#158: FILE: drivers/gpu/drm/i915/intel_display.h:434:
+#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.dev->mode_config.num_crtc && \
+		     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+		      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+		      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)++) \
+		for_each_if(crtc)

-:162: WARNING:LONG_LINE: line over 100 characters
#162: FILE: drivers/gpu/drm/i915/intel_display.h:438:
+		      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \

-:163: WARNING:LONG_LINE: line over 100 characters
#163: FILE: drivers/gpu/drm/i915/intel_display.h:439:
+		      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \

total: 0 errors, 2 warnings, 3 checks, 836 lines checked
6581d1c88787 drm/i915: Commit skl+ planes in an order that avoids ddb overlaps
972e01e50301 drm/i915: Rename the confusing 'plane_id' to 'color_plane'
f626b07e7e19 drm/i915: Pass the plane to icl_program_input_csc_coeff()

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✗ Fi.CI.SPARSE: warning for drm/i915: Program SKL+ watermarks/ddb more carefully (rev11)

[Patchwork]

== Series Details ==

Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev11)
URL   : https://patchwork.freedesktop.org/series/51878/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Reorganize plane register writes to make them more atomic
Okay!

Commit: drm/i915: Move single buffered plane register writes to the end
Okay!

Commit: drm/i915: Introduce crtc_state->update_planes bitmask
Okay!

Commit: drm/i915: Pass the new crtc_state to ->disable_plane()
Okay!

Commit: drm/i915: Fix latency==0 handling for level 0 watermark on skl+
Okay!

Commit: drm/i915: Remove some useless zeroing on skl+ wm calculations
Okay!

Commit: drm/i915: Pass the entire skl_plane_wm to skl_compute_transition_wm()
Okay!

Commit: drm/i915: Clean up skl+ vs. icl+ watermark computation
Okay!

Commit: drm/i915: Don't pass dev_priv around so much
Okay!

Commit: drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3569:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3566:16: warning: expression using sizeof(void)

Commit: drm/i915: Commit skl+ planes in an order that avoids ddb overlaps
Okay!

Commit: drm/i915: Rename the confusing 'plane_id' to 'color_plane'
Okay!

Commit: drm/i915: Pass the plane to icl_program_input_csc_coeff()
Okay!

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✓ Fi.CI.BAT: success for drm/i915: Program SKL+ watermarks/ddb more carefully (rev11)

[Patchwork]

== Series Details ==

Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev11)
URL   : https://patchwork.freedesktop.org/series/51878/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_5211 -> Patchwork_10915 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/51878/revisions/11/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10915 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_ctx_create@basic-files:
      fi-bsw-n3050:       PASS -> FAIL ([fdo#108656])
      fi-bsw-kefka:       PASS -> DMESG-FAIL ([fdo#108656])

    {igt@runner@aborted}:
      {fi-icl-u3}:        NOTRUN -> FAIL ([fdo#108866 ])
      fi-bsw-kefka:       NOTRUN -> FAIL ([fdo#108656])

    
    ==== Possible fixes ====

    igt@i915_module_load@reload:
      fi-blb-e6850:       INCOMPLETE ([fdo#107718]) -> PASS

    igt@i915_selftest@live_hangcheck:
      fi-cfl-8109u:       INCOMPLETE ([fdo#106070]) -> PASS

    igt@kms_chamelium@hdmi-hpd-fast:
      {fi-kbl-7500u}:     FAIL -> PASS

    igt@kms_pipe_crc_basic@read-crc-pipe-a:
      fi-byt-clapper:     FAIL ([fdo#107362]) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      fi-byt-clapper:     FAIL ([fdo#103191], [fdo#107362]) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-cfl-8109u:       DMESG-WARN ([fdo#106107]) -> PASS

    
    ==== Warnings ====

    igt@i915_selftest@live_contexts:
      {fi-icl-u3}:        DMESG-FAIL ([fdo#108569]) -> INCOMPLETE ([fdo#108315])

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#106070 https://bugs.freedesktop.org/show_bug.cgi?id=106070
  fdo#106107 https://bugs.freedesktop.org/show_bug.cgi?id=106107
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
  fdo#108315 https://bugs.freedesktop.org/show_bug.cgi?id=108315
  fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569
  fdo#108656 https://bugs.freedesktop.org/show_bug.cgi?id=108656
  fdo#108866  https://bugs.freedesktop.org/show_bug.cgi?id=108866 


== Participating hosts (51 -> 46) ==

  Missing    (5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 


== Build changes ==

    * Linux: CI_DRM_5211 -> Patchwork_10915

  CI_DRM_5211: b6ba4ad91b7c6c4341c40a05b0326470e0c293cb @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4732: eae5c3587e56abc581af9b59060cd316df2caa08 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10915: f626b07e7e192b298698c64e5fda851e03e79495 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

f626b07e7e19 drm/i915: Pass the plane to icl_program_input_csc_coeff()
972e01e50301 drm/i915: Rename the confusing 'plane_id' to 'color_plane'
6581d1c88787 drm/i915: Commit skl+ planes in an order that avoids ddb overlaps
378d0718daa0 drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+
4611696fec9f drm/i915: Don't pass dev_priv around so much
900570f29731 drm/i915: Clean up skl+ vs. icl+ watermark computation
c59c49fe42d5 drm/i915: Pass the entire skl_plane_wm to skl_compute_transition_wm()
ef730820a9b9 drm/i915: Remove some useless zeroing on skl+ wm calculations
edbc517f0a76 drm/i915: Fix latency==0 handling for level 0 watermark on skl+
7107a3d9c003 drm/i915: Pass the new crtc_state to ->disable_plane()
0384431cd12f drm/i915: Introduce crtc_state->update_planes bitmask
ef3ad7085ebf drm/i915: Move single buffered plane register writes to the end
094cd6f80a68 drm/i915: Reorganize plane register writes to make them more atomic

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10915/
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✓ Fi.CI.IGT: success for drm/i915: Program SKL+ watermarks/ddb more carefully (rev11)

[Patchwork]

== Series Details ==

Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev11)
URL   : https://patchwork.freedesktop.org/series/51878/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_5211_full -> Patchwork_10915_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10915_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10915_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10915_full:

  === IGT changes ===

    ==== Warnings ====

    igt@kms_chv_cursor_fail@pipe-b-64x64-top-edge:
      shard-snb:          SKIP -> PASS

    igt@pm_rc6_residency@rc6-accuracy:
      shard-kbl:          SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Patchwork_10915_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@debugfs_test@read_all_entries_display_off:
      shard-skl:          PASS -> INCOMPLETE ([fdo#104108])

    igt@gem_exec_suspend@basic-s3:
      shard-kbl:          PASS -> INCOMPLETE ([fdo#103665])

    igt@gem_softpin@noreloc-s3:
      shard-skl:          PASS -> INCOMPLETE ([fdo#104108], [fdo#107773])

    igt@i915_suspend@shrink:
      shard-skl:          NOTRUN -> INCOMPLETE ([fdo#106886])

    igt@kms_chv_cursor_fail@pipe-c-128x128-right-edge:
      shard-skl:          NOTRUN -> FAIL ([fdo#104671])

    igt@kms_color@pipe-a-ctm-0-25:
      shard-skl:          PASS -> FAIL ([fdo#108682])

    igt@kms_color@pipe-a-ctm-max:
      shard-apl:          PASS -> FAIL ([fdo#108147])

    igt@kms_cursor_crc@cursor-128x128-random:
      shard-apl:          PASS -> FAIL ([fdo#103232]) +3

    igt@kms_cursor_crc@cursor-64x21-onscreen:
      shard-glk:          PASS -> FAIL ([fdo#103232]) +2

    igt@kms_cursor_crc@cursor-64x64-suspend:
      shard-apl:          PASS -> FAIL ([fdo#103191], [fdo#103232])

    igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled:
      shard-skl:          PASS -> FAIL ([fdo#103184], [fdo#103232])

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
      shard-apl:          PASS -> FAIL ([fdo#103167]) +2

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt:
      shard-glk:          PASS -> FAIL ([fdo#103167]) +6

    igt@kms_frontbuffer_tracking@fbc-suspend:
      shard-skl:          PASS -> INCOMPLETE ([fdo#104108], [fdo#105959])

    igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render:
      shard-skl:          NOTRUN -> FAIL ([fdo#103167]) +1

    igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt:
      {shard-iclb}:       PASS -> FAIL ([fdo#103167]) +3

    igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb:
      shard-skl:          NOTRUN -> FAIL ([fdo#108145]) +1

    igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
      shard-skl:          NOTRUN -> FAIL ([fdo#107815])

    igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
      {shard-iclb}:       PASS -> FAIL ([fdo#103166])

    igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
      shard-glk:          PASS -> FAIL ([fdo#103166])
      shard-apl:          PASS -> FAIL ([fdo#103166]) +1

    igt@kms_psr@no_drrs:
      {shard-iclb}:       PASS -> FAIL ([fdo#108341])

    igt@pm_rpm@sysfs-read:
      {shard-iclb}:       PASS -> INCOMPLETE ([fdo#107713], [fdo#108840])

    
    ==== Possible fixes ====

    igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
      {shard-iclb}:       DMESG-WARN ([fdo#107956]) -> PASS

    igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
      shard-apl:          DMESG-WARN ([fdo#107956]) -> PASS

    igt@kms_color@pipe-a-legacy-gamma:
      shard-skl:          FAIL ([fdo#104782], [fdo#108145]) -> PASS

    igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
      shard-glk:          DMESG-WARN ([fdo#105763], [fdo#106538]) -> PASS

    igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled:
      shard-glk:          FAIL ([fdo#103184]) -> PASS

    igt@kms_flip@flip-vs-expired-vblank-interruptible:
      shard-apl:          FAIL ([fdo#102887], [fdo#105363]) -> PASS

    igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
      {shard-iclb}:       FAIL ([fdo#103167]) -> PASS +3

    igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
      {shard-iclb}:       FAIL ([fdo#103166]) -> PASS +1

    igt@pm_rpm@pm-caching:
      shard-skl:          INCOMPLETE ([fdo#107807]) -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
  fdo#104671 https://bugs.freedesktop.org/show_bug.cgi?id=104671
  fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
  fdo#105959 https://bugs.freedesktop.org/show_bug.cgi?id=105959
  fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713
  fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
  fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
  fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815
  fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
  fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
  fdo#108147 https://bugs.freedesktop.org/show_bug.cgi?id=108147
  fdo#108341 https://bugs.freedesktop.org/show_bug.cgi?id=108341
  fdo#108682 https://bugs.freedesktop.org/show_bug.cgi?id=108682
  fdo#108840 https://bugs.freedesktop.org/show_bug.cgi?id=108840


== Participating hosts (7 -> 7) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_5211 -> Patchwork_10915

  CI_DRM_5211: b6ba4ad91b7c6c4341c40a05b0326470e0c293cb @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4732: eae5c3587e56abc581af9b59060cd316df2caa08 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10915: f626b07e7e192b298698c64e5fda851e03e79495 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10915/shards.html
_______________________________________________
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Re: [PATCH v2 00/13] drm/i915: Program SKL+ watermarks/ddb more carefully

[Ville Syrjälä]

On Wed, Nov 14, 2018 at 11:07:16PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Here's the remainder of the skl+ ddb/wm programming series. I tried to
> split up the ugly monster patch into a few chunks, and I tossed in
> a few extra nuggets on top. I also tried to improve the commit
> messages a bit based on the previous review feedback.
> 
> Entire series available here:
> git://github.com/vsyrjala/linux.git skl_plane_ddb_wm_update_3
> 
> Ville Syrjälä (13):
>   drm/i915: Reorganize plane register writes to make them more atomic
>   drm/i915: Move single buffered plane register writes to the end
>   drm/i915: Introduce crtc_state->update_planes bitmask
>   drm/i915: Pass the new crtc_state to ->disable_plane()
>   drm/i915: Fix latency==0 handling for level 0 watermark on skl+
>   drm/i915: Remove some useless zeroing on skl+ wm calculations
>   drm/i915: Pass the entire skl_plane_wm to skl_compute_transition_wm()
>   drm/i915: Clean up skl+ vs. icl+ watermark computation
>   drm/i915: Don't pass dev_priv around so much
>   drm/i915: Move ddb/wm programming into plane update/disable hooks on
>     skl+
>   drm/i915: Commit skl+ planes in an order that avoids ddb overlaps
>   drm/i915: Rename the confusing 'plane_id' to 'color_plane'
>   drm/i915: Pass the plane to icl_program_input_csc_coeff()

Entire series pushed to dinq. Thanks for the reviews everyone.

-- 
Ville Syrjälä
Intel
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