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From: Will Deacon <will.deacon@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: mark.rutland@arm.com, vladimir.murzin@arm.com,
	catalin.marinas@arm.com, linux-kernel@vger.kernel.org,
	Andre Przywara <andre.przywara@arm.com>,
	dave.martin@arm.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 1/7] arm64: capabilities: Merge entries for ARM64_WORKAROUND_CLEAN_CACHE
Date: Thu, 6 Dec 2018 09:58:27 +0000	[thread overview]
Message-ID: <20181206095825.GA22201@arm.com> (raw)
In-Reply-To: <b61f749d-9d65-fb76-74b5-b999fecad42b@arm.com>

On Wed, Dec 05, 2018 at 05:14:53PM +0000, Suzuki K Poulose wrote:
> On 05/12/2018 15:02, Will Deacon wrote:
> >On Fri, Nov 30, 2018 at 05:18:00PM +0000, Suzuki K Poulose wrote:
> >>diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> >>index 12f93e4d..2e26375 100644
> >>--- a/arch/arm64/include/asm/cputype.h
> >>+++ b/arch/arm64/include/asm/cputype.h
> >>@@ -151,6 +151,7 @@ struct midr_range {
> >>  		.rv_max = MIDR_CPU_VAR_REV(v_max, r_max),	\
> >>  	}
> >>+#define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max)
> >
> >What's the point of this macro?
> 
> That can be used to specify a set of MIDRs which has the same "variant" but a
> range of "revisions". This is used for the A53 errata and also for the Cavium
> errata in the following patch.

Gah, I read this at least 10 times and I /still/ failed to spot the extra
'v' argument to MIDR_RANGE!

Ignore my silly comment; I'll queue this up today. Thanks.

Will

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WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will.deacon@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, catalin.marinas@arm.com,
	dave.martin@arm.com, mark.rutland@arm.com,
	vladimir.murzin@arm.com, Andre Przywara <andre.przywara@arm.com>
Subject: Re: [PATCH v2 1/7] arm64: capabilities: Merge entries for ARM64_WORKAROUND_CLEAN_CACHE
Date: Thu, 6 Dec 2018 09:58:27 +0000	[thread overview]
Message-ID: <20181206095825.GA22201@arm.com> (raw)
In-Reply-To: <b61f749d-9d65-fb76-74b5-b999fecad42b@arm.com>

On Wed, Dec 05, 2018 at 05:14:53PM +0000, Suzuki K Poulose wrote:
> On 05/12/2018 15:02, Will Deacon wrote:
> >On Fri, Nov 30, 2018 at 05:18:00PM +0000, Suzuki K Poulose wrote:
> >>diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> >>index 12f93e4d..2e26375 100644
> >>--- a/arch/arm64/include/asm/cputype.h
> >>+++ b/arch/arm64/include/asm/cputype.h
> >>@@ -151,6 +151,7 @@ struct midr_range {
> >>  		.rv_max = MIDR_CPU_VAR_REV(v_max, r_max),	\
> >>  	}
> >>+#define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max)
> >
> >What's the point of this macro?
> 
> That can be used to specify a set of MIDRs which has the same "variant" but a
> range of "revisions". This is used for the A53 errata and also for the Cavium
> errata in the following patch.

Gah, I read this at least 10 times and I /still/ failed to spot the extra
'v' argument to MIDR_RANGE!

Ignore my silly comment; I'll queue this up today. Thanks.

Will

  reply	other threads:[~2018-12-06  9:58 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-30 17:17 [PATCH v2 0/7] arm64: capabilities: Optimize checking and enabling Suzuki K Poulose
2018-11-30 17:17 ` Suzuki K Poulose
2018-11-30 17:18 ` [PATCH v2 1/7] arm64: capabilities: Merge entries for ARM64_WORKAROUND_CLEAN_CACHE Suzuki K Poulose
2018-11-30 17:18   ` Suzuki K Poulose
2018-12-05 15:02   ` Will Deacon
2018-12-05 15:02     ` Will Deacon
2018-12-05 17:14     ` Suzuki K Poulose
2018-12-05 17:14       ` Suzuki K Poulose
2018-12-06  9:58       ` Will Deacon [this message]
2018-12-06  9:58         ` Will Deacon
2018-11-30 17:18 ` [PATCH v2 2/7] arm64: capabilities: Merge duplicate Cavium erratum entries Suzuki K Poulose
2018-11-30 17:18   ` Suzuki K Poulose
2018-11-30 17:18 ` [PATCH v2 3/7] arm64: capabilities: Merge duplicate entries for Qualcomm erratum 1003 Suzuki K Poulose
2018-11-30 17:18   ` Suzuki K Poulose
2018-11-30 17:18 ` [PATCH v2 4/7] arm64: capabilities: Speed up capability lookup Suzuki K Poulose
2018-11-30 17:18   ` Suzuki K Poulose
2018-11-30 17:18 ` [PATCH v2 5/7] arm64: capabilities: Optimize this_cpu_has_cap Suzuki K Poulose
2018-11-30 17:18   ` Suzuki K Poulose
2018-11-30 17:18 ` [PATCH v2 6/7] arm64: capabilities: Use linear array for detection and verification Suzuki K Poulose
2018-11-30 17:18   ` Suzuki K Poulose
2018-11-30 17:18 ` [PATCH v2 7/7] arm64: capabilities: Batch cpu_enable callbacks Suzuki K Poulose
2018-11-30 17:18   ` Suzuki K Poulose

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