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From: "Roger Pau Monné" <roger.pau@citrix.com>
To: "Tian, Kevin" <kevin.tian@intel.com>
Cc: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>,
	Wei Liu <wei.liu2@citrix.com>,
	"Nakajima, Jun" <jun.nakajima@intel.com>,
	Jan Beulich <JBeulich@suse.com>,
	Andrew Cooper <andrew.cooper3@citrix.com>
Subject: Re: Interrupt injection with ISR set on Intel hardware
Date: Wed, 12 Dec 2018 13:17:30 +0100	[thread overview]
Message-ID: <20181212121730.kprvmtyhrwyhm62t@mac> (raw)
In-Reply-To: <AADFC41AFE54684AB9EE6CBC0274A5D19BE9DB2A@SHSMSX101.ccr.corp.intel.com>

On Wed, Dec 12, 2018 at 11:48:52AM +0000, Tian, Kevin wrote:
> > From: Roger Pau Monné [mailto:roger.pau@citrix.com]
> > Sent: Wednesday, December 12, 2018 7:25 PM
> > 
> > On Wed, Dec 12, 2018 at 10:36:44AM +0000, Tian, Kevin wrote:
> > > > From: Roger Pau Monné [mailto:roger.pau@citrix.com]
> > > > Sent: Monday, October 15, 2018 6:30 PM
> > > > (XEN)   [22642] POWER    TYPE 4
> > > > (XEN)   [22643] IDLE     PPR 0x00000020
> > > > (XEN)                    IRR
> > > >
> > 00000000000000000000000000000000000000000000000000000000000000
> > > > 00
> > > > (XEN)                    ISR
> > > >
> > 00000000020000000000000000000000000000000000000000000000000000
> > > > 00
> > > > (XEN)   [22644] WAKE     PPR 0x00000020
> > > > (XEN)                    IRR
> > > >
> > 00000000020000000000000000000000000000000000000000000000000000
> > > > 00
> > > > (XEN)                    ISR
> > > >
> > 00000000020000000000000000000000000000000000000000000000000000
> > > > 00
> > >
> > > looks pending IRR (0x21) doesn't always trigger a spurious interrupt?
> > 
> > Yes, that's correct. Having a pending IRR and going idle doesn't
> > always trigger the spurious interrupt re-injection.
> > 
> > > is it a fixed pattern after how many rounds of Cstate enter/exit with
> > > pending IRR(0x21) then you see assertion happened (in this example
> > > it happens at 3rd time)?
> > 
> > It's not a fixed pattern, here's another trace with IRR(0x21) being
> > pending just once during the Cstate transitions:
> 
> did you observe a case where such asset may occur when IRR(0x21)
> is cleared but ISR (0x21) is set?

No, I've always seen both ISR and IRR set when the interrupt injection
happens. This of course doesn't mean it's not possible, but I have not
seen any trace with ISR(0x21) set and IRR(0x21) clear.

Thanks, Roger.

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  reply	other threads:[~2018-12-12 12:17 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-15 10:30 Interrupt injection with ISR set on Intel hardware Roger Pau Monné
2018-10-15 12:06 ` Andrew Cooper
2018-10-22  7:33   ` Chao Gao
2018-10-22  7:57     ` Andrew Cooper
2018-10-29 11:22     ` Roger Pau Monné
2018-10-25 12:51   ` Jan Beulich
2018-10-25 13:02     ` Andrew Cooper
2018-10-25 13:57       ` Jan Beulich
2018-10-30  6:59         ` Tian, Kevin
     [not found]         ` <AADFC41AFE54684AB9EE6CBC0274A5D19BE2BAB0@SHSMSX101.ccr.corp.intel.com>
2018-11-01  0:40           ` Tian, Kevin
2018-11-01  9:18             ` Andrew Cooper
2018-11-28  9:19               ` Roger Pau Monné
2018-12-02  8:52                 ` Tian, Kevin
2018-10-29 16:33 ` Jan Beulich
2018-10-29 16:44   ` Andrew Cooper
2018-10-29 16:58     ` Jan Beulich
2018-10-29 17:06       ` Andrew Cooper
2018-10-30  7:32         ` Jan Beulich
2018-10-29 16:55   ` Roger Pau Monné
2018-12-12 10:36 ` Tian, Kevin
2018-12-12 11:24   ` Roger Pau Monné
2018-12-12 11:48     ` Tian, Kevin
2018-12-12 12:17       ` Roger Pau Monné [this message]
2018-12-13  1:28         ` Tian, Kevin
2018-12-13  8:36           ` Jan Beulich
2018-12-13  9:03             ` Tian, Kevin
2018-12-13  8:52           ` Roger Pau Monné
     [not found]         ` <AADFC41AFE54684AB9EE6CBC0274A5D19BE9E951@SHSMSX101.ccr.corp.intel.com>
2018-12-13  2:44           ` Tian, Kevin
2018-12-13  8:39             ` Roger Pau Monné
2018-12-13  9:04               ` Tian, Kevin

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