From: Bjorn Helgaas <helgaas@kernel.org>
To: Jianjun Wang <jianjun.wang@mediatek.com>
Cc: ryder.lee@mediatek.com, robh+dt@kernel.org,
lorenzo.pieralisi@arm.com, matthias.bgg@gmail.com,
linux-pci@vger.kernel.org, mark.rutland@arm.com,
devicetree@vger.kernel.org, youlin.pei@mediatek.com,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
honghui.zhang@mediatek.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 2/2] PCI: mediatek: Add controller support for MT7629
Date: Mon, 17 Dec 2018 08:32:47 -0600 [thread overview]
Message-ID: <20181217143247.GK20725@google.com> (raw)
In-Reply-To: <1545034779.8528.8.camel@mhfsdcap03>
On Mon, Dec 17, 2018 at 04:19:39PM +0800, Jianjun Wang wrote:
> On Thu, 2018-12-13 at 08:55 -0600, Bjorn Helgaas wrote:
> > On Thu, Dec 06, 2018 at 09:09:13AM +0800, Jianjun Wang wrote:
> > > The read value of BAR0 is 0xffff_ffff, it's size will be calculated as 4GB
> > > in arm64 but bogus alignment values at arm32, the pcie device and devices
> > > behind this bridge will not be enabled. Fix it's BAR0 resource size to
> > > guarantee the pcie devices will be enabled correctly.
> >
> > So this is a hardware erratum? Per spec, a memory BAR has bit 0 hardwired
> > to 0, and an IO BAR has bit 1 hardwired to 0.
>
> Yes, it only works properly on 64bit platform.
I don't understand. BARs are supposed to work the same regardless of
whether it's a 32- or 64-bit platform. If this is a workaround for a
hardware defect, please just say that explicitly.
Bjorn
WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Helgaas <helgaas@kernel.org>
To: Jianjun Wang <jianjun.wang@mediatek.com>
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
lorenzo.pieralisi@arm.com, linux-pci@vger.kernel.org,
youlin.pei@mediatek.com, linux-kernel@vger.kernel.org,
robh+dt@kernel.org, ryder.lee@mediatek.com,
linux-mediatek@lists.infradead.org, honghui.zhang@mediatek.com,
matthias.bgg@gmail.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 2/2] PCI: mediatek: Add controller support for MT7629
Date: Mon, 17 Dec 2018 08:32:47 -0600 [thread overview]
Message-ID: <20181217143247.GK20725@google.com> (raw)
In-Reply-To: <1545034779.8528.8.camel@mhfsdcap03>
On Mon, Dec 17, 2018 at 04:19:39PM +0800, Jianjun Wang wrote:
> On Thu, 2018-12-13 at 08:55 -0600, Bjorn Helgaas wrote:
> > On Thu, Dec 06, 2018 at 09:09:13AM +0800, Jianjun Wang wrote:
> > > The read value of BAR0 is 0xffff_ffff, it's size will be calculated as 4GB
> > > in arm64 but bogus alignment values at arm32, the pcie device and devices
> > > behind this bridge will not be enabled. Fix it's BAR0 resource size to
> > > guarantee the pcie devices will be enabled correctly.
> >
> > So this is a hardware erratum? Per spec, a memory BAR has bit 0 hardwired
> > to 0, and an IO BAR has bit 1 hardwired to 0.
>
> Yes, it only works properly on 64bit platform.
I don't understand. BARs are supposed to work the same regardless of
whether it's a 32- or 64-bit platform. If this is a workaround for a
hardware defect, please just say that explicitly.
Bjorn
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next prev parent reply other threads:[~2018-12-17 14:32 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-06 1:09 [PATCH 0/2] PCI: mediatek: Add support for MT7629 Jianjun Wang
2018-12-06 1:09 ` Jianjun Wang
2018-12-06 1:09 ` Jianjun Wang
2018-12-06 1:09 ` [PATCH 1/2] dt-bindings: PCI: " Jianjun Wang
2018-12-06 1:09 ` Jianjun Wang
2018-12-06 1:09 ` Jianjun Wang
2018-12-19 20:38 ` Rob Herring
2018-12-19 20:38 ` Rob Herring
2018-12-19 20:38 ` Rob Herring
2018-12-06 1:09 ` [PATCH 2/2] PCI: mediatek: Add controller " Jianjun Wang
2018-12-06 1:09 ` Jianjun Wang
2018-12-06 1:09 ` Jianjun Wang
2018-12-06 5:53 ` Honghui Zhang
2018-12-06 5:53 ` Honghui Zhang
2018-12-06 5:53 ` Honghui Zhang
2018-12-07 12:56 ` Jianjun Wang
2018-12-07 12:56 ` Jianjun Wang
2018-12-07 12:56 ` Jianjun Wang
2018-12-12 5:43 ` Honghui Zhang
2018-12-12 5:43 ` Honghui Zhang
2018-12-12 5:43 ` Honghui Zhang
2018-12-13 3:39 ` Ryder Lee
2018-12-13 3:39 ` Ryder Lee
2018-12-13 3:39 ` Ryder Lee
2018-12-17 7:51 ` Jianjun Wang
2018-12-17 7:51 ` Jianjun Wang
2018-12-17 7:51 ` Jianjun Wang
2018-12-13 14:55 ` Bjorn Helgaas
2018-12-13 14:55 ` Bjorn Helgaas
2018-12-17 8:19 ` Jianjun Wang
2018-12-17 8:19 ` Jianjun Wang
2018-12-17 8:19 ` Jianjun Wang
2018-12-17 14:32 ` Bjorn Helgaas [this message]
2018-12-17 14:32 ` Bjorn Helgaas
2018-12-17 15:46 ` Lorenzo Pieralisi
2018-12-17 15:46 ` Lorenzo Pieralisi
2018-12-18 9:19 ` Jianjun Wang
2018-12-18 9:19 ` Jianjun Wang
2018-12-18 9:19 ` Jianjun Wang
2018-12-18 15:32 ` Lorenzo Pieralisi
2018-12-18 15:32 ` Lorenzo Pieralisi
2018-12-21 13:13 ` Jianjun Wang
2018-12-21 13:13 ` Jianjun Wang
2018-12-21 13:13 ` Jianjun Wang
2018-12-20 18:20 ` Bjorn Helgaas
2018-12-20 18:20 ` Bjorn Helgaas
2018-12-24 11:40 ` Jianjun Wang
2018-12-24 11:40 ` Jianjun Wang
2018-12-24 11:40 ` Jianjun Wang
2019-01-23 15:40 ` Lorenzo Pieralisi
2019-01-23 15:40 ` Lorenzo Pieralisi
2019-02-19 7:01 ` Jianjun Wang
2019-02-19 7:01 ` Jianjun Wang
2019-02-19 7:01 ` Jianjun Wang
2019-02-19 15:03 ` Lorenzo Pieralisi
2019-02-19 15:03 ` Lorenzo Pieralisi
2019-06-28 6:38 ` Jianjun Wang
2019-06-28 6:38 ` Jianjun Wang
2019-06-28 6:38 ` Jianjun Wang
2018-12-06 1:40 ` [PATCH 0/2] PCI: mediatek: Add " Ryder Lee
2018-12-06 1:40 ` Ryder Lee
2018-12-06 1:40 ` Ryder Lee
-- strict thread matches above, loose matches on Subject: below --
2018-12-05 7:57 Jianjun Wang
2018-12-05 7:57 ` [PATCH 2/2] PCI: mediatek: Add controller " Jianjun Wang
2018-12-05 7:30 [PATCH 0/2] PCI: mediatek: Add " Jianjun Wang
2018-12-05 7:30 ` [PATCH 2/2] PCI: mediatek: Add controller " Jianjun Wang
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