[PATCH 0/2] irqchip/meson-gpio: Add support for Meson-G12A SoC

[PATCH 0/2] irqchip/meson-gpio: Add support for Meson-G12A SoC

[Xingyu Chen]

This series try to add GPIO interrupt controller support for Meson-G12A SoCs.
Although the total number of pins is the same as the Meson-AXG SoC, the gpio
banks and irq numbers are different. To avoid confusion on use, i think the
new compatible string is needed.

Xingyu Chen (2):
  dt-bindings: interrupt-controller: New binding for Meson-G12A SoC
  irqchip/meson-gpio: Add support for Meson-G12A SoC

 .../interrupt-controller/amlogic,meson-gpio-intc.txt         | 1 +
 drivers/irqchip/irq-meson-gpio.c                             | 5 +++++
 2 files changed, 6 insertions(+)

-- 
2.19.2


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[PATCH 0/2] irqchip/meson-gpio: Add support for Meson-G12A SoC

[Xingyu Chen]

This series try to add GPIO interrupt controller support for Meson-G12A SoCs.
Although the total number of pins is the same as the Meson-AXG SoC, the gpio
banks and irq numbers are different. To avoid confusion on use, i think the
new compatible string is needed.

Xingyu Chen (2):
  dt-bindings: interrupt-controller: New binding for Meson-G12A SoC
  irqchip/meson-gpio: Add support for Meson-G12A SoC

 .../interrupt-controller/amlogic,meson-gpio-intc.txt         | 1 +
 drivers/irqchip/irq-meson-gpio.c                             | 5 +++++
 2 files changed, 6 insertions(+)

-- 
2.19.2

[PATCH 0/2] irqchip/meson-gpio: Add support for Meson-G12A SoC

[Xingyu Chen]

This series try to add GPIO interrupt controller support for Meson-G12A SoCs.
Although the total number of pins is the same as the Meson-AXG SoC, the gpio
banks and irq numbers are different. To avoid confusion on use, i think the
new compatible string is needed.

Xingyu Chen (2):
  dt-bindings: interrupt-controller: New binding for Meson-G12A SoC
  irqchip/meson-gpio: Add support for Meson-G12A SoC

 .../interrupt-controller/amlogic,meson-gpio-intc.txt         | 1 +
 drivers/irqchip/irq-meson-gpio.c                             | 5 +++++
 2 files changed, 6 insertions(+)

-- 
2.19.2

[PATCH 0/2] irqchip/meson-gpio: Add support for Meson-G12A SoC

[Xingyu Chen]

This series try to add GPIO interrupt controller support for Meson-G12A SoCs.
Although the total number of pins is the same as the Meson-AXG SoC, the gpio
banks and irq numbers are different. To avoid confusion on use, i think the
new compatible string is needed.

Xingyu Chen (2):
  dt-bindings: interrupt-controller: New binding for Meson-G12A SoC
  irqchip/meson-gpio: Add support for Meson-G12A SoC

 .../interrupt-controller/amlogic,meson-gpio-intc.txt         | 1 +
 drivers/irqchip/irq-meson-gpio.c                             | 5 +++++
 2 files changed, 6 insertions(+)

-- 
2.19.2


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[PATCH 1/2] dt-bindings: interrupt-controller: New binding for Meson-G12A SoC

[Xingyu Chen]

Update the dt-binding document to support new compatible string for the
GPIO interrupt controller which found in Amlogic's Meson-G12A SoC.

Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
---
 .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt    | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
index 1502a51548bb..7d531d5fff29 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
@@ -15,6 +15,7 @@ Required properties:
     "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or
     "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912)
     "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)
+    "amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)
 - reg : Specifies base physical address and size of the registers.
 - interrupt-controller : Identifies the node as an interrupt controller.
 - #interrupt-cells : Specifies the number of cells needed to encode an
-- 
2.19.2


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[PATCH 1/2] dt-bindings: interrupt-controller: New binding for Meson-G12A SoC

[Xingyu Chen]

Update the dt-binding document to support new compatible string for the
GPIO interrupt controller which found in Amlogic's Meson-G12A SoC.

Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
---
 .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt    | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
index 1502a51548bb..7d531d5fff29 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
@@ -15,6 +15,7 @@ Required properties:
     "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or
     "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912)
     "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)
+    "amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)
 - reg : Specifies base physical address and size of the registers.
 - interrupt-controller : Identifies the node as an interrupt controller.
 - #interrupt-cells : Specifies the number of cells needed to encode an
-- 
2.19.2

[PATCH 1/2] dt-bindings: interrupt-controller: New binding for Meson-G12A SoC

[Xingyu Chen]

Update the dt-binding document to support new compatible string for the
GPIO interrupt controller which found in Amlogic's Meson-G12A SoC.

Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
---
 .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt    | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
index 1502a51548bb..7d531d5fff29 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
@@ -15,6 +15,7 @@ Required properties:
     "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or
     "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912)
     "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)
+    "amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)
 - reg : Specifies base physical address and size of the registers.
 - interrupt-controller : Identifies the node as an interrupt controller.
 - #interrupt-cells : Specifies the number of cells needed to encode an
-- 
2.19.2

[PATCH 1/2] dt-bindings: interrupt-controller: New binding for Meson-G12A SoC

[Xingyu Chen]

Update the dt-binding document to support new compatible string for the
GPIO interrupt controller which found in Amlogic's Meson-G12A SoC.

Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
---
 .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt    | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
index 1502a51548bb..7d531d5fff29 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
@@ -15,6 +15,7 @@ Required properties:
     "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or
     "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912)
     "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)
+    "amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)
 - reg : Specifies base physical address and size of the registers.
 - interrupt-controller : Identifies the node as an interrupt controller.
 - #interrupt-cells : Specifies the number of cells needed to encode an
-- 
2.19.2


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Re: [PATCH 1/2] dt-bindings: interrupt-controller: New binding for Meson-G12A SoC

[Rob Herring]

On Mon, 3 Dec 2018 14:13:23 +0800, Xingyu Chen wrote:
> Update the dt-binding document to support new compatible string for the
> GPIO interrupt controller which found in Amlogic's Meson-G12A SoC.
> 
> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
> ---
>  .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt    | 1 +
>  1 file changed, 1 insertion(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

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Re: [PATCH 1/2] dt-bindings: interrupt-controller: New binding for Meson-G12A SoC

[Rob Herring]

On Mon, 3 Dec 2018 14:13:23 +0800, Xingyu Chen wrote:
> Update the dt-binding document to support new compatible string for the
> GPIO interrupt controller which found in Amlogic's Meson-G12A SoC.
> 
> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
> ---
>  .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt    | 1 +
>  1 file changed, 1 insertion(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH 1/2] dt-bindings: interrupt-controller: New binding for Meson-G12A SoC

[Rob Herring]

On Mon, 3 Dec 2018 14:13:23 +0800, Xingyu Chen wrote:
> Update the dt-binding document to support new compatible string for the
> GPIO interrupt controller which found in Amlogic's Meson-G12A SoC.
> 
> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
> ---
>  .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt    | 1 +
>  1 file changed, 1 insertion(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH 1/2] dt-bindings: interrupt-controller: New binding for Meson-G12A SoC

[Rob Herring]

On Mon, 3 Dec 2018 14:13:23 +0800, Xingyu Chen wrote:
> Update the dt-binding document to support new compatible string for the
> GPIO interrupt controller which found in Amlogic's Meson-G12A SoC.
> 
> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
> ---
>  .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt    | 1 +
>  1 file changed, 1 insertion(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

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[PATCH 2/2] irqchip/meson-gpio: Add support for Meson-G12A SoC

[Xingyu Chen]

The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:

- 223:100 undefined (no interrupt)
- 99:97   3 pins on bank GPIOE
- 96:77   20 pins on bank GPIOX
- 76:61   16 pins on bank GPIOA
- 60:53   8 pins on bank GPIOC
- 52:37   16 pins on bank BOOT
- 36:28   9 pins on bank GPIOH
- 27:12   16 pins on bank GPIOZ
- 11:0    12 pins in the AO domain

Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
---
 drivers/irqchip/irq-meson-gpio.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index 7b531fd075b8..971e8dea069a 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -67,12 +67,17 @@ static const struct meson_gpio_irq_params axg_params = {
 	.nr_hwirq = 100,
 };
 
+static const struct meson_gpio_irq_params g12a_params = {
+	.nr_hwirq = 100,
+};
+
 static const struct of_device_id meson_irq_gpio_matches[] = {
 	{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
 	{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
 	{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params },
 	{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
 	{ .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
+	{ .compatible = "amlogic,meson-g12a-gpio-intc", .data = &g12a_params },
 	{ }
 };
 
-- 
2.19.2


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[PATCH 2/2] irqchip/meson-gpio: Add support for Meson-G12A SoC

[Xingyu Chen]

The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:

- 223:100 undefined (no interrupt)
- 99:97   3 pins on bank GPIOE
- 96:77   20 pins on bank GPIOX
- 76:61   16 pins on bank GPIOA
- 60:53   8 pins on bank GPIOC
- 52:37   16 pins on bank BOOT
- 36:28   9 pins on bank GPIOH
- 27:12   16 pins on bank GPIOZ
- 11:0    12 pins in the AO domain

Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
---
 drivers/irqchip/irq-meson-gpio.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index 7b531fd075b8..971e8dea069a 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -67,12 +67,17 @@ static const struct meson_gpio_irq_params axg_params = {
 	.nr_hwirq = 100,
 };
 
+static const struct meson_gpio_irq_params g12a_params = {
+	.nr_hwirq = 100,
+};
+
 static const struct of_device_id meson_irq_gpio_matches[] = {
 	{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
 	{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
 	{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params },
 	{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
 	{ .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
+	{ .compatible = "amlogic,meson-g12a-gpio-intc", .data = &g12a_params },
 	{ }
 };
 
-- 
2.19.2

[PATCH 2/2] irqchip/meson-gpio: Add support for Meson-G12A SoC

[Xingyu Chen]

The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:

- 223:100 undefined (no interrupt)
- 99:97   3 pins on bank GPIOE
- 96:77   20 pins on bank GPIOX
- 76:61   16 pins on bank GPIOA
- 60:53   8 pins on bank GPIOC
- 52:37   16 pins on bank BOOT
- 36:28   9 pins on bank GPIOH
- 27:12   16 pins on bank GPIOZ
- 11:0    12 pins in the AO domain

Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
---
 drivers/irqchip/irq-meson-gpio.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index 7b531fd075b8..971e8dea069a 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -67,12 +67,17 @@ static const struct meson_gpio_irq_params axg_params = {
 	.nr_hwirq = 100,
 };
 
+static const struct meson_gpio_irq_params g12a_params = {
+	.nr_hwirq = 100,
+};
+
 static const struct of_device_id meson_irq_gpio_matches[] = {
 	{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
 	{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
 	{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params },
 	{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
 	{ .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
+	{ .compatible = "amlogic,meson-g12a-gpio-intc", .data = &g12a_params },
 	{ }
 };
 
-- 
2.19.2


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Re: [PATCH 2/2] irqchip/meson-gpio: Add support for Meson-G12A SoC

[Jerome Brunet]

On Mon, 2018-12-03 at 14:13 +0800, Xingyu Chen wrote:
> The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
> other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
> 
> - 223:100 undefined (no interrupt)
> - 99:97   3 pins on bank GPIOE
> - 96:77   20 pins on bank GPIOX
> - 76:61   16 pins on bank GPIOA
> - 60:53   8 pins on bank GPIOC
> - 52:37   16 pins on bank BOOT
> - 36:28   9 pins on bank GPIOH
> - 27:12   16 pins on bank GPIOZ
> - 11:0    12 pins in the AO domain
> 
> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
> ---
>  drivers/irqchip/irq-meson-gpio.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-
> gpio.c
> index 7b531fd075b8..971e8dea069a 100644
> --- a/drivers/irqchip/irq-meson-gpio.c
> +++ b/drivers/irqchip/irq-meson-gpio.c
> @@ -67,12 +67,17 @@ static const struct meson_gpio_irq_params axg_params = {
>  	.nr_hwirq = 100,
>  };
>  
> +static const struct meson_gpio_irq_params g12a_params = {
> +	.nr_hwirq = 100,
> +};
> +

Same comment as on i2c, the g12 seems compatible with the axg.
Is this patchset patchset really necessary ?

>  static const struct of_device_id meson_irq_gpio_matches[] = {
>  	{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
>  	{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params
> },
>  	{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params
> },
>  	{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
>  	{ .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
> +	{ .compatible = "amlogic,meson-g12a-gpio-intc", .data = &g12a_params
> },
>  	{ }
>  };
>  



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Re: [PATCH 2/2] irqchip/meson-gpio: Add support for Meson-G12A SoC

[Jerome Brunet]

On Mon, 2018-12-03 at 14:13 +0800, Xingyu Chen wrote:
> The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
> other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
> 
> - 223:100 undefined (no interrupt)
> - 99:97   3 pins on bank GPIOE
> - 96:77   20 pins on bank GPIOX
> - 76:61   16 pins on bank GPIOA
> - 60:53   8 pins on bank GPIOC
> - 52:37   16 pins on bank BOOT
> - 36:28   9 pins on bank GPIOH
> - 27:12   16 pins on bank GPIOZ
> - 11:0    12 pins in the AO domain
> 
> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
> ---
>  drivers/irqchip/irq-meson-gpio.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-
> gpio.c
> index 7b531fd075b8..971e8dea069a 100644
> --- a/drivers/irqchip/irq-meson-gpio.c
> +++ b/drivers/irqchip/irq-meson-gpio.c
> @@ -67,12 +67,17 @@ static const struct meson_gpio_irq_params axg_params = {
>  	.nr_hwirq = 100,
>  };
>  
> +static const struct meson_gpio_irq_params g12a_params = {
> +	.nr_hwirq = 100,
> +};
> +

Same comment as on i2c, the g12 seems compatible with the axg.
Is this patchset patchset really necessary ?

>  static const struct of_device_id meson_irq_gpio_matches[] = {
>  	{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
>  	{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params
> },
>  	{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params
> },
>  	{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
>  	{ .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
> +	{ .compatible = "amlogic,meson-g12a-gpio-intc", .data = &g12a_params
> },
>  	{ }
>  };
>  

Re: [PATCH 2/2] irqchip/meson-gpio: Add support for Meson-G12A SoC

[Jerome Brunet]

On Mon, 2018-12-03 at 14:13 +0800, Xingyu Chen wrote:
> The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
> other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
> 
> - 223:100 undefined (no interrupt)
> - 99:97   3 pins on bank GPIOE
> - 96:77   20 pins on bank GPIOX
> - 76:61   16 pins on bank GPIOA
> - 60:53   8 pins on bank GPIOC
> - 52:37   16 pins on bank BOOT
> - 36:28   9 pins on bank GPIOH
> - 27:12   16 pins on bank GPIOZ
> - 11:0    12 pins in the AO domain
> 
> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
> ---
>  drivers/irqchip/irq-meson-gpio.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-
> gpio.c
> index 7b531fd075b8..971e8dea069a 100644
> --- a/drivers/irqchip/irq-meson-gpio.c
> +++ b/drivers/irqchip/irq-meson-gpio.c
> @@ -67,12 +67,17 @@ static const struct meson_gpio_irq_params axg_params = {
>  	.nr_hwirq = 100,
>  };
>  
> +static const struct meson_gpio_irq_params g12a_params = {
> +	.nr_hwirq = 100,
> +};
> +

Same comment as on i2c, the g12 seems compatible with the axg.
Is this patchset patchset really necessary ?

>  static const struct of_device_id meson_irq_gpio_matches[] = {
>  	{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
>  	{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params
> },
>  	{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params
> },
>  	{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
>  	{ .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
> +	{ .compatible = "amlogic,meson-g12a-gpio-intc", .data = &g12a_params
> },
>  	{ }
>  };
>  



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Re: [PATCH 2/2] irqchip/meson-gpio: Add support for Meson-G12A SoC

[Xingyu Chen]

On 2018/12/3 17:19, Jerome Brunet wrote:
> On Mon, 2018-12-03 at 14:13 +0800, Xingyu Chen wrote:
>> The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
>> other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
>>
>> - 223:100 undefined (no interrupt)
>> - 99:97   3 pins on bank GPIOE
>> - 96:77   20 pins on bank GPIOX
>> - 76:61   16 pins on bank GPIOA
>> - 60:53   8 pins on bank GPIOC
>> - 52:37   16 pins on bank BOOT
>> - 36:28   9 pins on bank GPIOH
>> - 27:12   16 pins on bank GPIOZ
>> - 11:0    12 pins in the AO domain
>>
>> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
>> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
>> ---
>>   drivers/irqchip/irq-meson-gpio.c | 5 +++++
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-
>> gpio.c
>> index 7b531fd075b8..971e8dea069a 100644
>> --- a/drivers/irqchip/irq-meson-gpio.c
>> +++ b/drivers/irqchip/irq-meson-gpio.c
>> @@ -67,12 +67,17 @@ static const struct meson_gpio_irq_params axg_params = {
>>   	.nr_hwirq = 100,
>>   };
>>   
>> +static const struct meson_gpio_irq_params g12a_params = {
>> +	.nr_hwirq = 100,
>> +};
>> +
> 
> Same comment as on i2c, the g12 seems compatible with the axg.
> Is this patchset patchset really necessary ?
> 
Although the total number of pins is the same as the Meson-AXG SoC, the 
gpio banks and irq numbers are different. To avoid confusion on use, i 
think the new compatible string is needed.
>>   static const struct of_device_id meson_irq_gpio_matches[] = {
>>   	{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
>>   	{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params
>> },
>>   	{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params
>> },
>>   	{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
>>   	{ .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
>> +	{ .compatible = "amlogic,meson-g12a-gpio-intc", .data = &g12a_params
>> },
>>   	{ }
>>   };
>>   
> 
> 
> .
> 

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Re: [PATCH 2/2] irqchip/meson-gpio: Add support for Meson-G12A SoC

[Xingyu Chen]

On 2018/12/3 17:19, Jerome Brunet wrote:
> On Mon, 2018-12-03 at 14:13 +0800, Xingyu Chen wrote:
>> The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
>> other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
>>
>> - 223:100 undefined (no interrupt)
>> - 99:97   3 pins on bank GPIOE
>> - 96:77   20 pins on bank GPIOX
>> - 76:61   16 pins on bank GPIOA
>> - 60:53   8 pins on bank GPIOC
>> - 52:37   16 pins on bank BOOT
>> - 36:28   9 pins on bank GPIOH
>> - 27:12   16 pins on bank GPIOZ
>> - 11:0    12 pins in the AO domain
>>
>> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
>> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
>> ---
>>   drivers/irqchip/irq-meson-gpio.c | 5 +++++
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-
>> gpio.c
>> index 7b531fd075b8..971e8dea069a 100644
>> --- a/drivers/irqchip/irq-meson-gpio.c
>> +++ b/drivers/irqchip/irq-meson-gpio.c
>> @@ -67,12 +67,17 @@ static const struct meson_gpio_irq_params axg_params = {
>>   	.nr_hwirq = 100,
>>   };
>>   
>> +static const struct meson_gpio_irq_params g12a_params = {
>> +	.nr_hwirq = 100,
>> +};
>> +
> 
> Same comment as on i2c, the g12 seems compatible with the axg.
> Is this patchset patchset really necessary ?
> 
Although the total number of pins is the same as the Meson-AXG SoC, the 
gpio banks and irq numbers are different. To avoid confusion on use, i 
think the new compatible string is needed.
>>   static const struct of_device_id meson_irq_gpio_matches[] = {
>>   	{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
>>   	{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params
>> },
>>   	{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params
>> },
>>   	{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
>>   	{ .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
>> +	{ .compatible = "amlogic,meson-g12a-gpio-intc", .data = &g12a_params
>> },
>>   	{ }
>>   };
>>   
> 
> 
> .
> 

Re: [PATCH 2/2] irqchip/meson-gpio: Add support for Meson-G12A SoC

[Xingyu Chen]

On 2018/12/3 17:19, Jerome Brunet wrote:
> On Mon, 2018-12-03 at 14:13 +0800, Xingyu Chen wrote:
>> The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
>> other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
>>
>> - 223:100 undefined (no interrupt)
>> - 99:97   3 pins on bank GPIOE
>> - 96:77   20 pins on bank GPIOX
>> - 76:61   16 pins on bank GPIOA
>> - 60:53   8 pins on bank GPIOC
>> - 52:37   16 pins on bank BOOT
>> - 36:28   9 pins on bank GPIOH
>> - 27:12   16 pins on bank GPIOZ
>> - 11:0    12 pins in the AO domain
>>
>> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
>> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
>> ---
>>   drivers/irqchip/irq-meson-gpio.c | 5 +++++
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-
>> gpio.c
>> index 7b531fd075b8..971e8dea069a 100644
>> --- a/drivers/irqchip/irq-meson-gpio.c
>> +++ b/drivers/irqchip/irq-meson-gpio.c
>> @@ -67,12 +67,17 @@ static const struct meson_gpio_irq_params axg_params = {
>>   	.nr_hwirq = 100,
>>   };
>>   
>> +static const struct meson_gpio_irq_params g12a_params = {
>> +	.nr_hwirq = 100,
>> +};
>> +
> 
> Same comment as on i2c, the g12 seems compatible with the axg.
> Is this patchset patchset really necessary ?
> 
Although the total number of pins is the same as the Meson-AXG SoC, the 
gpio banks and irq numbers are different. To avoid confusion on use, i 
think the new compatible string is needed.
>>   static const struct of_device_id meson_irq_gpio_matches[] = {
>>   	{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
>>   	{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params
>> },
>>   	{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params
>> },
>>   	{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
>>   	{ .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
>> +	{ .compatible = "amlogic,meson-g12a-gpio-intc", .data = &g12a_params
>> },
>>   	{ }
>>   };
>>   
> 
> 
> .
> 

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Re: [PATCH 2/2] irqchip/meson-gpio: Add support for Meson-G12A SoC

[Neil Armstrong]

On 03/12/2018 10:28, Xingyu Chen wrote:
> 
> 
> On 2018/12/3 17:19, Jerome Brunet wrote:
>> On Mon, 2018-12-03 at 14:13 +0800, Xingyu Chen wrote:
>>> The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
>>> other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
>>>
>>> - 223:100 undefined (no interrupt)
>>> - 99:97   3 pins on bank GPIOE
>>> - 96:77   20 pins on bank GPIOX
>>> - 76:61   16 pins on bank GPIOA
>>> - 60:53   8 pins on bank GPIOC
>>> - 52:37   16 pins on bank BOOT
>>> - 36:28   9 pins on bank GPIOH
>>> - 27:12   16 pins on bank GPIOZ
>>> - 11:0    12 pins in the AO domain
>>>
>>> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
>>> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
>>> ---
>>>   drivers/irqchip/irq-meson-gpio.c | 5 +++++
>>>   1 file changed, 5 insertions(+)
>>>
>>> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-
>>> gpio.c
>>> index 7b531fd075b8..971e8dea069a 100644
>>> --- a/drivers/irqchip/irq-meson-gpio.c
>>> +++ b/drivers/irqchip/irq-meson-gpio.c
>>> @@ -67,12 +67,17 @@ static const struct meson_gpio_irq_params axg_params = {
>>>       .nr_hwirq = 100,
>>>   };
>>>   +static const struct meson_gpio_irq_params g12a_params = {
>>> +    .nr_hwirq = 100,
>>> +};
>>> +
>>
>> Same comment as on i2c, the g12 seems compatible with the axg.
>> Is this patchset patchset really necessary ?
>>
> Although the total number of pins is the same as the Meson-AXG SoC, the gpio banks and irq numbers are different. To avoid confusion on use, i think the new compatible string is needed.

OK for the new compatible, but you can re-use the same struct like for i2c.

Neil

>>>   static const struct of_device_id meson_irq_gpio_matches[] = {
>>>       { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
>>>       { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params
>>> },
>>>       { .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params
>>> },
>>>       { .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
>>>       { .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
>>> +    { .compatible = "amlogic,meson-g12a-gpio-intc", .data = &g12a_params
>>> },
>>>       { }
>>>   };
>>>   
>>
>>
>> .
>>
> 
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Re: [PATCH 2/2] irqchip/meson-gpio: Add support for Meson-G12A SoC

[Neil Armstrong]

On 03/12/2018 10:28, Xingyu Chen wrote:
> 
> 
> On 2018/12/3 17:19, Jerome Brunet wrote:
>> On Mon, 2018-12-03 at 14:13 +0800, Xingyu Chen wrote:
>>> The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
>>> other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
>>>
>>> - 223:100 undefined (no interrupt)
>>> - 99:97   3 pins on bank GPIOE
>>> - 96:77   20 pins on bank GPIOX
>>> - 76:61   16 pins on bank GPIOA
>>> - 60:53   8 pins on bank GPIOC
>>> - 52:37   16 pins on bank BOOT
>>> - 36:28   9 pins on bank GPIOH
>>> - 27:12   16 pins on bank GPIOZ
>>> - 11:0    12 pins in the AO domain
>>>
>>> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
>>> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
>>> ---
>>>   drivers/irqchip/irq-meson-gpio.c | 5 +++++
>>>   1 file changed, 5 insertions(+)
>>>
>>> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-
>>> gpio.c
>>> index 7b531fd075b8..971e8dea069a 100644
>>> --- a/drivers/irqchip/irq-meson-gpio.c
>>> +++ b/drivers/irqchip/irq-meson-gpio.c
>>> @@ -67,12 +67,17 @@ static const struct meson_gpio_irq_params axg_params = {
>>>       .nr_hwirq = 100,
>>>   };
>>>   +static const struct meson_gpio_irq_params g12a_params = {
>>> +    .nr_hwirq = 100,
>>> +};
>>> +
>>
>> Same comment as on i2c, the g12 seems compatible with the axg.
>> Is this patchset patchset really necessary ?
>>
> Although the total number of pins is the same as the Meson-AXG SoC, the gpio banks and irq numbers are different. To avoid confusion on use, i think the new compatible string is needed.

OK for the new compatible, but you can re-use the same struct like for i2c.

Neil

>>>   static const struct of_device_id meson_irq_gpio_matches[] = {
>>>       { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
>>>       { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params
>>> },
>>>       { .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params
>>> },
>>>       { .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
>>>       { .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
>>> +    { .compatible = "amlogic,meson-g12a-gpio-intc", .data = &g12a_params
>>> },
>>>       { }
>>>   };
>>>   
>>
>>
>> .
>>
> 
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Re: [PATCH 2/2] irqchip/meson-gpio: Add support for Meson-G12A SoC

[Neil Armstrong]

On 03/12/2018 10:28, Xingyu Chen wrote:
> 
> 
> On 2018/12/3 17:19, Jerome Brunet wrote:
>> On Mon, 2018-12-03 at 14:13 +0800, Xingyu Chen wrote:
>>> The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
>>> other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
>>>
>>> - 223:100 undefined (no interrupt)
>>> - 99:97   3 pins on bank GPIOE
>>> - 96:77   20 pins on bank GPIOX
>>> - 76:61   16 pins on bank GPIOA
>>> - 60:53   8 pins on bank GPIOC
>>> - 52:37   16 pins on bank BOOT
>>> - 36:28   9 pins on bank GPIOH
>>> - 27:12   16 pins on bank GPIOZ
>>> - 11:0    12 pins in the AO domain
>>>
>>> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
>>> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
>>> ---
>>>   drivers/irqchip/irq-meson-gpio.c | 5 +++++
>>>   1 file changed, 5 insertions(+)
>>>
>>> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-
>>> gpio.c
>>> index 7b531fd075b8..971e8dea069a 100644
>>> --- a/drivers/irqchip/irq-meson-gpio.c
>>> +++ b/drivers/irqchip/irq-meson-gpio.c
>>> @@ -67,12 +67,17 @@ static const struct meson_gpio_irq_params axg_params = {
>>>       .nr_hwirq = 100,
>>>   };
>>>   +static const struct meson_gpio_irq_params g12a_params = {
>>> +    .nr_hwirq = 100,
>>> +};
>>> +
>>
>> Same comment as on i2c, the g12 seems compatible with the axg.
>> Is this patchset patchset really necessary ?
>>
> Although the total number of pins is the same as the Meson-AXG SoC, the gpio banks and irq numbers are different. To avoid confusion on use, i think the new compatible string is needed.

OK for the new compatible, but you can re-use the same struct like for i2c.

Neil

>>>   static const struct of_device_id meson_irq_gpio_matches[] = {
>>>       { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
>>>       { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params
>>> },
>>>       { .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params
>>> },
>>>       { .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
>>>       { .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
>>> +    { .compatible = "amlogic,meson-g12a-gpio-intc", .data = &g12a_params
>>> },
>>>       { }
>>>   };
>>>   
>>
>>
>> .
>>
> 
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Re: [PATCH 2/2] irqchip/meson-gpio: Add support for Meson-G12A SoC

[Xingyu Chen]

On 2018/12/3 18:06, Neil Armstrong wrote:
> On 03/12/2018 10:28, Xingyu Chen wrote:
>>
>>
>> On 2018/12/3 17:19, Jerome Brunet wrote:
>>> On Mon, 2018-12-03 at 14:13 +0800, Xingyu Chen wrote:
>>>> The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
>>>> other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
>>>>
>>>> - 223:100 undefined (no interrupt)
>>>> - 99:97   3 pins on bank GPIOE
>>>> - 96:77   20 pins on bank GPIOX
>>>> - 76:61   16 pins on bank GPIOA
>>>> - 60:53   8 pins on bank GPIOC
>>>> - 52:37   16 pins on bank BOOT
>>>> - 36:28   9 pins on bank GPIOH
>>>> - 27:12   16 pins on bank GPIOZ
>>>> - 11:0    12 pins in the AO domain
>>>>
>>>> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
>>>> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
>>>> ---
>>>>    drivers/irqchip/irq-meson-gpio.c | 5 +++++
>>>>    1 file changed, 5 insertions(+)
>>>>
>>>> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-
>>>> gpio.c
>>>> index 7b531fd075b8..971e8dea069a 100644
>>>> --- a/drivers/irqchip/irq-meson-gpio.c
>>>> +++ b/drivers/irqchip/irq-meson-gpio.c
>>>> @@ -67,12 +67,17 @@ static const struct meson_gpio_irq_params axg_params = {
>>>>        .nr_hwirq = 100,
>>>>    };
>>>>    +static const struct meson_gpio_irq_params g12a_params = {
>>>> +    .nr_hwirq = 100,
>>>> +};
>>>> +
>>>
>>> Same comment as on i2c, the g12 seems compatible with the axg.
>>> Is this patchset patchset really necessary ?
>>>
>> Although the total number of pins is the same as the Meson-AXG SoC, the gpio banks and irq numbers are different. To avoid confusion on use, i think the new compatible string is needed.
> 
> OK for the new compatible, but you can re-use the same struct like for i2c.
> 
> Neil
> 
Thanks for your comment, I will fix it in the next version.

>>>>    static const struct of_device_id meson_irq_gpio_matches[] = {
>>>>        { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
>>>>        { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params
>>>> },
>>>>        { .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params
>>>> },
>>>>        { .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
>>>>        { .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
>>>> +    { .compatible = "amlogic,meson-g12a-gpio-intc", .data = &g12a_params
>>>> },
>>>>        { }
>>>>    };
>>>>    
>>>
>>>
>>> .
>>>
>>
>> _______________________________________________
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>> http://lists.infradead.org/mailman/listinfo/linux-amlogic
> 
> .
> 

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Re: [PATCH 2/2] irqchip/meson-gpio: Add support for Meson-G12A SoC

[Xingyu Chen]

On 2018/12/3 18:06, Neil Armstrong wrote:
> On 03/12/2018 10:28, Xingyu Chen wrote:
>>
>>
>> On 2018/12/3 17:19, Jerome Brunet wrote:
>>> On Mon, 2018-12-03 at 14:13 +0800, Xingyu Chen wrote:
>>>> The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
>>>> other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
>>>>
>>>> - 223:100 undefined (no interrupt)
>>>> - 99:97   3 pins on bank GPIOE
>>>> - 96:77   20 pins on bank GPIOX
>>>> - 76:61   16 pins on bank GPIOA
>>>> - 60:53   8 pins on bank GPIOC
>>>> - 52:37   16 pins on bank BOOT
>>>> - 36:28   9 pins on bank GPIOH
>>>> - 27:12   16 pins on bank GPIOZ
>>>> - 11:0    12 pins in the AO domain
>>>>
>>>> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
>>>> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
>>>> ---
>>>>    drivers/irqchip/irq-meson-gpio.c | 5 +++++
>>>>    1 file changed, 5 insertions(+)
>>>>
>>>> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-
>>>> gpio.c
>>>> index 7b531fd075b8..971e8dea069a 100644
>>>> --- a/drivers/irqchip/irq-meson-gpio.c
>>>> +++ b/drivers/irqchip/irq-meson-gpio.c
>>>> @@ -67,12 +67,17 @@ static const struct meson_gpio_irq_params axg_params = {
>>>>        .nr_hwirq = 100,
>>>>    };
>>>>    +static const struct meson_gpio_irq_params g12a_params = {
>>>> +    .nr_hwirq = 100,
>>>> +};
>>>> +
>>>
>>> Same comment as on i2c, the g12 seems compatible with the axg.
>>> Is this patchset patchset really necessary ?
>>>
>> Although the total number of pins is the same as the Meson-AXG SoC, the gpio banks and irq numbers are different. To avoid confusion on use, i think the new compatible string is needed.
> 
> OK for the new compatible, but you can re-use the same struct like for i2c.
> 
> Neil
> 
Thanks for your comment, I will fix it in the next version.

>>>>    static const struct of_device_id meson_irq_gpio_matches[] = {
>>>>        { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
>>>>        { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params
>>>> },
>>>>        { .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params
>>>> },
>>>>        { .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
>>>>        { .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
>>>> +    { .compatible = "amlogic,meson-g12a-gpio-intc", .data = &g12a_params
>>>> },
>>>>        { }
>>>>    };
>>>>    
>>>
>>>
>>> .
>>>
>>
>> _______________________________________________
>> linux-amlogic mailing list
>> linux-amlogic@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-amlogic
> 
> .
> 

Re: [PATCH 2/2] irqchip/meson-gpio: Add support for Meson-G12A SoC

[Xingyu Chen]

On 2018/12/3 18:06, Neil Armstrong wrote:
> On 03/12/2018 10:28, Xingyu Chen wrote:
>>
>>
>> On 2018/12/3 17:19, Jerome Brunet wrote:
>>> On Mon, 2018-12-03 at 14:13 +0800, Xingyu Chen wrote:
>>>> The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
>>>> other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
>>>>
>>>> - 223:100 undefined (no interrupt)
>>>> - 99:97   3 pins on bank GPIOE
>>>> - 96:77   20 pins on bank GPIOX
>>>> - 76:61   16 pins on bank GPIOA
>>>> - 60:53   8 pins on bank GPIOC
>>>> - 52:37   16 pins on bank BOOT
>>>> - 36:28   9 pins on bank GPIOH
>>>> - 27:12   16 pins on bank GPIOZ
>>>> - 11:0    12 pins in the AO domain
>>>>
>>>> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
>>>> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
>>>> ---
>>>>    drivers/irqchip/irq-meson-gpio.c | 5 +++++
>>>>    1 file changed, 5 insertions(+)
>>>>
>>>> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-
>>>> gpio.c
>>>> index 7b531fd075b8..971e8dea069a 100644
>>>> --- a/drivers/irqchip/irq-meson-gpio.c
>>>> +++ b/drivers/irqchip/irq-meson-gpio.c
>>>> @@ -67,12 +67,17 @@ static const struct meson_gpio_irq_params axg_params = {
>>>>        .nr_hwirq = 100,
>>>>    };
>>>>    +static const struct meson_gpio_irq_params g12a_params = {
>>>> +    .nr_hwirq = 100,
>>>> +};
>>>> +
>>>
>>> Same comment as on i2c, the g12 seems compatible with the axg.
>>> Is this patchset patchset really necessary ?
>>>
>> Although the total number of pins is the same as the Meson-AXG SoC, the gpio banks and irq numbers are different. To avoid confusion on use, i think the new compatible string is needed.
> 
> OK for the new compatible, but you can re-use the same struct like for i2c.
> 
> Neil
> 
Thanks for your comment, I will fix it in the next version.

>>>>    static const struct of_device_id meson_irq_gpio_matches[] = {
>>>>        { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
>>>>        { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params
>>>> },
>>>>        { .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params
>>>> },
>>>>        { .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
>>>>        { .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
>>>> +    { .compatible = "amlogic,meson-g12a-gpio-intc", .data = &g12a_params
>>>> },
>>>>        { }
>>>>    };
>>>>    
>>>
>>>
>>> .
>>>
>>
>> _______________________________________________
>> linux-amlogic mailing list
>> linux-amlogic@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-amlogic
> 
> .
> 

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