* [U-Boot] [PATCH] exynos: allow SPL to build in thumb mode @ 2019-01-02 13:31 ` Guillaume GARDET 2019-01-04 0:30 ` Minkyu Kang 2019-01-04 4:45 ` Siarhei Siamashka 0 siblings, 2 replies; 4+ messages in thread From: Guillaume GARDET @ 2019-01-02 13:31 UTC (permalink / raw) To: u-boot Building peach-pi smdk5420 and peach-pit with thumb mode for SPL ends-up in the following error: Error: Thumb encoding does not support an immediate here -- `msr cpsr_c,#0x13|0xC0' Use an intermediate register to be able to use thumb for exynos5 SPL. Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Tom Rini <trini@konsulko.com> --- arch/arm/mach-exynos/include/mach/system.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h index 4837781957..81fa9800b4 100644 --- a/arch/arm/mach-exynos/include/mach/system.h +++ b/arch/arm/mach-exynos/include/mach/system.h @@ -58,7 +58,8 @@ struct exynos5_sysreg { /* Move 0xd3 value to CPSR register to enable SVC mode */ #define svc32_mode_en() __asm__ __volatile__ \ ("@ I&F disable, Mode: 0x13 - SVC\n\t" \ - "msr cpsr_c, #0x13|0xC0\n\t" : : ) + "mov r0, #0x13|0xC0\n\t" \ + "msr cpsr_c, r0\n\t" : : ) /* Set program counter with the given value */ #define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : "r"(x)) -- 2.20.1 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH] exynos: allow SPL to build in thumb mode 2019-01-02 13:31 ` [U-Boot] [PATCH] exynos: allow SPL to build in thumb mode Guillaume GARDET @ 2019-01-04 0:30 ` Minkyu Kang 2019-01-04 4:45 ` Siarhei Siamashka 1 sibling, 0 replies; 4+ messages in thread From: Minkyu Kang @ 2019-01-04 0:30 UTC (permalink / raw) To: u-boot On 02/01/19 22:31, Guillaume GARDET wrote: > Building peach-pi smdk5420 and peach-pit with thumb mode for SPL > ends-up in the following error: > > Error: Thumb encoding does not support an immediate here -- `msr cpsr_c,#0x13|0xC0' > > Use an intermediate register to be able to use thumb for exynos5 SPL. > > > Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> > > Cc: Albert Aribaud <albert.u.boot@aribaud.net> > Cc: Minkyu Kang <mk7.kang@samsung.com> > Cc: Tom Rini <trini@konsulko.com> > > --- > arch/arm/mach-exynos/include/mach/system.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h > index 4837781957..81fa9800b4 100644 > --- a/arch/arm/mach-exynos/include/mach/system.h > +++ b/arch/arm/mach-exynos/include/mach/system.h > @@ -58,7 +58,8 @@ struct exynos5_sysreg { > /* Move 0xd3 value to CPSR register to enable SVC mode */ > #define svc32_mode_en() __asm__ __volatile__ \ > ("@ I&F disable, Mode: 0x13 - SVC\n\t" \ > - "msr cpsr_c, #0x13|0xC0\n\t" : : ) > + "mov r0, #0x13|0xC0\n\t" \ > + "msr cpsr_c, r0\n\t" : : ) > > /* Set program counter with the given value */ > #define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : "r"(x)) > applied to u-boot-samsung. Thanks, Minkyu Kang. ^ permalink raw reply [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH] exynos: allow SPL to build in thumb mode 2019-01-02 13:31 ` [U-Boot] [PATCH] exynos: allow SPL to build in thumb mode Guillaume GARDET 2019-01-04 0:30 ` Minkyu Kang @ 2019-01-04 4:45 ` Siarhei Siamashka 2019-01-04 8:25 ` [U-Boot] Re : " Guillaume GARDET 1 sibling, 1 reply; 4+ messages in thread From: Siarhei Siamashka @ 2019-01-04 4:45 UTC (permalink / raw) To: u-boot On Wed, 2 Jan 2019 14:31:41 +0100 Guillaume GARDET <guillaume.gardet@free.fr> wrote: > Building peach-pi smdk5420 and peach-pit with thumb mode for SPL > ends-up in the following error: > > Error: Thumb encoding does not support an immediate here -- `msr cpsr_c,#0x13|0xC0' > > Use an intermediate register to be able to use thumb for exynos5 SPL. > > > Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> > > Cc: Albert Aribaud <albert.u.boot@aribaud.net> > Cc: Minkyu Kang <mk7.kang@samsung.com> > Cc: Tom Rini <trini@konsulko.com> > > --- > arch/arm/mach-exynos/include/mach/system.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h > index 4837781957..81fa9800b4 100644 > --- a/arch/arm/mach-exynos/include/mach/system.h > +++ b/arch/arm/mach-exynos/include/mach/system.h > @@ -58,7 +58,8 @@ struct exynos5_sysreg { > /* Move 0xd3 value to CPSR register to enable SVC mode */ > #define svc32_mode_en() __asm__ __volatile__ \ > ("@ I&F disable, Mode: 0x13 - SVC\n\t" \ > - "msr cpsr_c, #0x13|0xC0\n\t" : : ) > + "mov r0, #0x13|0xC0\n\t" \ > + "msr cpsr_c, r0\n\t" : : ) This line needs "r0" to be also added to the clobber list. If you don't do this, then you may encounter sporadic r0 corruption problem depending on the compiler version or optimization settings. This would be: "msr cpsr_c, r0\n\t" : : : "r0") See https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html for more details. An even better option is to just use something like this and give the compiler freedom to pick any register: "msr cpsr_c, %0\n\t" : : "r"(0x13|0xC0)) -- Best regards, Siarhei Siamashka ^ permalink raw reply [flat|nested] 4+ messages in thread
* [U-Boot] Re : Re: [PATCH] exynos: allow SPL to build in thumb mode 2019-01-04 4:45 ` Siarhei Siamashka @ 2019-01-04 8:25 ` Guillaume GARDET 0 siblings, 0 replies; 4+ messages in thread From: Guillaume GARDET @ 2019-01-04 8:25 UTC (permalink / raw) To: u-boot Hi, ----- Siarhei Siamashka <siarhei.siamashka@gmail.com> a écrit : > On Wed, 2 Jan 2019 14:31:41 +0100 > Guillaume GARDET <guillaume.gardet@free.fr> wrote: > > > Building peach-pi smdk5420 and peach-pit with thumb mode for SPL > > ends-up in the following error: > > > > Error: Thumb encoding does not support an immediate here -- `msr cpsr_c,#0x13|0xC0' > > > > Use an intermediate register to be able to use thumb for exynos5 SPL. > > > > > > Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> > > > > Cc: Albert Aribaud <albert.u.boot@aribaud.net> > > Cc: Minkyu Kang <mk7.kang@samsung.com> > > Cc: Tom Rini <trini@konsulko.com> > > > > --- > > arch/arm/mach-exynos/include/mach/system.h | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h > > index 4837781957..81fa9800b4 100644 > > --- a/arch/arm/mach-exynos/include/mach/system.h > > +++ b/arch/arm/mach-exynos/include/mach/system.h > > @@ -58,7 +58,8 @@ struct exynos5_sysreg { > > /* Move 0xd3 value to CPSR register to enable SVC mode */ > > #define svc32_mode_en() __asm__ __volatile__ \ > > ("@ I&F disable, Mode: 0x13 - SVC\n\t" \ > > - "msr cpsr_c, #0x13|0xC0\n\t" : : ) > > + "mov r0, #0x13|0xC0\n\t" \ > > + "msr cpsr_c, r0\n\t" : : ) > > This line needs "r0" to be also added to the clobber list. If you > don't do this, then you may encounter sporadic r0 corruption > problem depending on the compiler version or optimization settings. > > This would be: > > "msr cpsr_c, r0\n\t" : : : "r0") > > See https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html for more > details. > > An even better option is to just use something like this and give > the compiler freedom to pick any register: > > "msr cpsr_c, %0\n\t" : : "r"(0x13|0xC0)) Thanks for the report Siarhei. Minkyu, please merge also this patch: https://lists.denx.de/pipermail/u-boot/2019-January/353533.html Thanks, Guillaume > > -- > Best regards, > Siarhei Siamashka ^ permalink raw reply [flat|nested] 4+ messages in thread
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2019-01-02 13:31 ` [U-Boot] [PATCH] exynos: allow SPL to build in thumb mode Guillaume GARDET
2019-01-04 0:30 ` Minkyu Kang
2019-01-04 4:45 ` Siarhei Siamashka
2019-01-04 8:25 ` [U-Boot] Re : " Guillaume GARDET
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