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From: Shawn Guo <shawnguo@kernel.org>
To: Lucas Stach <l.stach@pengutronix.de>
Cc: devicetree@vger.kernel.org, patchwork-lst@pengutronix.de,
	Rob Herring <robh+dt@kernel.org>,
	NXP Linux Team <linux-imx@nxp.com>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Fabio Estevam <fabio.estevam@nxp.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/2] soc: imx: gpcv2: handle additional power-down bits in handshake register
Date: Fri, 11 Jan 2019 15:13:42 +0800	[thread overview]
Message-ID: <20190111071341.GB32649@dragon> (raw)
In-Reply-To: <20181217153152.21135-1-l.stach@pengutronix.de>

On Mon, Dec 17, 2018 at 04:31:51PM +0100, Lucas Stach wrote:
> Some of the i.MX8MQ domains have an additional control bit in the PU
> handshake (HSK) register. Documentation about this bit is a bit sparse
> at the moment, but it seems that it controls a power-down request to
> the AMBA domain bridge (ADB-400) attached to those domains.
> 
> As the documentation doesn't desribe the usage of this bit yet, handle
> it in the same way as done in the ATF implementation.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Applied both, thanks.

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WARNING: multiple messages have this Message-ID (diff)
From: Shawn Guo <shawnguo@kernel.org>
To: Lucas Stach <l.stach@pengutronix.de>
Cc: devicetree@vger.kernel.org, patchwork-lst@pengutronix.de,
	Rob Herring <robh+dt@kernel.org>,
	NXP Linux Team <linux-imx@nxp.com>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Fabio Estevam <fabio.estevam@nxp.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/2] soc: imx: gpcv2: handle additional power-down bits in handshake register
Date: Fri, 11 Jan 2019 15:13:42 +0800	[thread overview]
Message-ID: <20190111071341.GB32649@dragon> (raw)
In-Reply-To: <20181217153152.21135-1-l.stach@pengutronix.de>

On Mon, Dec 17, 2018 at 04:31:51PM +0100, Lucas Stach wrote:
> Some of the i.MX8MQ domains have an additional control bit in the PU
> handshake (HSK) register. Documentation about this bit is a bit sparse
> at the moment, but it seems that it controls a power-down request to
> the AMBA domain bridge (ADB-400) attached to those domains.
> 
> As the documentation doesn't desribe the usage of this bit yet, handle
> it in the same way as done in the ATF implementation.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Applied both, thanks.

  parent reply	other threads:[~2019-01-11  7:14 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-17 15:31 [PATCH 1/2] soc: imx: gpcv2: handle additional power-down bits in handshake register Lucas Stach
2018-12-17 15:31 ` Lucas Stach
2018-12-17 15:31 ` [PATCH 2/2] soc: imx: gpcv2: handle reset clocks Lucas Stach
2018-12-17 15:31   ` Lucas Stach
2018-12-20 21:43   ` Rob Herring
2018-12-20 21:43     ` Rob Herring
2019-01-11  7:13 ` Shawn Guo [this message]
2019-01-11  7:13   ` [PATCH 1/2] soc: imx: gpcv2: handle additional power-down bits in handshake register Shawn Guo

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