From: Rob Herring <robh@kernel.org>
Cc: robh+dt@kernel.org, mark.rutland@arm.com, mperttunen@nvidia.com,
thierry.reding@gmail.com, jonathanh@nvidia.com,
adrian.hunter@intel.com, ulf.hansson@linaro.org,
devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org,
Sowjanya Komatineni <skomatineni@nvidia.com>
Subject: Re: [PATCH V3 1/3] dt-bindings: mmc: tegra: Add pinctrl for pad drive strength config
Date: Fri, 11 Jan 2019 10:11:20 -0600 [thread overview]
Message-ID: <20190111161120.GA6491@bogus> (raw)
In-Reply-To: <1546462674-22856-1-git-send-email-skomatineni@nvidia.com>
On Wed, 2 Jan 2019 12:57:52 -0800, Sowjanya Komatineni wrote:
> Add pinctrl for 3V3 and 1V8 pad drive strength configuration for
> Tegra210 sdmmc which has pad configuration registers in the pinmux
> reigster domain.
> Pad drive strengths for Tegra186 and Later are
> part of SDMMC device node itself.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Sowjanya Komatineni <skomatineni@nvidia.com>
Cc: robh+dt@kernel.org, mark.rutland@arm.com, mperttunen@nvidia.com,
thierry.reding@gmail.com, jonathanh@nvidia.com,
adrian.hunter@intel.com, ulf.hansson@linaro.org,
devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org,
Sowjanya Komatineni <skomatineni@nvidia.com>
Subject: Re: [PATCH V3 1/3] dt-bindings: mmc: tegra: Add pinctrl for pad drive strength config
Date: Fri, 11 Jan 2019 10:11:20 -0600 [thread overview]
Message-ID: <20190111161120.GA6491@bogus> (raw)
In-Reply-To: <1546462674-22856-1-git-send-email-skomatineni@nvidia.com>
On Wed, 2 Jan 2019 12:57:52 -0800, Sowjanya Komatineni wrote:
> Add pinctrl for 3V3 and 1V8 pad drive strength configuration for
> Tegra210 sdmmc which has pad configuration registers in the pinmux
> reigster domain.
> Pad drive strengths for Tegra186 and Later are
> part of SDMMC device node itself.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
next prev parent reply other threads:[~2019-01-11 16:11 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-02 20:57 [PATCH V3 1/3] dt-bindings: mmc: tegra: Add pinctrl for pad drive strength config Sowjanya Komatineni
2019-01-02 20:57 ` Sowjanya Komatineni
2019-01-02 20:57 ` [PATCH V3 2/3] arm64: dts: tegra: Add SDMMC Auto-cal settings Sowjanya Komatineni
2019-01-02 20:57 ` Sowjanya Komatineni
2019-01-02 20:57 ` [PATCH V3 3/3] mmc: tegra: SDMMC pads auto-calibration Sowjanya Komatineni
2019-01-02 20:57 ` Sowjanya Komatineni
2019-01-10 15:06 ` Thierry Reding
2019-01-10 19:19 ` Sowjanya Komatineni
2019-01-10 19:19 ` Sowjanya Komatineni
2019-01-10 14:48 ` [PATCH V3 1/3] dt-bindings: mmc: tegra: Add pinctrl for pad drive strength config Thierry Reding
2019-01-11 16:11 ` Rob Herring [this message]
2019-01-11 16:11 ` Rob Herring
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