* [PATCH v2 0/4] soc: amlogic: clk-measure: add axg and g12a support @ 2019-01-18 10:34 ` Jerome Brunet 0 siblings, 0 replies; 25+ messages in thread From: Jerome Brunet @ 2019-01-18 10:34 UTC (permalink / raw) To: Kevin Hilman Cc: linux-amlogic, devicetree, patchwork-bot+notify, linux-kernel, Jerome Brunet This patchset adds support for the axg and g12a SoC family in amlogic's clock measure driver and enable it on the related devices Changes since v1 [0]: * re-order node in the g12a.dtsi * change node name [0]: https://lkml.kernel.org/r/20190117164838.8008-1-jbrunet@baylibre.com Jerome Brunet (4): dt-bindings: amlogic: add new compatible devices to clk_measure soc: amlogic: clk-measure: add axg and g12a support arm64: dts: meson: axg: add clk measure support arm64: dts: meson: g12a: add clk measure support .../bindings/soc/amlogic/clk-measure.txt | 2 + arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 5 + arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 5 + drivers/soc/amlogic/meson-clk-measure.c | 194 ++++++++++++++++++ 4 files changed, 206 insertions(+) -- 2.20.1 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 0/4] soc: amlogic: clk-measure: add axg and g12a support @ 2019-01-18 10:34 ` Jerome Brunet 0 siblings, 0 replies; 25+ messages in thread From: Jerome Brunet @ 2019-01-18 10:34 UTC (permalink / raw) To: Kevin Hilman Cc: Jerome Brunet, linux-amlogic, devicetree, linux-kernel, patchwork-bot+notify This patchset adds support for the axg and g12a SoC family in amlogic's clock measure driver and enable it on the related devices Changes since v1 [0]: * re-order node in the g12a.dtsi * change node name [0]: https://lkml.kernel.org/r/20190117164838.8008-1-jbrunet@baylibre.com Jerome Brunet (4): dt-bindings: amlogic: add new compatible devices to clk_measure soc: amlogic: clk-measure: add axg and g12a support arm64: dts: meson: axg: add clk measure support arm64: dts: meson: g12a: add clk measure support .../bindings/soc/amlogic/clk-measure.txt | 2 + arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 5 + arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 5 + drivers/soc/amlogic/meson-clk-measure.c | 194 ++++++++++++++++++ 4 files changed, 206 insertions(+) -- 2.20.1 ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 1/4] dt-bindings: amlogic: add new compatible devices to clk_measure 2019-01-18 10:34 ` Jerome Brunet @ 2019-01-18 10:34 ` Jerome Brunet -1 siblings, 0 replies; 25+ messages in thread From: Jerome Brunet @ 2019-01-18 10:34 UTC (permalink / raw) To: Kevin Hilman Cc: linux-amlogic, devicetree, patchwork-bot+notify, linux-kernel, Jerome Brunet Add the axg and g12a SoC family compatible to the clock measure bindings Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> --- Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt b/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt index 205a54bcd7c7..6bf6b43f8dd8 100644 --- a/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt +++ b/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt @@ -9,6 +9,8 @@ Required properties: "amlogic,meson-gx-clk-measure" for GX SoCs "amlogic,meson8-clk-measure" for Meson8 SoCs "amlogic,meson8b-clk-measure" for Meson8b SoCs + "amlogic,meson-axg-clk-measure" for AXG SoCs + "amlogic,meson-g12a-clk-measure" for G12a SoCs - reg: base address and size of the Clock Measurer register space. Example: -- 2.20.1 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 1/4] dt-bindings: amlogic: add new compatible devices to clk_measure @ 2019-01-18 10:34 ` Jerome Brunet 0 siblings, 0 replies; 25+ messages in thread From: Jerome Brunet @ 2019-01-18 10:34 UTC (permalink / raw) To: Kevin Hilman Cc: Jerome Brunet, linux-amlogic, devicetree, linux-kernel, patchwork-bot+notify Add the axg and g12a SoC family compatible to the clock measure bindings Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> --- Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt b/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt index 205a54bcd7c7..6bf6b43f8dd8 100644 --- a/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt +++ b/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt @@ -9,6 +9,8 @@ Required properties: "amlogic,meson-gx-clk-measure" for GX SoCs "amlogic,meson8-clk-measure" for Meson8 SoCs "amlogic,meson8b-clk-measure" for Meson8b SoCs + "amlogic,meson-axg-clk-measure" for AXG SoCs + "amlogic,meson-g12a-clk-measure" for G12a SoCs - reg: base address and size of the Clock Measurer register space. Example: -- 2.20.1 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v2 1/4] dt-bindings: amlogic: add new compatible devices to clk_measure 2019-01-18 10:34 ` Jerome Brunet @ 2019-01-18 21:56 ` Martin Blumenstingl -1 siblings, 0 replies; 25+ messages in thread From: Martin Blumenstingl @ 2019-01-18 21:56 UTC (permalink / raw) To: Jerome Brunet Cc: Kevin Hilman, devicetree, patchwork-bot+notify, linux-kernel, linux-amlogic On Fri, Jan 18, 2019 at 11:34 AM Jerome Brunet <jbrunet@baylibre.com> wrote: > > Add the axg and g12a SoC family compatible to the clock measure bindings > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> this is certainly going to make it easier to fix potential issues with the clock controller drivers! Regards Martin _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 1/4] dt-bindings: amlogic: add new compatible devices to clk_measure @ 2019-01-18 21:56 ` Martin Blumenstingl 0 siblings, 0 replies; 25+ messages in thread From: Martin Blumenstingl @ 2019-01-18 21:56 UTC (permalink / raw) To: Jerome Brunet Cc: Kevin Hilman, linux-amlogic, devicetree, patchwork-bot+notify, linux-kernel On Fri, Jan 18, 2019 at 11:34 AM Jerome Brunet <jbrunet@baylibre.com> wrote: > > Add the axg and g12a SoC family compatible to the clock measure bindings > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> this is certainly going to make it easier to fix potential issues with the clock controller drivers! Regards Martin ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 1/4] dt-bindings: amlogic: add new compatible devices to clk_measure 2019-01-18 10:34 ` Jerome Brunet (?) @ 2019-01-21 17:11 ` Rob Herring -1 siblings, 0 replies; 25+ messages in thread From: Rob Herring @ 2019-01-21 17:11 UTC (permalink / raw) To: Jerome Brunet Cc: devicetree, Kevin Hilman, linux-kernel, patchwork-bot+notify, linux-amlogic, Jerome Brunet On Fri, 18 Jan 2019 11:34:20 +0100, Jerome Brunet wrote: > Add the axg and g12a SoC family compatible to the clock measure bindings > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> > --- > Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt | 2 ++ > 1 file changed, 2 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org> _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 1/4] dt-bindings: amlogic: add new compatible devices to clk_measure @ 2019-01-21 17:11 ` Rob Herring 0 siblings, 0 replies; 25+ messages in thread From: Rob Herring @ 2019-01-21 17:11 UTC (permalink / raw) To: Jerome Brunet Cc: Kevin Hilman, Jerome Brunet, linux-amlogic, devicetree, linux-kernel, patchwork-bot+notify On Fri, 18 Jan 2019 11:34:20 +0100, Jerome Brunet wrote: > Add the axg and g12a SoC family compatible to the clock measure bindings > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> > --- > Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt | 2 ++ > 1 file changed, 2 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 1/4] dt-bindings: amlogic: add new compatible devices to clk_measure @ 2019-01-21 17:11 ` Rob Herring 0 siblings, 0 replies; 25+ messages in thread From: Rob Herring @ 2019-01-21 17:11 UTC (permalink / raw) Cc: Kevin Hilman, Jerome Brunet, linux-amlogic, devicetree, linux-kernel, patchwork-bot+notify On Fri, 18 Jan 2019 11:34:20 +0100, Jerome Brunet wrote: > Add the axg and g12a SoC family compatible to the clock measure bindings > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> > --- > Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt | 2 ++ > 1 file changed, 2 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 2/4] soc: amlogic: clk-measure: add axg and g12a support 2019-01-18 10:34 ` Jerome Brunet @ 2019-01-18 10:34 ` Jerome Brunet -1 siblings, 0 replies; 25+ messages in thread From: Jerome Brunet @ 2019-01-18 10:34 UTC (permalink / raw) To: Kevin Hilman Cc: linux-amlogic, devicetree, patchwork-bot+notify, linux-kernel, Jerome Brunet Add support for the axg and g12a SoC family in amlogic clk measure Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> --- drivers/soc/amlogic/meson-clk-measure.c | 194 ++++++++++++++++++++++++ 1 file changed, 194 insertions(+) diff --git a/drivers/soc/amlogic/meson-clk-measure.c b/drivers/soc/amlogic/meson-clk-measure.c index daea191a66fa..5570180b94a1 100644 --- a/drivers/soc/amlogic/meson-clk-measure.c +++ b/drivers/soc/amlogic/meson-clk-measure.c @@ -165,6 +165,192 @@ static struct meson_msr_id clk_msr_gx[CLK_MSR_MAX] = { CLK_MSR_ID(82, "ge2d"), }; +static struct meson_msr_id clk_msr_axg[CLK_MSR_MAX] = { + CLK_MSR_ID(0, "ring_osc_out_ee_0"), + CLK_MSR_ID(1, "ring_osc_out_ee_1"), + CLK_MSR_ID(2, "ring_osc_out_ee_2"), + CLK_MSR_ID(3, "a53_ring_osc"), + CLK_MSR_ID(4, "gp0_pll"), + CLK_MSR_ID(5, "gp1_pll"), + CLK_MSR_ID(7, "clk81"), + CLK_MSR_ID(9, "encl"), + CLK_MSR_ID(17, "sys_pll_div16"), + CLK_MSR_ID(18, "sys_cpu_div16"), + CLK_MSR_ID(20, "rtc_osc_out"), + CLK_MSR_ID(23, "mmc_clk"), + CLK_MSR_ID(28, "sar_adc"), + CLK_MSR_ID(31, "mpll_test_out"), + CLK_MSR_ID(40, "mod_eth_tx_clk"), + CLK_MSR_ID(41, "mod_eth_rx_clk_rmii"), + CLK_MSR_ID(42, "mp0_out"), + CLK_MSR_ID(43, "fclk_div5"), + CLK_MSR_ID(44, "pwm_b"), + CLK_MSR_ID(45, "pwm_a"), + CLK_MSR_ID(46, "vpu"), + CLK_MSR_ID(47, "ddr_dpll_pt"), + CLK_MSR_ID(48, "mp1_out"), + CLK_MSR_ID(49, "mp2_out"), + CLK_MSR_ID(50, "mp3_out"), + CLK_MSR_ID(51, "sd_emmm_c"), + CLK_MSR_ID(52, "sd_emmc_b"), + CLK_MSR_ID(61, "gpio_msr"), + CLK_MSR_ID(66, "audio_slv_lrclk_c"), + CLK_MSR_ID(67, "audio_slv_lrclk_b"), + CLK_MSR_ID(68, "audio_slv_lrclk_a"), + CLK_MSR_ID(69, "audio_slv_sclk_c"), + CLK_MSR_ID(70, "audio_slv_sclk_b"), + CLK_MSR_ID(71, "audio_slv_sclk_a"), + CLK_MSR_ID(72, "pwm_d"), + CLK_MSR_ID(73, "pwm_c"), + CLK_MSR_ID(73, "wifi_beacon"), + CLK_MSR_ID(75, "tdmin_lb_lrcl"), + CLK_MSR_ID(76, "tdmin_lb_sclk"), + CLK_MSR_ID(77, "rng_ring_osc_0"), + CLK_MSR_ID(78, "rng_ring_osc_1"), + CLK_MSR_ID(79, "rng_ring_osc_2"), + CLK_MSR_ID(80, "rng_ring_osc_3"), + CLK_MSR_ID(81, "vapb"), + CLK_MSR_ID(82, "ge2d"), + CLK_MSR_ID(84, "audio_resample"), + CLK_MSR_ID(85, "audio_pdm_sys"), + CLK_MSR_ID(86, "audio_spdifout"), + CLK_MSR_ID(87, "audio_spdifin"), + CLK_MSR_ID(88, "audio_lrclk_f"), + CLK_MSR_ID(89, "audio_lrclk_e"), + CLK_MSR_ID(90, "audio_lrclk_d"), + CLK_MSR_ID(91, "audio_lrclk_c"), + CLK_MSR_ID(92, "audio_lrclk_b"), + CLK_MSR_ID(93, "audio_lrclk_a"), + CLK_MSR_ID(94, "audio_sclk_f"), + CLK_MSR_ID(95, "audio_sclk_e"), + CLK_MSR_ID(96, "audio_sclk_d"), + CLK_MSR_ID(97, "audio_sclk_c"), + CLK_MSR_ID(98, "audio_sclk_b"), + CLK_MSR_ID(99, "audio_sclk_a"), + CLK_MSR_ID(100, "audio_mclk_f"), + CLK_MSR_ID(101, "audio_mclk_e"), + CLK_MSR_ID(102, "audio_mclk_d"), + CLK_MSR_ID(103, "audio_mclk_c"), + CLK_MSR_ID(104, "audio_mclk_b"), + CLK_MSR_ID(105, "audio_mclk_a"), + CLK_MSR_ID(106, "pcie_refclk_n"), + CLK_MSR_ID(107, "pcie_refclk_p"), + CLK_MSR_ID(108, "audio_locker_out"), + CLK_MSR_ID(109, "audio_locker_in"), +}; + +static struct meson_msr_id clk_msr_g12a[CLK_MSR_MAX] = { + CLK_MSR_ID(0, "ring_osc_out_ee_0"), + CLK_MSR_ID(1, "ring_osc_out_ee_1"), + CLK_MSR_ID(2, "ring_osc_out_ee_2"), + CLK_MSR_ID(3, "sys_cpu_ring_osc"), + CLK_MSR_ID(4, "gp0_pll"), + CLK_MSR_ID(6, "enci"), + CLK_MSR_ID(7, "clk81"), + CLK_MSR_ID(8, "encp"), + CLK_MSR_ID(9, "encl"), + CLK_MSR_ID(10, "vdac"), + CLK_MSR_ID(11, "eth_tx"), + CLK_MSR_ID(12, "hifi_pll"), + CLK_MSR_ID(13, "mod_tcon"), + CLK_MSR_ID(14, "fec_0"), + CLK_MSR_ID(15, "fec_1"), + CLK_MSR_ID(16, "fec_2"), + CLK_MSR_ID(17, "sys_pll_div16"), + CLK_MSR_ID(18, "sys_cpu_div16"), + CLK_MSR_ID(19, "lcd_an_ph2"), + CLK_MSR_ID(20, "rtc_osc_out"), + CLK_MSR_ID(21, "lcd_an_ph3"), + CLK_MSR_ID(22, "eth_phy_ref"), + CLK_MSR_ID(23, "mpll_50m"), + CLK_MSR_ID(24, "eth_125m"), + CLK_MSR_ID(25, "eth_rmii"), + CLK_MSR_ID(26, "sc_int"), + CLK_MSR_ID(27, "in_mac"), + CLK_MSR_ID(28, "sar_adc"), + CLK_MSR_ID(31, "mpll_test_out"), + CLK_MSR_ID(32, "vdec"), + CLK_MSR_ID(33, "sys_cpu_ring_osc_1"), + CLK_MSR_ID(34, "eth_mpll_50m"), + CLK_MSR_ID(35, "mali"), + CLK_MSR_ID(36, "hdmi_tx_pixel"), + CLK_MSR_ID(37, "cdac"), + CLK_MSR_ID(38, "vdin_meas"), + CLK_MSR_ID(39, "bt656"), + CLK_MSR_ID(41, "eth_rx_or_rmii"), + CLK_MSR_ID(42, "mp0_out"), + CLK_MSR_ID(43, "fclk_div5"), + CLK_MSR_ID(44, "pwm_b"), + CLK_MSR_ID(45, "pwm_a"), + CLK_MSR_ID(46, "vpu"), + CLK_MSR_ID(47, "ddr_dpll_pt"), + CLK_MSR_ID(48, "mp1_out"), + CLK_MSR_ID(49, "mp2_out"), + CLK_MSR_ID(50, "mp3_out"), + CLK_MSR_ID(51, "sd_emmc_c"), + CLK_MSR_ID(52, "sd_emmc_b"), + CLK_MSR_ID(53, "sd_emmc_a"), + CLK_MSR_ID(54, "vpu_clkc"), + CLK_MSR_ID(55, "vid_pll_div_out"), + CLK_MSR_ID(56, "wave420l_a"), + CLK_MSR_ID(57, "wave420l_c"), + CLK_MSR_ID(58, "wave420l_b"), + CLK_MSR_ID(59, "hcodec"), + CLK_MSR_ID(61, "gpio_msr"), + CLK_MSR_ID(62, "hevcb"), + CLK_MSR_ID(63, "dsi_meas"), + CLK_MSR_ID(64, "spicc_1"), + CLK_MSR_ID(65, "spicc_0"), + CLK_MSR_ID(66, "vid_lock"), + CLK_MSR_ID(67, "dsi_phy"), + CLK_MSR_ID(68, "hdcp22_skp"), + CLK_MSR_ID(69, "hdcp22_esm"), + CLK_MSR_ID(70, "pwm_f"), + CLK_MSR_ID(71, "pwm_e"), + CLK_MSR_ID(72, "pwm_d"), + CLK_MSR_ID(73, "pwm_c"), + CLK_MSR_ID(75, "hevcf"), + CLK_MSR_ID(77, "rng_ring_osc_0"), + CLK_MSR_ID(78, "rng_ring_osc_1"), + CLK_MSR_ID(79, "rng_ring_osc_2"), + CLK_MSR_ID(80, "rng_ring_osc_3"), + CLK_MSR_ID(81, "vapb"), + CLK_MSR_ID(82, "ge2d"), + CLK_MSR_ID(83, "co_rx"), + CLK_MSR_ID(84, "co_tx"), + CLK_MSR_ID(89, "hdmi_todig"), + CLK_MSR_ID(90, "hdmitx_sys"), + CLK_MSR_ID(94, "eth_phy_rx"), + CLK_MSR_ID(95, "eth_phy_pll"), + CLK_MSR_ID(96, "vpu_b"), + CLK_MSR_ID(97, "cpu_b_tmp"), + CLK_MSR_ID(98, "ts"), + CLK_MSR_ID(99, "ring_osc_out_ee_3"), + CLK_MSR_ID(100, "ring_osc_out_ee_4"), + CLK_MSR_ID(101, "ring_osc_out_ee_5"), + CLK_MSR_ID(102, "ring_osc_out_ee_6"), + CLK_MSR_ID(103, "ring_osc_out_ee_7"), + CLK_MSR_ID(104, "ring_osc_out_ee_8"), + CLK_MSR_ID(105, "ring_osc_out_ee_9"), + CLK_MSR_ID(106, "ephy_test"), + CLK_MSR_ID(107, "au_dac_g128x"), + CLK_MSR_ID(108, "audio_locker_out"), + CLK_MSR_ID(109, "audio_locker_in"), + CLK_MSR_ID(110, "audio_tdmout_c_sclk"), + CLK_MSR_ID(111, "audio_tdmout_b_sclk"), + CLK_MSR_ID(112, "audio_tdmout_a_sclk"), + CLK_MSR_ID(113, "audio_tdmin_lb_sclk"), + CLK_MSR_ID(114, "audio_tdmin_c_sclk"), + CLK_MSR_ID(115, "audio_tdmin_b_sclk"), + CLK_MSR_ID(116, "audio_tdmin_a_sclk"), + CLK_MSR_ID(117, "audio_resample"), + CLK_MSR_ID(118, "audio_pdm_sys"), + CLK_MSR_ID(119, "audio_spdifout_b"), + CLK_MSR_ID(120, "audio_spdifout"), + CLK_MSR_ID(121, "audio_spdifin"), + CLK_MSR_ID(122, "audio_pdm_dclk"), +}; + static int meson_measure_id(struct meson_msr_id *clk_msr_id, unsigned int duration) { @@ -337,6 +523,14 @@ static const struct of_device_id meson_msr_match_table[] = { .compatible = "amlogic,meson8b-clk-measure", .data = (void *)clk_msr_m8, }, + { + .compatible = "amlogic,meson-axg-clk-measure", + .data = (void *)clk_msr_axg, + }, + { + .compatible = "amlogic,meson-g12a-clk-measure", + .data = (void *)clk_msr_g12a, + }, { /* sentinel */ } }; -- 2.20.1 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 2/4] soc: amlogic: clk-measure: add axg and g12a support @ 2019-01-18 10:34 ` Jerome Brunet 0 siblings, 0 replies; 25+ messages in thread From: Jerome Brunet @ 2019-01-18 10:34 UTC (permalink / raw) To: Kevin Hilman Cc: Jerome Brunet, linux-amlogic, devicetree, linux-kernel, patchwork-bot+notify Add support for the axg and g12a SoC family in amlogic clk measure Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> --- drivers/soc/amlogic/meson-clk-measure.c | 194 ++++++++++++++++++++++++ 1 file changed, 194 insertions(+) diff --git a/drivers/soc/amlogic/meson-clk-measure.c b/drivers/soc/amlogic/meson-clk-measure.c index daea191a66fa..5570180b94a1 100644 --- a/drivers/soc/amlogic/meson-clk-measure.c +++ b/drivers/soc/amlogic/meson-clk-measure.c @@ -165,6 +165,192 @@ static struct meson_msr_id clk_msr_gx[CLK_MSR_MAX] = { CLK_MSR_ID(82, "ge2d"), }; +static struct meson_msr_id clk_msr_axg[CLK_MSR_MAX] = { + CLK_MSR_ID(0, "ring_osc_out_ee_0"), + CLK_MSR_ID(1, "ring_osc_out_ee_1"), + CLK_MSR_ID(2, "ring_osc_out_ee_2"), + CLK_MSR_ID(3, "a53_ring_osc"), + CLK_MSR_ID(4, "gp0_pll"), + CLK_MSR_ID(5, "gp1_pll"), + CLK_MSR_ID(7, "clk81"), + CLK_MSR_ID(9, "encl"), + CLK_MSR_ID(17, "sys_pll_div16"), + CLK_MSR_ID(18, "sys_cpu_div16"), + CLK_MSR_ID(20, "rtc_osc_out"), + CLK_MSR_ID(23, "mmc_clk"), + CLK_MSR_ID(28, "sar_adc"), + CLK_MSR_ID(31, "mpll_test_out"), + CLK_MSR_ID(40, "mod_eth_tx_clk"), + CLK_MSR_ID(41, "mod_eth_rx_clk_rmii"), + CLK_MSR_ID(42, "mp0_out"), + CLK_MSR_ID(43, "fclk_div5"), + CLK_MSR_ID(44, "pwm_b"), + CLK_MSR_ID(45, "pwm_a"), + CLK_MSR_ID(46, "vpu"), + CLK_MSR_ID(47, "ddr_dpll_pt"), + CLK_MSR_ID(48, "mp1_out"), + CLK_MSR_ID(49, "mp2_out"), + CLK_MSR_ID(50, "mp3_out"), + CLK_MSR_ID(51, "sd_emmm_c"), + CLK_MSR_ID(52, "sd_emmc_b"), + CLK_MSR_ID(61, "gpio_msr"), + CLK_MSR_ID(66, "audio_slv_lrclk_c"), + CLK_MSR_ID(67, "audio_slv_lrclk_b"), + CLK_MSR_ID(68, "audio_slv_lrclk_a"), + CLK_MSR_ID(69, "audio_slv_sclk_c"), + CLK_MSR_ID(70, "audio_slv_sclk_b"), + CLK_MSR_ID(71, "audio_slv_sclk_a"), + CLK_MSR_ID(72, "pwm_d"), + CLK_MSR_ID(73, "pwm_c"), + CLK_MSR_ID(73, "wifi_beacon"), + CLK_MSR_ID(75, "tdmin_lb_lrcl"), + CLK_MSR_ID(76, "tdmin_lb_sclk"), + CLK_MSR_ID(77, "rng_ring_osc_0"), + CLK_MSR_ID(78, "rng_ring_osc_1"), + CLK_MSR_ID(79, "rng_ring_osc_2"), + CLK_MSR_ID(80, "rng_ring_osc_3"), + CLK_MSR_ID(81, "vapb"), + CLK_MSR_ID(82, "ge2d"), + CLK_MSR_ID(84, "audio_resample"), + CLK_MSR_ID(85, "audio_pdm_sys"), + CLK_MSR_ID(86, "audio_spdifout"), + CLK_MSR_ID(87, "audio_spdifin"), + CLK_MSR_ID(88, "audio_lrclk_f"), + CLK_MSR_ID(89, "audio_lrclk_e"), + CLK_MSR_ID(90, "audio_lrclk_d"), + CLK_MSR_ID(91, "audio_lrclk_c"), + CLK_MSR_ID(92, "audio_lrclk_b"), + CLK_MSR_ID(93, "audio_lrclk_a"), + CLK_MSR_ID(94, "audio_sclk_f"), + CLK_MSR_ID(95, "audio_sclk_e"), + CLK_MSR_ID(96, "audio_sclk_d"), + CLK_MSR_ID(97, "audio_sclk_c"), + CLK_MSR_ID(98, "audio_sclk_b"), + CLK_MSR_ID(99, "audio_sclk_a"), + CLK_MSR_ID(100, "audio_mclk_f"), + CLK_MSR_ID(101, "audio_mclk_e"), + CLK_MSR_ID(102, "audio_mclk_d"), + CLK_MSR_ID(103, "audio_mclk_c"), + CLK_MSR_ID(104, "audio_mclk_b"), + CLK_MSR_ID(105, "audio_mclk_a"), + CLK_MSR_ID(106, "pcie_refclk_n"), + CLK_MSR_ID(107, "pcie_refclk_p"), + CLK_MSR_ID(108, "audio_locker_out"), + CLK_MSR_ID(109, "audio_locker_in"), +}; + +static struct meson_msr_id clk_msr_g12a[CLK_MSR_MAX] = { + CLK_MSR_ID(0, "ring_osc_out_ee_0"), + CLK_MSR_ID(1, "ring_osc_out_ee_1"), + CLK_MSR_ID(2, "ring_osc_out_ee_2"), + CLK_MSR_ID(3, "sys_cpu_ring_osc"), + CLK_MSR_ID(4, "gp0_pll"), + CLK_MSR_ID(6, "enci"), + CLK_MSR_ID(7, "clk81"), + CLK_MSR_ID(8, "encp"), + CLK_MSR_ID(9, "encl"), + CLK_MSR_ID(10, "vdac"), + CLK_MSR_ID(11, "eth_tx"), + CLK_MSR_ID(12, "hifi_pll"), + CLK_MSR_ID(13, "mod_tcon"), + CLK_MSR_ID(14, "fec_0"), + CLK_MSR_ID(15, "fec_1"), + CLK_MSR_ID(16, "fec_2"), + CLK_MSR_ID(17, "sys_pll_div16"), + CLK_MSR_ID(18, "sys_cpu_div16"), + CLK_MSR_ID(19, "lcd_an_ph2"), + CLK_MSR_ID(20, "rtc_osc_out"), + CLK_MSR_ID(21, "lcd_an_ph3"), + CLK_MSR_ID(22, "eth_phy_ref"), + CLK_MSR_ID(23, "mpll_50m"), + CLK_MSR_ID(24, "eth_125m"), + CLK_MSR_ID(25, "eth_rmii"), + CLK_MSR_ID(26, "sc_int"), + CLK_MSR_ID(27, "in_mac"), + CLK_MSR_ID(28, "sar_adc"), + CLK_MSR_ID(31, "mpll_test_out"), + CLK_MSR_ID(32, "vdec"), + CLK_MSR_ID(33, "sys_cpu_ring_osc_1"), + CLK_MSR_ID(34, "eth_mpll_50m"), + CLK_MSR_ID(35, "mali"), + CLK_MSR_ID(36, "hdmi_tx_pixel"), + CLK_MSR_ID(37, "cdac"), + CLK_MSR_ID(38, "vdin_meas"), + CLK_MSR_ID(39, "bt656"), + CLK_MSR_ID(41, "eth_rx_or_rmii"), + CLK_MSR_ID(42, "mp0_out"), + CLK_MSR_ID(43, "fclk_div5"), + CLK_MSR_ID(44, "pwm_b"), + CLK_MSR_ID(45, "pwm_a"), + CLK_MSR_ID(46, "vpu"), + CLK_MSR_ID(47, "ddr_dpll_pt"), + CLK_MSR_ID(48, "mp1_out"), + CLK_MSR_ID(49, "mp2_out"), + CLK_MSR_ID(50, "mp3_out"), + CLK_MSR_ID(51, "sd_emmc_c"), + CLK_MSR_ID(52, "sd_emmc_b"), + CLK_MSR_ID(53, "sd_emmc_a"), + CLK_MSR_ID(54, "vpu_clkc"), + CLK_MSR_ID(55, "vid_pll_div_out"), + CLK_MSR_ID(56, "wave420l_a"), + CLK_MSR_ID(57, "wave420l_c"), + CLK_MSR_ID(58, "wave420l_b"), + CLK_MSR_ID(59, "hcodec"), + CLK_MSR_ID(61, "gpio_msr"), + CLK_MSR_ID(62, "hevcb"), + CLK_MSR_ID(63, "dsi_meas"), + CLK_MSR_ID(64, "spicc_1"), + CLK_MSR_ID(65, "spicc_0"), + CLK_MSR_ID(66, "vid_lock"), + CLK_MSR_ID(67, "dsi_phy"), + CLK_MSR_ID(68, "hdcp22_skp"), + CLK_MSR_ID(69, "hdcp22_esm"), + CLK_MSR_ID(70, "pwm_f"), + CLK_MSR_ID(71, "pwm_e"), + CLK_MSR_ID(72, "pwm_d"), + CLK_MSR_ID(73, "pwm_c"), + CLK_MSR_ID(75, "hevcf"), + CLK_MSR_ID(77, "rng_ring_osc_0"), + CLK_MSR_ID(78, "rng_ring_osc_1"), + CLK_MSR_ID(79, "rng_ring_osc_2"), + CLK_MSR_ID(80, "rng_ring_osc_3"), + CLK_MSR_ID(81, "vapb"), + CLK_MSR_ID(82, "ge2d"), + CLK_MSR_ID(83, "co_rx"), + CLK_MSR_ID(84, "co_tx"), + CLK_MSR_ID(89, "hdmi_todig"), + CLK_MSR_ID(90, "hdmitx_sys"), + CLK_MSR_ID(94, "eth_phy_rx"), + CLK_MSR_ID(95, "eth_phy_pll"), + CLK_MSR_ID(96, "vpu_b"), + CLK_MSR_ID(97, "cpu_b_tmp"), + CLK_MSR_ID(98, "ts"), + CLK_MSR_ID(99, "ring_osc_out_ee_3"), + CLK_MSR_ID(100, "ring_osc_out_ee_4"), + CLK_MSR_ID(101, "ring_osc_out_ee_5"), + CLK_MSR_ID(102, "ring_osc_out_ee_6"), + CLK_MSR_ID(103, "ring_osc_out_ee_7"), + CLK_MSR_ID(104, "ring_osc_out_ee_8"), + CLK_MSR_ID(105, "ring_osc_out_ee_9"), + CLK_MSR_ID(106, "ephy_test"), + CLK_MSR_ID(107, "au_dac_g128x"), + CLK_MSR_ID(108, "audio_locker_out"), + CLK_MSR_ID(109, "audio_locker_in"), + CLK_MSR_ID(110, "audio_tdmout_c_sclk"), + CLK_MSR_ID(111, "audio_tdmout_b_sclk"), + CLK_MSR_ID(112, "audio_tdmout_a_sclk"), + CLK_MSR_ID(113, "audio_tdmin_lb_sclk"), + CLK_MSR_ID(114, "audio_tdmin_c_sclk"), + CLK_MSR_ID(115, "audio_tdmin_b_sclk"), + CLK_MSR_ID(116, "audio_tdmin_a_sclk"), + CLK_MSR_ID(117, "audio_resample"), + CLK_MSR_ID(118, "audio_pdm_sys"), + CLK_MSR_ID(119, "audio_spdifout_b"), + CLK_MSR_ID(120, "audio_spdifout"), + CLK_MSR_ID(121, "audio_spdifin"), + CLK_MSR_ID(122, "audio_pdm_dclk"), +}; + static int meson_measure_id(struct meson_msr_id *clk_msr_id, unsigned int duration) { @@ -337,6 +523,14 @@ static const struct of_device_id meson_msr_match_table[] = { .compatible = "amlogic,meson8b-clk-measure", .data = (void *)clk_msr_m8, }, + { + .compatible = "amlogic,meson-axg-clk-measure", + .data = (void *)clk_msr_axg, + }, + { + .compatible = "amlogic,meson-g12a-clk-measure", + .data = (void *)clk_msr_g12a, + }, { /* sentinel */ } }; -- 2.20.1 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v2 2/4] soc: amlogic: clk-measure: add axg and g12a support 2019-01-18 10:34 ` Jerome Brunet @ 2019-01-18 21:53 ` Martin Blumenstingl -1 siblings, 0 replies; 25+ messages in thread From: Martin Blumenstingl @ 2019-01-18 21:53 UTC (permalink / raw) To: Jerome Brunet Cc: Kevin Hilman, devicetree, patchwork-bot+notify, linux-kernel, linux-amlogic Hi Jerome, On Fri, Jan 18, 2019 at 11:34 AM Jerome Brunet <jbrunet@baylibre.com> wrote: > > Add support for the axg and g12a SoC family in amlogic clk measure > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> with the "wifi_beacon" issue below solved: Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> please have a look at the other comments regarding G12A as well. since I don't have any other information than what's available in buildroot_openlinux_kernel_4.9_fbdev_20180706 I can't say whether your IDs / names are right or not (all I can say is: some don't match with that specific buildroot version). > --- > drivers/soc/amlogic/meson-clk-measure.c | 194 ++++++++++++++++++++++++ > 1 file changed, 194 insertions(+) > > diff --git a/drivers/soc/amlogic/meson-clk-measure.c b/drivers/soc/amlogic/meson-clk-measure.c > index daea191a66fa..5570180b94a1 100644 > --- a/drivers/soc/amlogic/meson-clk-measure.c > +++ b/drivers/soc/amlogic/meson-clk-measure.c > @@ -165,6 +165,192 @@ static struct meson_msr_id clk_msr_gx[CLK_MSR_MAX] = { > CLK_MSR_ID(82, "ge2d"), > }; > > +static struct meson_msr_id clk_msr_axg[CLK_MSR_MAX] = { > + CLK_MSR_ID(0, "ring_osc_out_ee_0"), > + CLK_MSR_ID(1, "ring_osc_out_ee_1"), > + CLK_MSR_ID(2, "ring_osc_out_ee_2"), > + CLK_MSR_ID(3, "a53_ring_osc"), > + CLK_MSR_ID(4, "gp0_pll"), > + CLK_MSR_ID(5, "gp1_pll"), > + CLK_MSR_ID(7, "clk81"), > + CLK_MSR_ID(9, "encl"), > + CLK_MSR_ID(17, "sys_pll_div16"), > + CLK_MSR_ID(18, "sys_cpu_div16"), > + CLK_MSR_ID(20, "rtc_osc_out"), > + CLK_MSR_ID(23, "mmc_clk"), > + CLK_MSR_ID(28, "sar_adc"), > + CLK_MSR_ID(31, "mpll_test_out"), > + CLK_MSR_ID(40, "mod_eth_tx_clk"), > + CLK_MSR_ID(41, "mod_eth_rx_clk_rmii"), > + CLK_MSR_ID(42, "mp0_out"), > + CLK_MSR_ID(43, "fclk_div5"), > + CLK_MSR_ID(44, "pwm_b"), > + CLK_MSR_ID(45, "pwm_a"), > + CLK_MSR_ID(46, "vpu"), > + CLK_MSR_ID(47, "ddr_dpll_pt"), > + CLK_MSR_ID(48, "mp1_out"), > + CLK_MSR_ID(49, "mp2_out"), > + CLK_MSR_ID(50, "mp3_out"), > + CLK_MSR_ID(51, "sd_emmm_c"), > + CLK_MSR_ID(52, "sd_emmc_b"), > + CLK_MSR_ID(61, "gpio_msr"), > + CLK_MSR_ID(66, "audio_slv_lrclk_c"), > + CLK_MSR_ID(67, "audio_slv_lrclk_b"), > + CLK_MSR_ID(68, "audio_slv_lrclk_a"), > + CLK_MSR_ID(69, "audio_slv_sclk_c"), > + CLK_MSR_ID(70, "audio_slv_sclk_b"), > + CLK_MSR_ID(71, "audio_slv_sclk_a"), > + CLK_MSR_ID(72, "pwm_d"), > + CLK_MSR_ID(73, "pwm_c"), > + CLK_MSR_ID(73, "wifi_beacon"), "wifi_beacon" is ID 74 according to Amlogic's buildroot kernel sources (buildroot_openlinux_kernel_4.9_fbdev_20180706) > + CLK_MSR_ID(75, "tdmin_lb_lrcl"), > + CLK_MSR_ID(76, "tdmin_lb_sclk"), > + CLK_MSR_ID(77, "rng_ring_osc_0"), > + CLK_MSR_ID(78, "rng_ring_osc_1"), > + CLK_MSR_ID(79, "rng_ring_osc_2"), > + CLK_MSR_ID(80, "rng_ring_osc_3"), > + CLK_MSR_ID(81, "vapb"), > + CLK_MSR_ID(82, "ge2d"), > + CLK_MSR_ID(84, "audio_resample"), > + CLK_MSR_ID(85, "audio_pdm_sys"), > + CLK_MSR_ID(86, "audio_spdifout"), > + CLK_MSR_ID(87, "audio_spdifin"), > + CLK_MSR_ID(88, "audio_lrclk_f"), > + CLK_MSR_ID(89, "audio_lrclk_e"), > + CLK_MSR_ID(90, "audio_lrclk_d"), > + CLK_MSR_ID(91, "audio_lrclk_c"), > + CLK_MSR_ID(92, "audio_lrclk_b"), > + CLK_MSR_ID(93, "audio_lrclk_a"), > + CLK_MSR_ID(94, "audio_sclk_f"), > + CLK_MSR_ID(95, "audio_sclk_e"), > + CLK_MSR_ID(96, "audio_sclk_d"), > + CLK_MSR_ID(97, "audio_sclk_c"), > + CLK_MSR_ID(98, "audio_sclk_b"), > + CLK_MSR_ID(99, "audio_sclk_a"), > + CLK_MSR_ID(100, "audio_mclk_f"), > + CLK_MSR_ID(101, "audio_mclk_e"), > + CLK_MSR_ID(102, "audio_mclk_d"), > + CLK_MSR_ID(103, "audio_mclk_c"), > + CLK_MSR_ID(104, "audio_mclk_b"), > + CLK_MSR_ID(105, "audio_mclk_a"), > + CLK_MSR_ID(106, "pcie_refclk_n"), > + CLK_MSR_ID(107, "pcie_refclk_p"), > + CLK_MSR_ID(108, "audio_locker_out"), > + CLK_MSR_ID(109, "audio_locker_in"), > +}; > + > +static struct meson_msr_id clk_msr_g12a[CLK_MSR_MAX] = { > + CLK_MSR_ID(0, "ring_osc_out_ee_0"), > + CLK_MSR_ID(1, "ring_osc_out_ee_1"), > + CLK_MSR_ID(2, "ring_osc_out_ee_2"), > + CLK_MSR_ID(3, "sys_cpu_ring_osc"), > + CLK_MSR_ID(4, "gp0_pll"), > + CLK_MSR_ID(6, "enci"), > + CLK_MSR_ID(7, "clk81"), > + CLK_MSR_ID(8, "encp"), > + CLK_MSR_ID(9, "encl"), > + CLK_MSR_ID(10, "vdac"), > + CLK_MSR_ID(11, "eth_tx"), Amlogic's buildroot kernel (buildroot_openlinux_kernel_4.9_fbdev_20180706) calls this "mac_eth_tx_clk". I leave it up to you whether you want to change it to "mac_eth_tx" or not (it's only used for debugging purpose and I don't know what the actual signal name in the G12A datasheet is) > + CLK_MSR_ID(12, "hifi_pll"), > + CLK_MSR_ID(13, "mod_tcon"), > + CLK_MSR_ID(14, "fec_0"), > + CLK_MSR_ID(15, "fec_1"), > + CLK_MSR_ID(16, "fec_2"), > + CLK_MSR_ID(17, "sys_pll_div16"), > + CLK_MSR_ID(18, "sys_cpu_div16"), > + CLK_MSR_ID(19, "lcd_an_ph2"), > + CLK_MSR_ID(20, "rtc_osc_out"), > + CLK_MSR_ID(21, "lcd_an_ph3"), > + CLK_MSR_ID(22, "eth_phy_ref"), similar to the "eth_tx" clock above this is called "mac_eth_phy_ref_clk" in the buildroot kernel which I'm using as reference > + CLK_MSR_ID(23, "mpll_50m"), > + CLK_MSR_ID(24, "eth_125m"), > + CLK_MSR_ID(25, "eth_rmii"), > + CLK_MSR_ID(26, "sc_int"), > + CLK_MSR_ID(27, "in_mac"), > + CLK_MSR_ID(28, "sar_adc"), Amlogic's buildroot_openlinux_kernel_4.9_fbdev_20180706 kernel also has: 29 = "pcie_clk_inp" 30 = "pcie_clk_inn" > + CLK_MSR_ID(31, "mpll_test_out"), > + CLK_MSR_ID(32, "vdec"), > + CLK_MSR_ID(33, "sys_cpu_ring_osc_1"), > + CLK_MSR_ID(34, "eth_mpll_50m"), > + CLK_MSR_ID(35, "mali"), > + CLK_MSR_ID(36, "hdmi_tx_pixel"), > + CLK_MSR_ID(37, "cdac"), > + CLK_MSR_ID(38, "vdin_meas"), > + CLK_MSR_ID(39, "bt656"), > + CLK_MSR_ID(41, "eth_rx_or_rmii"), similar to the "eth_tx" clock above this is called "mac_eth_rx_clk_rmii" in the buildroot kernel which I'm using as reference > + CLK_MSR_ID(42, "mp0_out"), > + CLK_MSR_ID(43, "fclk_div5"), > + CLK_MSR_ID(44, "pwm_b"), > + CLK_MSR_ID(45, "pwm_a"), > + CLK_MSR_ID(46, "vpu"), > + CLK_MSR_ID(47, "ddr_dpll_pt"), > + CLK_MSR_ID(48, "mp1_out"), > + CLK_MSR_ID(49, "mp2_out"), > + CLK_MSR_ID(50, "mp3_out"), > + CLK_MSR_ID(51, "sd_emmc_c"), > + CLK_MSR_ID(52, "sd_emmc_b"), > + CLK_MSR_ID(53, "sd_emmc_a"), > + CLK_MSR_ID(54, "vpu_clkc"), > + CLK_MSR_ID(55, "vid_pll_div_out"), > + CLK_MSR_ID(56, "wave420l_a"), > + CLK_MSR_ID(57, "wave420l_c"), > + CLK_MSR_ID(58, "wave420l_b"), > + CLK_MSR_ID(59, "hcodec"), > + CLK_MSR_ID(61, "gpio_msr"), > + CLK_MSR_ID(62, "hevcb"), > + CLK_MSR_ID(63, "dsi_meas"), > + CLK_MSR_ID(64, "spicc_1"), > + CLK_MSR_ID(65, "spicc_0"), > + CLK_MSR_ID(66, "vid_lock"), > + CLK_MSR_ID(67, "dsi_phy"), > + CLK_MSR_ID(68, "hdcp22_skp"), > + CLK_MSR_ID(69, "hdcp22_esm"), buildroot_openlinux_kernel_4.9_fbdev_20180706 has these 68 and 69 swapped, I'm not sure which one is right though: 69 = "cts_hdcp22_skpclk" 68 = "cts_hdcp22_esmclk" > + CLK_MSR_ID(70, "pwm_f"), > + CLK_MSR_ID(71, "pwm_e"), > + CLK_MSR_ID(72, "pwm_d"), > + CLK_MSR_ID(73, "pwm_c"), > + CLK_MSR_ID(75, "hevcf"), > + CLK_MSR_ID(77, "rng_ring_osc_0"), > + CLK_MSR_ID(78, "rng_ring_osc_1"), > + CLK_MSR_ID(79, "rng_ring_osc_2"), > + CLK_MSR_ID(80, "rng_ring_osc_3"), > + CLK_MSR_ID(81, "vapb"), > + CLK_MSR_ID(82, "ge2d"), > + CLK_MSR_ID(83, "co_rx"), > + CLK_MSR_ID(84, "co_tx"), > + CLK_MSR_ID(89, "hdmi_todig"), > + CLK_MSR_ID(90, "hdmitx_sys"), > + CLK_MSR_ID(94, "eth_phy_rx"), > + CLK_MSR_ID(95, "eth_phy_pll"), this is called "eth_phy_plltxclk" in buildroot_openlinux_kernel_4.9_fbdev_20180706 which I'm using as refernece > + CLK_MSR_ID(96, "vpu_b"), > + CLK_MSR_ID(97, "cpu_b_tmp"), > + CLK_MSR_ID(98, "ts"), > + CLK_MSR_ID(99, "ring_osc_out_ee_3"), > + CLK_MSR_ID(100, "ring_osc_out_ee_4"), > + CLK_MSR_ID(101, "ring_osc_out_ee_5"), > + CLK_MSR_ID(102, "ring_osc_out_ee_6"), > + CLK_MSR_ID(103, "ring_osc_out_ee_7"), > + CLK_MSR_ID(104, "ring_osc_out_ee_8"), > + CLK_MSR_ID(105, "ring_osc_out_ee_9"), > + CLK_MSR_ID(106, "ephy_test"), > + CLK_MSR_ID(107, "au_dac_g128x"), > + CLK_MSR_ID(108, "audio_locker_out"), > + CLK_MSR_ID(109, "audio_locker_in"), > + CLK_MSR_ID(110, "audio_tdmout_c_sclk"), > + CLK_MSR_ID(111, "audio_tdmout_b_sclk"), > + CLK_MSR_ID(112, "audio_tdmout_a_sclk"), > + CLK_MSR_ID(113, "audio_tdmin_lb_sclk"), > + CLK_MSR_ID(114, "audio_tdmin_c_sclk"), > + CLK_MSR_ID(115, "audio_tdmin_b_sclk"), > + CLK_MSR_ID(116, "audio_tdmin_a_sclk"), > + CLK_MSR_ID(117, "audio_resample"), > + CLK_MSR_ID(118, "audio_pdm_sys"), > + CLK_MSR_ID(119, "audio_spdifout_b"), > + CLK_MSR_ID(120, "audio_spdifout"), > + CLK_MSR_ID(121, "audio_spdifin"), the three clocks above use a "_mst_clk" suffix in buildroot_openlinux_kernel_4.9_fbdev_20180706. I'm not sure if that "_mst" suffix is relevant (might stand for "master") Regards Martin _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 2/4] soc: amlogic: clk-measure: add axg and g12a support @ 2019-01-18 21:53 ` Martin Blumenstingl 0 siblings, 0 replies; 25+ messages in thread From: Martin Blumenstingl @ 2019-01-18 21:53 UTC (permalink / raw) To: Jerome Brunet Cc: Kevin Hilman, linux-amlogic, devicetree, patchwork-bot+notify, linux-kernel Hi Jerome, On Fri, Jan 18, 2019 at 11:34 AM Jerome Brunet <jbrunet@baylibre.com> wrote: > > Add support for the axg and g12a SoC family in amlogic clk measure > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> with the "wifi_beacon" issue below solved: Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> please have a look at the other comments regarding G12A as well. since I don't have any other information than what's available in buildroot_openlinux_kernel_4.9_fbdev_20180706 I can't say whether your IDs / names are right or not (all I can say is: some don't match with that specific buildroot version). > --- > drivers/soc/amlogic/meson-clk-measure.c | 194 ++++++++++++++++++++++++ > 1 file changed, 194 insertions(+) > > diff --git a/drivers/soc/amlogic/meson-clk-measure.c b/drivers/soc/amlogic/meson-clk-measure.c > index daea191a66fa..5570180b94a1 100644 > --- a/drivers/soc/amlogic/meson-clk-measure.c > +++ b/drivers/soc/amlogic/meson-clk-measure.c > @@ -165,6 +165,192 @@ static struct meson_msr_id clk_msr_gx[CLK_MSR_MAX] = { > CLK_MSR_ID(82, "ge2d"), > }; > > +static struct meson_msr_id clk_msr_axg[CLK_MSR_MAX] = { > + CLK_MSR_ID(0, "ring_osc_out_ee_0"), > + CLK_MSR_ID(1, "ring_osc_out_ee_1"), > + CLK_MSR_ID(2, "ring_osc_out_ee_2"), > + CLK_MSR_ID(3, "a53_ring_osc"), > + CLK_MSR_ID(4, "gp0_pll"), > + CLK_MSR_ID(5, "gp1_pll"), > + CLK_MSR_ID(7, "clk81"), > + CLK_MSR_ID(9, "encl"), > + CLK_MSR_ID(17, "sys_pll_div16"), > + CLK_MSR_ID(18, "sys_cpu_div16"), > + CLK_MSR_ID(20, "rtc_osc_out"), > + CLK_MSR_ID(23, "mmc_clk"), > + CLK_MSR_ID(28, "sar_adc"), > + CLK_MSR_ID(31, "mpll_test_out"), > + CLK_MSR_ID(40, "mod_eth_tx_clk"), > + CLK_MSR_ID(41, "mod_eth_rx_clk_rmii"), > + CLK_MSR_ID(42, "mp0_out"), > + CLK_MSR_ID(43, "fclk_div5"), > + CLK_MSR_ID(44, "pwm_b"), > + CLK_MSR_ID(45, "pwm_a"), > + CLK_MSR_ID(46, "vpu"), > + CLK_MSR_ID(47, "ddr_dpll_pt"), > + CLK_MSR_ID(48, "mp1_out"), > + CLK_MSR_ID(49, "mp2_out"), > + CLK_MSR_ID(50, "mp3_out"), > + CLK_MSR_ID(51, "sd_emmm_c"), > + CLK_MSR_ID(52, "sd_emmc_b"), > + CLK_MSR_ID(61, "gpio_msr"), > + CLK_MSR_ID(66, "audio_slv_lrclk_c"), > + CLK_MSR_ID(67, "audio_slv_lrclk_b"), > + CLK_MSR_ID(68, "audio_slv_lrclk_a"), > + CLK_MSR_ID(69, "audio_slv_sclk_c"), > + CLK_MSR_ID(70, "audio_slv_sclk_b"), > + CLK_MSR_ID(71, "audio_slv_sclk_a"), > + CLK_MSR_ID(72, "pwm_d"), > + CLK_MSR_ID(73, "pwm_c"), > + CLK_MSR_ID(73, "wifi_beacon"), "wifi_beacon" is ID 74 according to Amlogic's buildroot kernel sources (buildroot_openlinux_kernel_4.9_fbdev_20180706) > + CLK_MSR_ID(75, "tdmin_lb_lrcl"), > + CLK_MSR_ID(76, "tdmin_lb_sclk"), > + CLK_MSR_ID(77, "rng_ring_osc_0"), > + CLK_MSR_ID(78, "rng_ring_osc_1"), > + CLK_MSR_ID(79, "rng_ring_osc_2"), > + CLK_MSR_ID(80, "rng_ring_osc_3"), > + CLK_MSR_ID(81, "vapb"), > + CLK_MSR_ID(82, "ge2d"), > + CLK_MSR_ID(84, "audio_resample"), > + CLK_MSR_ID(85, "audio_pdm_sys"), > + CLK_MSR_ID(86, "audio_spdifout"), > + CLK_MSR_ID(87, "audio_spdifin"), > + CLK_MSR_ID(88, "audio_lrclk_f"), > + CLK_MSR_ID(89, "audio_lrclk_e"), > + CLK_MSR_ID(90, "audio_lrclk_d"), > + CLK_MSR_ID(91, "audio_lrclk_c"), > + CLK_MSR_ID(92, "audio_lrclk_b"), > + CLK_MSR_ID(93, "audio_lrclk_a"), > + CLK_MSR_ID(94, "audio_sclk_f"), > + CLK_MSR_ID(95, "audio_sclk_e"), > + CLK_MSR_ID(96, "audio_sclk_d"), > + CLK_MSR_ID(97, "audio_sclk_c"), > + CLK_MSR_ID(98, "audio_sclk_b"), > + CLK_MSR_ID(99, "audio_sclk_a"), > + CLK_MSR_ID(100, "audio_mclk_f"), > + CLK_MSR_ID(101, "audio_mclk_e"), > + CLK_MSR_ID(102, "audio_mclk_d"), > + CLK_MSR_ID(103, "audio_mclk_c"), > + CLK_MSR_ID(104, "audio_mclk_b"), > + CLK_MSR_ID(105, "audio_mclk_a"), > + CLK_MSR_ID(106, "pcie_refclk_n"), > + CLK_MSR_ID(107, "pcie_refclk_p"), > + CLK_MSR_ID(108, "audio_locker_out"), > + CLK_MSR_ID(109, "audio_locker_in"), > +}; > + > +static struct meson_msr_id clk_msr_g12a[CLK_MSR_MAX] = { > + CLK_MSR_ID(0, "ring_osc_out_ee_0"), > + CLK_MSR_ID(1, "ring_osc_out_ee_1"), > + CLK_MSR_ID(2, "ring_osc_out_ee_2"), > + CLK_MSR_ID(3, "sys_cpu_ring_osc"), > + CLK_MSR_ID(4, "gp0_pll"), > + CLK_MSR_ID(6, "enci"), > + CLK_MSR_ID(7, "clk81"), > + CLK_MSR_ID(8, "encp"), > + CLK_MSR_ID(9, "encl"), > + CLK_MSR_ID(10, "vdac"), > + CLK_MSR_ID(11, "eth_tx"), Amlogic's buildroot kernel (buildroot_openlinux_kernel_4.9_fbdev_20180706) calls this "mac_eth_tx_clk". I leave it up to you whether you want to change it to "mac_eth_tx" or not (it's only used for debugging purpose and I don't know what the actual signal name in the G12A datasheet is) > + CLK_MSR_ID(12, "hifi_pll"), > + CLK_MSR_ID(13, "mod_tcon"), > + CLK_MSR_ID(14, "fec_0"), > + CLK_MSR_ID(15, "fec_1"), > + CLK_MSR_ID(16, "fec_2"), > + CLK_MSR_ID(17, "sys_pll_div16"), > + CLK_MSR_ID(18, "sys_cpu_div16"), > + CLK_MSR_ID(19, "lcd_an_ph2"), > + CLK_MSR_ID(20, "rtc_osc_out"), > + CLK_MSR_ID(21, "lcd_an_ph3"), > + CLK_MSR_ID(22, "eth_phy_ref"), similar to the "eth_tx" clock above this is called "mac_eth_phy_ref_clk" in the buildroot kernel which I'm using as reference > + CLK_MSR_ID(23, "mpll_50m"), > + CLK_MSR_ID(24, "eth_125m"), > + CLK_MSR_ID(25, "eth_rmii"), > + CLK_MSR_ID(26, "sc_int"), > + CLK_MSR_ID(27, "in_mac"), > + CLK_MSR_ID(28, "sar_adc"), Amlogic's buildroot_openlinux_kernel_4.9_fbdev_20180706 kernel also has: 29 = "pcie_clk_inp" 30 = "pcie_clk_inn" > + CLK_MSR_ID(31, "mpll_test_out"), > + CLK_MSR_ID(32, "vdec"), > + CLK_MSR_ID(33, "sys_cpu_ring_osc_1"), > + CLK_MSR_ID(34, "eth_mpll_50m"), > + CLK_MSR_ID(35, "mali"), > + CLK_MSR_ID(36, "hdmi_tx_pixel"), > + CLK_MSR_ID(37, "cdac"), > + CLK_MSR_ID(38, "vdin_meas"), > + CLK_MSR_ID(39, "bt656"), > + CLK_MSR_ID(41, "eth_rx_or_rmii"), similar to the "eth_tx" clock above this is called "mac_eth_rx_clk_rmii" in the buildroot kernel which I'm using as reference > + CLK_MSR_ID(42, "mp0_out"), > + CLK_MSR_ID(43, "fclk_div5"), > + CLK_MSR_ID(44, "pwm_b"), > + CLK_MSR_ID(45, "pwm_a"), > + CLK_MSR_ID(46, "vpu"), > + CLK_MSR_ID(47, "ddr_dpll_pt"), > + CLK_MSR_ID(48, "mp1_out"), > + CLK_MSR_ID(49, "mp2_out"), > + CLK_MSR_ID(50, "mp3_out"), > + CLK_MSR_ID(51, "sd_emmc_c"), > + CLK_MSR_ID(52, "sd_emmc_b"), > + CLK_MSR_ID(53, "sd_emmc_a"), > + CLK_MSR_ID(54, "vpu_clkc"), > + CLK_MSR_ID(55, "vid_pll_div_out"), > + CLK_MSR_ID(56, "wave420l_a"), > + CLK_MSR_ID(57, "wave420l_c"), > + CLK_MSR_ID(58, "wave420l_b"), > + CLK_MSR_ID(59, "hcodec"), > + CLK_MSR_ID(61, "gpio_msr"), > + CLK_MSR_ID(62, "hevcb"), > + CLK_MSR_ID(63, "dsi_meas"), > + CLK_MSR_ID(64, "spicc_1"), > + CLK_MSR_ID(65, "spicc_0"), > + CLK_MSR_ID(66, "vid_lock"), > + CLK_MSR_ID(67, "dsi_phy"), > + CLK_MSR_ID(68, "hdcp22_skp"), > + CLK_MSR_ID(69, "hdcp22_esm"), buildroot_openlinux_kernel_4.9_fbdev_20180706 has these 68 and 69 swapped, I'm not sure which one is right though: 69 = "cts_hdcp22_skpclk" 68 = "cts_hdcp22_esmclk" > + CLK_MSR_ID(70, "pwm_f"), > + CLK_MSR_ID(71, "pwm_e"), > + CLK_MSR_ID(72, "pwm_d"), > + CLK_MSR_ID(73, "pwm_c"), > + CLK_MSR_ID(75, "hevcf"), > + CLK_MSR_ID(77, "rng_ring_osc_0"), > + CLK_MSR_ID(78, "rng_ring_osc_1"), > + CLK_MSR_ID(79, "rng_ring_osc_2"), > + CLK_MSR_ID(80, "rng_ring_osc_3"), > + CLK_MSR_ID(81, "vapb"), > + CLK_MSR_ID(82, "ge2d"), > + CLK_MSR_ID(83, "co_rx"), > + CLK_MSR_ID(84, "co_tx"), > + CLK_MSR_ID(89, "hdmi_todig"), > + CLK_MSR_ID(90, "hdmitx_sys"), > + CLK_MSR_ID(94, "eth_phy_rx"), > + CLK_MSR_ID(95, "eth_phy_pll"), this is called "eth_phy_plltxclk" in buildroot_openlinux_kernel_4.9_fbdev_20180706 which I'm using as refernece > + CLK_MSR_ID(96, "vpu_b"), > + CLK_MSR_ID(97, "cpu_b_tmp"), > + CLK_MSR_ID(98, "ts"), > + CLK_MSR_ID(99, "ring_osc_out_ee_3"), > + CLK_MSR_ID(100, "ring_osc_out_ee_4"), > + CLK_MSR_ID(101, "ring_osc_out_ee_5"), > + CLK_MSR_ID(102, "ring_osc_out_ee_6"), > + CLK_MSR_ID(103, "ring_osc_out_ee_7"), > + CLK_MSR_ID(104, "ring_osc_out_ee_8"), > + CLK_MSR_ID(105, "ring_osc_out_ee_9"), > + CLK_MSR_ID(106, "ephy_test"), > + CLK_MSR_ID(107, "au_dac_g128x"), > + CLK_MSR_ID(108, "audio_locker_out"), > + CLK_MSR_ID(109, "audio_locker_in"), > + CLK_MSR_ID(110, "audio_tdmout_c_sclk"), > + CLK_MSR_ID(111, "audio_tdmout_b_sclk"), > + CLK_MSR_ID(112, "audio_tdmout_a_sclk"), > + CLK_MSR_ID(113, "audio_tdmin_lb_sclk"), > + CLK_MSR_ID(114, "audio_tdmin_c_sclk"), > + CLK_MSR_ID(115, "audio_tdmin_b_sclk"), > + CLK_MSR_ID(116, "audio_tdmin_a_sclk"), > + CLK_MSR_ID(117, "audio_resample"), > + CLK_MSR_ID(118, "audio_pdm_sys"), > + CLK_MSR_ID(119, "audio_spdifout_b"), > + CLK_MSR_ID(120, "audio_spdifout"), > + CLK_MSR_ID(121, "audio_spdifin"), the three clocks above use a "_mst_clk" suffix in buildroot_openlinux_kernel_4.9_fbdev_20180706. I'm not sure if that "_mst" suffix is relevant (might stand for "master") Regards Martin ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 3/4] arm64: dts: meson: axg: add clk measure support 2019-01-18 10:34 ` Jerome Brunet @ 2019-01-18 10:34 ` Jerome Brunet -1 siblings, 0 replies; 25+ messages in thread From: Jerome Brunet @ 2019-01-18 10:34 UTC (permalink / raw) To: Kevin Hilman Cc: linux-amlogic, devicetree, patchwork-bot+notify, linux-kernel, Jerome Brunet Add the clock measure device to the axg SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index f044473dc7d0..398b7ac1b107 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -1610,6 +1610,11 @@ status = "disabled"; }; + clk_msr: clock-measure@18000 { + compatible = "amlogic,meson-axg-clk-measure"; + reg = <0x0 0x18000 0x0 0x10>; + }; + i2c3: i2c@1c000 { compatible = "amlogic,meson-axg-i2c"; reg = <0x0 0x1c000 0x0 0x20>; -- 2.20.1 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 3/4] arm64: dts: meson: axg: add clk measure support @ 2019-01-18 10:34 ` Jerome Brunet 0 siblings, 0 replies; 25+ messages in thread From: Jerome Brunet @ 2019-01-18 10:34 UTC (permalink / raw) To: Kevin Hilman Cc: Jerome Brunet, linux-amlogic, devicetree, linux-kernel, patchwork-bot+notify Add the clock measure device to the axg SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index f044473dc7d0..398b7ac1b107 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -1610,6 +1610,11 @@ status = "disabled"; }; + clk_msr: clock-measure@18000 { + compatible = "amlogic,meson-axg-clk-measure"; + reg = <0x0 0x18000 0x0 0x10>; + }; + i2c3: i2c@1c000 { compatible = "amlogic,meson-axg-i2c"; reg = <0x0 0x1c000 0x0 0x20>; -- 2.20.1 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v2 3/4] arm64: dts: meson: axg: add clk measure support 2019-01-18 10:34 ` Jerome Brunet @ 2019-01-18 21:57 ` Martin Blumenstingl -1 siblings, 0 replies; 25+ messages in thread From: Martin Blumenstingl @ 2019-01-18 21:57 UTC (permalink / raw) To: Jerome Brunet Cc: Kevin Hilman, devicetree, patchwork-bot+notify, linux-kernel, linux-amlogic On Fri, Jan 18, 2019 at 11:34 AM Jerome Brunet <jbrunet@baylibre.com> wrote: > > Add the clock measure device to the axg SoC family > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > --- > arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > index f044473dc7d0..398b7ac1b107 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > @@ -1610,6 +1610,11 @@ > status = "disabled"; > }; > > + clk_msr: clock-measure@18000 { thanks for updating this to use "clock-measure" (for consistency with what Rob acked in the example and what we use on the GX SoCs)! _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 3/4] arm64: dts: meson: axg: add clk measure support @ 2019-01-18 21:57 ` Martin Blumenstingl 0 siblings, 0 replies; 25+ messages in thread From: Martin Blumenstingl @ 2019-01-18 21:57 UTC (permalink / raw) To: Jerome Brunet Cc: Kevin Hilman, linux-amlogic, devicetree, patchwork-bot+notify, linux-kernel On Fri, Jan 18, 2019 at 11:34 AM Jerome Brunet <jbrunet@baylibre.com> wrote: > > Add the clock measure device to the axg SoC family > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > --- > arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > index f044473dc7d0..398b7ac1b107 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > @@ -1610,6 +1610,11 @@ > status = "disabled"; > }; > > + clk_msr: clock-measure@18000 { thanks for updating this to use "clock-measure" (for consistency with what Rob acked in the example and what we use on the GX SoCs)! ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 4/4] arm64: dts: meson: g12a: add clk measure support 2019-01-18 10:34 ` Jerome Brunet @ 2019-01-18 10:34 ` Jerome Brunet -1 siblings, 0 replies; 25+ messages in thread From: Jerome Brunet @ 2019-01-18 10:34 UTC (permalink / raw) To: Kevin Hilman Cc: linux-amlogic, devicetree, patchwork-bot+notify, linux-kernel, Jerome Brunet Add the clock measure device to the g12a SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> --- arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index bd24de947a5b..59900ddb7b43 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -193,6 +193,11 @@ #interrupt-cells = <3>; #address-cells = <0>; }; + + clk_msr: clock-measure@ffd18000 { + compatible = "amlogic,meson-g12a-clk-measure"; + reg = <0x0 0xffd18000 0x0 0x10>; + }; }; timer { -- 2.20.1 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 4/4] arm64: dts: meson: g12a: add clk measure support @ 2019-01-18 10:34 ` Jerome Brunet 0 siblings, 0 replies; 25+ messages in thread From: Jerome Brunet @ 2019-01-18 10:34 UTC (permalink / raw) To: Kevin Hilman Cc: Jerome Brunet, linux-amlogic, devicetree, linux-kernel, patchwork-bot+notify Add the clock measure device to the g12a SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> --- arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index bd24de947a5b..59900ddb7b43 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -193,6 +193,11 @@ #interrupt-cells = <3>; #address-cells = <0>; }; + + clk_msr: clock-measure@ffd18000 { + compatible = "amlogic,meson-g12a-clk-measure"; + reg = <0x0 0xffd18000 0x0 0x10>; + }; }; timer { -- 2.20.1 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v2 4/4] arm64: dts: meson: g12a: add clk measure support 2019-01-18 10:34 ` Jerome Brunet @ 2019-01-18 21:59 ` Martin Blumenstingl -1 siblings, 0 replies; 25+ messages in thread From: Martin Blumenstingl @ 2019-01-18 21:59 UTC (permalink / raw) To: Jerome Brunet Cc: Kevin Hilman, devicetree, patchwork-bot+notify, linux-kernel, linux-amlogic On Fri, Jan 18, 2019 at 11:34 AM Jerome Brunet <jbrunet@baylibre.com> wrote: > > Add the clock measure device to the g12a SoC family > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> > --- > arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > index bd24de947a5b..59900ddb7b43 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > @@ -193,6 +193,11 @@ > #interrupt-cells = <3>; > #address-cells = <0>; > }; > + > + clk_msr: clock-measure@ffd18000 { > + compatible = "amlogic,meson-g12a-clk-measure"; > + reg = <0x0 0xffd18000 0x0 0x10>; > + }; I'll wait with my Reviewed-by until we have a result in the G12A bus discussion in "arm64: dts: meson: g12a: add clk measure support" from [0] [0] https://patchwork.kernel.org/patch/10766427/ _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 4/4] arm64: dts: meson: g12a: add clk measure support @ 2019-01-18 21:59 ` Martin Blumenstingl 0 siblings, 0 replies; 25+ messages in thread From: Martin Blumenstingl @ 2019-01-18 21:59 UTC (permalink / raw) To: Jerome Brunet Cc: Kevin Hilman, linux-amlogic, devicetree, patchwork-bot+notify, linux-kernel On Fri, Jan 18, 2019 at 11:34 AM Jerome Brunet <jbrunet@baylibre.com> wrote: > > Add the clock measure device to the g12a SoC family > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> > --- > arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > index bd24de947a5b..59900ddb7b43 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > @@ -193,6 +193,11 @@ > #interrupt-cells = <3>; > #address-cells = <0>; > }; > + > + clk_msr: clock-measure@ffd18000 { > + compatible = "amlogic,meson-g12a-clk-measure"; > + reg = <0x0 0xffd18000 0x0 0x10>; > + }; I'll wait with my Reviewed-by until we have a result in the G12A bus discussion in "arm64: dts: meson: g12a: add clk measure support" from [0] [0] https://patchwork.kernel.org/patch/10766427/ ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 0/4] soc: amlogic: clk-measure: add axg and g12a support 2019-01-18 10:34 ` Jerome Brunet @ 2019-01-18 10:52 ` Neil Armstrong -1 siblings, 0 replies; 25+ messages in thread From: Neil Armstrong @ 2019-01-18 10:52 UTC (permalink / raw) To: Jerome Brunet, Kevin Hilman Cc: linux-amlogic, patchwork-bot+notify, linux-kernel, devicetree On 18/01/2019 11:34, Jerome Brunet wrote: > This patchset adds support for the axg and g12a SoC family in amlogic's > clock measure driver and enable it on the related devices > > Changes since v1 [0]: > * re-order node in the g12a.dtsi > * change node name > > [0]: https://lkml.kernel.org/r/20190117164838.8008-1-jbrunet@baylibre.com > > Jerome Brunet (4): > dt-bindings: amlogic: add new compatible devices to clk_measure > soc: amlogic: clk-measure: add axg and g12a support > arm64: dts: meson: axg: add clk measure support > arm64: dts: meson: g12a: add clk measure support > > .../bindings/soc/amlogic/clk-measure.txt | 2 + > arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 5 + > arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 5 + > drivers/soc/amlogic/meson-clk-measure.c | 194 ++++++++++++++++++ > 4 files changed, 206 insertions(+) > Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 0/4] soc: amlogic: clk-measure: add axg and g12a support @ 2019-01-18 10:52 ` Neil Armstrong 0 siblings, 0 replies; 25+ messages in thread From: Neil Armstrong @ 2019-01-18 10:52 UTC (permalink / raw) To: Jerome Brunet, Kevin Hilman Cc: linux-amlogic, devicetree, patchwork-bot+notify, linux-kernel On 18/01/2019 11:34, Jerome Brunet wrote: > This patchset adds support for the axg and g12a SoC family in amlogic's > clock measure driver and enable it on the related devices > > Changes since v1 [0]: > * re-order node in the g12a.dtsi > * change node name > > [0]: https://lkml.kernel.org/r/20190117164838.8008-1-jbrunet@baylibre.com > > Jerome Brunet (4): > dt-bindings: amlogic: add new compatible devices to clk_measure > soc: amlogic: clk-measure: add axg and g12a support > arm64: dts: meson: axg: add clk measure support > arm64: dts: meson: g12a: add clk measure support > > .../bindings/soc/amlogic/clk-measure.txt | 2 + > arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 5 + > arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 5 + > drivers/soc/amlogic/meson-clk-measure.c | 194 ++++++++++++++++++ > 4 files changed, 206 insertions(+) > Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 0/4] soc: amlogic: clk-measure: add axg and g12a support 2019-01-18 10:52 ` Neil Armstrong @ 2019-02-07 3:38 ` Kevin Hilman -1 siblings, 0 replies; 25+ messages in thread From: Kevin Hilman @ 2019-02-07 3:38 UTC (permalink / raw) To: Neil Armstrong, Jerome Brunet Cc: linux-amlogic, patchwork-bot+notify, linux-kernel, devicetree Neil Armstrong <narmstrong@baylibre.com> writes: > On 18/01/2019 11:34, Jerome Brunet wrote: >> This patchset adds support for the axg and g12a SoC family in amlogic's >> clock measure driver and enable it on the related devices >> >> Changes since v1 [0]: >> * re-order node in the g12a.dtsi >> * change node name >> >> [0]: https://lkml.kernel.org/r/20190117164838.8008-1-jbrunet@baylibre.com >> >> Jerome Brunet (4): >> dt-bindings: amlogic: add new compatible devices to clk_measure >> soc: amlogic: clk-measure: add axg and g12a support >> arm64: dts: meson: axg: add clk measure support >> arm64: dts: meson: g12a: add clk measure support >> >> .../bindings/soc/amlogic/clk-measure.txt | 2 + >> arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 5 + >> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 5 + >> drivers/soc/amlogic/meson-clk-measure.c | 194 ++++++++++++++++++ >> 4 files changed, 206 insertions(+) >> > > Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Queued for v5.1 (branch v5.1/dt64) Kevin _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 0/4] soc: amlogic: clk-measure: add axg and g12a support @ 2019-02-07 3:38 ` Kevin Hilman 0 siblings, 0 replies; 25+ messages in thread From: Kevin Hilman @ 2019-02-07 3:38 UTC (permalink / raw) To: Neil Armstrong, Jerome Brunet Cc: linux-amlogic, devicetree, patchwork-bot+notify, linux-kernel Neil Armstrong <narmstrong@baylibre.com> writes: > On 18/01/2019 11:34, Jerome Brunet wrote: >> This patchset adds support for the axg and g12a SoC family in amlogic's >> clock measure driver and enable it on the related devices >> >> Changes since v1 [0]: >> * re-order node in the g12a.dtsi >> * change node name >> >> [0]: https://lkml.kernel.org/r/20190117164838.8008-1-jbrunet@baylibre.com >> >> Jerome Brunet (4): >> dt-bindings: amlogic: add new compatible devices to clk_measure >> soc: amlogic: clk-measure: add axg and g12a support >> arm64: dts: meson: axg: add clk measure support >> arm64: dts: meson: g12a: add clk measure support >> >> .../bindings/soc/amlogic/clk-measure.txt | 2 + >> arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 5 + >> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 5 + >> drivers/soc/amlogic/meson-clk-measure.c | 194 ++++++++++++++++++ >> 4 files changed, 206 insertions(+) >> > > Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Queued for v5.1 (branch v5.1/dt64) Kevin ^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2019-02-07 3:38 UTC | newest] Thread overview: 25+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-01-18 10:34 [PATCH v2 0/4] soc: amlogic: clk-measure: add axg and g12a support Jerome Brunet 2019-01-18 10:34 ` Jerome Brunet 2019-01-18 10:34 ` [PATCH v2 1/4] dt-bindings: amlogic: add new compatible devices to clk_measure Jerome Brunet 2019-01-18 10:34 ` Jerome Brunet 2019-01-18 21:56 ` Martin Blumenstingl 2019-01-18 21:56 ` Martin Blumenstingl 2019-01-21 17:11 ` Rob Herring 2019-01-21 17:11 ` Rob Herring 2019-01-21 17:11 ` Rob Herring 2019-01-18 10:34 ` [PATCH v2 2/4] soc: amlogic: clk-measure: add axg and g12a support Jerome Brunet 2019-01-18 10:34 ` Jerome Brunet 2019-01-18 21:53 ` Martin Blumenstingl 2019-01-18 21:53 ` Martin Blumenstingl 2019-01-18 10:34 ` [PATCH v2 3/4] arm64: dts: meson: axg: add clk measure support Jerome Brunet 2019-01-18 10:34 ` Jerome Brunet 2019-01-18 21:57 ` Martin Blumenstingl 2019-01-18 21:57 ` Martin Blumenstingl 2019-01-18 10:34 ` [PATCH v2 4/4] arm64: dts: meson: g12a: " Jerome Brunet 2019-01-18 10:34 ` Jerome Brunet 2019-01-18 21:59 ` Martin Blumenstingl 2019-01-18 21:59 ` Martin Blumenstingl 2019-01-18 10:52 ` [PATCH v2 0/4] soc: amlogic: clk-measure: add axg and g12a support Neil Armstrong 2019-01-18 10:52 ` Neil Armstrong 2019-02-07 3:38 ` Kevin Hilman 2019-02-07 3:38 ` Kevin Hilman
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