[MODERATED] Re: [PATCH v3 6/6] PERFv3

[Peter Zijlstra <peterz@infradead.org>]

On Thu, Feb 07, 2019 at 03:41:08PM -0800, speck for Andi Kleen wrote:
> From: Andi Kleen <ak@linux.intel.com>
> Subject:  kvm: vmx: Support TSX_FORCE_ABORT in KVM guests
> 
> Recent microcode for Skylake added a new CPUID bit and MSR to control
> TSX aborting and enabling PMU counter 3. This patch adds support
> for controlling counter 3 from KVM guests.
> 
> Intercept the MSR and set the correct attribute on the perf events
> used by the virtualized PMU. TSX is only disabled when counter
> 3 is actually used by the host PMU. The guest can use all four
> counters without multiplexing.
> 
> Also export the CPUID bit.
> 
> Signed-off-by: Andi Kleen <ak@linux.intel.com>

I would really rather not do this at all.

Keep this walnut crap as small as possible. The more code you generate,
the more we need to maintain. And very soon nobody will give a crap
about this weird bug anymore, but we're stuck with all this junk.

Also; apparently the virt people themselves already said not to expose
this, so why do you persist.