From: "Jonathan Neuschäfer" <j.neuschaefer@gmx.net>
To: Fabio Estevam <festevam@gmail.com>
Cc: "Jonathan Neuschäfer" <j.neuschaefer@gmx.net>,
linux-clk <linux-clk@vger.kernel.org>,
linux-mmc <linux-mmc@vger.kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
"Ulf Hansson" <ulf.hansson@linaro.org>,
"Stephen Boyd" <sboyd@kernel.org>,
"Sascha Hauer" <s.hauer@pengutronix.de>,
"Adrian Hunter" <adrian.hunter@intel.com>,
"NXP Linux Team" <linux-imx@nxp.com>,
"Pengutronix Kernel Team" <kernel@pengutronix.de>,
"Fabio Estevam" <fabio.estevam@nxp.com>,
"Shawn Guo" <shawnguo@kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: sdhci-esdhc-imx/v5.0-rc5: i.MX50 system hangs when "per" clock is disabled
Date: Sat, 9 Feb 2019 17:24:49 +0100 [thread overview]
Message-ID: <20190209162449.GB2061@latitude> (raw)
In-Reply-To: <CAOMZO5BH1Su=tKD8vV8+-i_0a_4fNDQKbk0q6DX5TZWYezeH9Q@mail.gmail.com>
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On Thu, Feb 07, 2019 at 10:50:28PM -0200, Fabio Estevam wrote:
> On Thu, Feb 7, 2019 at 8:52 PM Jonathan Neuschäfer
[...]
> > I tried to compare the CCM's clocks between i.MX50 and i.MX53, but
> > unfortunately, the i.MX50 reference manual doesn't have the table called
> > "Output clocks from CCM".
>
> Please check Table 5-10. CCM_CCGR3 Gated Clock Mapping to Target
> Module from the MX50 Referene Manual.
Ok, the tables show:
For i.MX50:
[1:0] 0 ipg_clk_root eSDHCv2_1
[3:2] 1 esdhc1_clk_root eSDHCv2_1
For i.MX53:
1–0 CG0 esdhc1_ipg_hclk: affects ipg_clk and hclk inputs of ESDEHC-1 (esdhc1_clk_enable)
3–2 CG1 esdhc1_perclk: affects ipg_clk_perclk input of ESDEHC-1 (esdhc1_serial_clk_enable)
Table 18-3 (Output clocks from CCM) in the iMX53RM shows that
ESDHCv2-1's ipg_clk_perclk is esdhc1_clk_root, so the clock structure
does seem to be the same here, between i.MX50 and i.MX53…
(The reason why I looked at i.MX53 is that there are several i.MX53
boards in tree, so it appears to be well tested under mainline Linux)
> Does the change below help?
>
> --- a/arch/arm/boot/dts/imx50.dtsi
> +++ b/arch/arm/boot/dts/imx50.dtsi
> @@ -102,7 +102,7 @@
> reg = <0x50004000 0x4000>;
> interrupts = <1>;
> clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
> - <&clks IMX5_CLK_DUMMY>,
> + <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
> <&clks IMX5_CLK_ESDHC1_PER_GATE>;
> clock-names = "ipg", "ahb", "per";
Unfortunately, this doesn't help.
Thanks,
Jonathan Neuschäfer
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WARNING: multiple messages have this Message-ID (diff)
From: "Jonathan Neuschäfer" <j.neuschaefer@gmx.net>
To: Fabio Estevam <festevam@gmail.com>
Cc: "Ulf Hansson" <ulf.hansson@linaro.org>,
"Stephen Boyd" <sboyd@kernel.org>,
"Sascha Hauer" <s.hauer@pengutronix.de>,
linux-mmc <linux-mmc@vger.kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
"Jonathan Neuschäfer" <j.neuschaefer@gmx.net>,
"Michael Turquette" <mturquette@baylibre.com>,
"NXP Linux Team" <linux-imx@nxp.com>,
"Pengutronix Kernel Team" <kernel@pengutronix.de>,
"Fabio Estevam" <fabio.estevam@nxp.com>,
"Adrian Hunter" <adrian.hunter@intel.com>,
"Shawn Guo" <shawnguo@kernel.org>,
linux-clk <linux-clk@vger.kernel.org>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: sdhci-esdhc-imx/v5.0-rc5: i.MX50 system hangs when "per" clock is disabled
Date: Sat, 9 Feb 2019 17:24:49 +0100 [thread overview]
Message-ID: <20190209162449.GB2061@latitude> (raw)
In-Reply-To: <CAOMZO5BH1Su=tKD8vV8+-i_0a_4fNDQKbk0q6DX5TZWYezeH9Q@mail.gmail.com>
[-- Attachment #1.1: Type: text/plain, Size: 1827 bytes --]
On Thu, Feb 07, 2019 at 10:50:28PM -0200, Fabio Estevam wrote:
> On Thu, Feb 7, 2019 at 8:52 PM Jonathan Neuschäfer
[...]
> > I tried to compare the CCM's clocks between i.MX50 and i.MX53, but
> > unfortunately, the i.MX50 reference manual doesn't have the table called
> > "Output clocks from CCM".
>
> Please check Table 5-10. CCM_CCGR3 Gated Clock Mapping to Target
> Module from the MX50 Referene Manual.
Ok, the tables show:
For i.MX50:
[1:0] 0 ipg_clk_root eSDHCv2_1
[3:2] 1 esdhc1_clk_root eSDHCv2_1
For i.MX53:
1–0 CG0 esdhc1_ipg_hclk: affects ipg_clk and hclk inputs of ESDEHC-1 (esdhc1_clk_enable)
3–2 CG1 esdhc1_perclk: affects ipg_clk_perclk input of ESDEHC-1 (esdhc1_serial_clk_enable)
Table 18-3 (Output clocks from CCM) in the iMX53RM shows that
ESDHCv2-1's ipg_clk_perclk is esdhc1_clk_root, so the clock structure
does seem to be the same here, between i.MX50 and i.MX53…
(The reason why I looked at i.MX53 is that there are several i.MX53
boards in tree, so it appears to be well tested under mainline Linux)
> Does the change below help?
>
> --- a/arch/arm/boot/dts/imx50.dtsi
> +++ b/arch/arm/boot/dts/imx50.dtsi
> @@ -102,7 +102,7 @@
> reg = <0x50004000 0x4000>;
> interrupts = <1>;
> clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
> - <&clks IMX5_CLK_DUMMY>,
> + <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
> <&clks IMX5_CLK_ESDHC1_PER_GATE>;
> clock-names = "ipg", "ahb", "per";
Unfortunately, this doesn't help.
Thanks,
Jonathan Neuschäfer
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next prev parent reply other threads:[~2019-02-09 16:25 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-07 22:52 sdhci-esdhc-imx/v5.0-rc5: i.MX50 system hangs when "per" clock is disabled Jonathan Neuschäfer
2019-02-07 22:52 ` Jonathan Neuschäfer
2019-02-08 0:50 ` Fabio Estevam
2019-02-08 0:50 ` Fabio Estevam
2019-02-09 16:24 ` Jonathan Neuschäfer [this message]
2019-02-09 16:24 ` Jonathan Neuschäfer
2019-02-09 17:15 ` Fabio Estevam
2019-02-09 17:15 ` Fabio Estevam
2019-02-10 21:32 ` Jonathan Neuschäfer
2019-02-10 21:32 ` Jonathan Neuschäfer
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