[PATCH v5 0/3] Support 64 bpp half float formats

[PATCH v5 0/3] Support 64 bpp half float formats

[Kevin Strasser]

This series defines new formats and adds implementation to the i915 driver.
Since posting v1 I have removed the pixel normalize property, as it's not needed
for basic functionality. Also, I have been working on adding support to
userspace, but we can't land any patches until drm_fourcc.h has been updated
here.

I have submitted a series to Mesa to make use of the RGBA ordered formats:
  https://patchwork.freedesktop.org/series/54759/

My igt branch is reworked to drop usage of pixel normalize and includes use
of f16c intrinsics to speed up conversion:
  https://gitlab.freedesktop.org/strassek/igt-gpu-tools/commits/fp16

I also have a libdrm branch with fp16 coverage added to modetest:
  https://gitlab.freedesktop.org/strassek/drm/commits/fp16

To serve as a smoke test of the whole stack I have a modified version of
kmscube:
  https://gitlab.freedesktop.org/strassek/kmscube/commits/fp16

Kevin Strasser (3):
  drm/fourcc: Add 64 bpp half float formats
  drm/i915: Refactor icl_is_hdr_plane
  drm/i915/icl: Implement half float formats

 drivers/gpu/drm/drm_fourcc.c         |  4 ++
 drivers/gpu/drm/i915/intel_atomic.c  |  3 +-
 drivers/gpu/drm/i915/intel_display.c | 29 +++++++++++++-
 drivers/gpu/drm/i915/intel_drv.h     |  7 ++--
 drivers/gpu/drm/i915/intel_sprite.c  | 73 +++++++++++++++++++++++++++++++-----
 include/uapi/drm/drm_fourcc.h        | 11 ++++++
 6 files changed, 112 insertions(+), 15 deletions(-)

-- 
2.7.4

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[PATCH v5 1/3] drm/fourcc: Add 64 bpp half float formats

[Kevin Strasser]

Add 64 bpp 16:16:16:16 half float pixel formats. Each 16 bit component is
formatted in IEEE-754 half-precision float (binary16) 1:5:10
MSb-sign:exponent:fraction form.

This patch attempts to address the feedback provided when 2 of these
formats were previosly proposed:
  https://patchwork.kernel.org/patch/10072545/

v2:
- Fixed cpp (Ville)
- Added detail pixel formatting (Ville)
- Ordered formats in header (Ville)

v5:
- .depth should be 0 for new formats (Maarten)

Cc: Tina Zhang <tina.zhang@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/drm_fourcc.c  |  4 ++++
 include/uapi/drm/drm_fourcc.h | 11 +++++++++++
 2 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index d90ee03..46da785 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -198,6 +198,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
 		{ .format = DRM_FORMAT_ABGR8888,	.depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
 		{ .format = DRM_FORMAT_RGBA8888,	.depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
 		{ .format = DRM_FORMAT_BGRA8888,	.depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
+		{ .format = DRM_FORMAT_XRGB16161616F,	.depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
+		{ .format = DRM_FORMAT_XBGR16161616F,	.depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
+		{ .format = DRM_FORMAT_ARGB16161616F,	.depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
+		{ .format = DRM_FORMAT_ABGR16161616F,	.depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
 		{ .format = DRM_FORMAT_RGB888_A8,	.depth = 32, .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
 		{ .format = DRM_FORMAT_BGR888_A8,	.depth = 32, .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
 		{ .format = DRM_FORMAT_XRGB8888_A8,	.depth = 32, .num_planes = 2, .cpp = { 4, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 93a341d..d323c73 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -144,6 +144,17 @@ extern "C" {
 #define DRM_FORMAT_RGBA1010102	fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
 #define DRM_FORMAT_BGRA1010102	fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
 
+/*
+ * Floating point 64bpp RGB
+ * IEEE 754-2008 binary16 half-precision float
+ * [15:0] sign:exponent:mantissa 1:5:10
+ */
+#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
+#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
+
+#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
+#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
+
 /* packed YCbCr */
 #define DRM_FORMAT_YUYV		fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
 #define DRM_FORMAT_YVYU		fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
-- 
2.7.4

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[PATCH v5 2/3] drm/i915: Refactor icl_is_hdr_plane

[Kevin Strasser]

Change the api in order to enable callers that can't supply a valid
intel_plane pointer, as would be the case prior to calling
drm_universal_plane_init.

v4:
- Rename variables and move a declaration (Ville)

Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_atomic.c  | 3 ++-
 drivers/gpu/drm/i915/intel_display.c | 7 +++++--
 drivers/gpu/drm/i915/intel_drv.h     | 7 ++++---
 drivers/gpu/drm/i915/intel_sprite.c  | 6 +++---
 4 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index 7cf9290..3a0d72b 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -234,10 +234,11 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
 	if (plane_state && plane_state->base.fb &&
 	    plane_state->base.fb->format->is_yuv &&
 	    plane_state->base.fb->format->num_planes > 1) {
+		struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 		if (IS_GEN(dev_priv, 9) &&
 		    !IS_GEMINILAKE(dev_priv)) {
 			mode = SKL_PS_SCALER_MODE_NV12;
-		} else if (icl_is_hdr_plane(to_intel_plane(plane_state->base.plane))) {
+		} else if (icl_is_hdr_plane(dev_priv, plane->id)) {
 			/*
 			 * On gen11+'s HDR planes we only use the scaler for
 			 * scaling. They have a dedicated chroma upsampler, so
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5b8dabd..68f7dae 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3779,6 +3779,8 @@ u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
 			const struct intel_plane_state *plane_state)
 {
+	struct drm_i915_private *dev_priv =
+		to_i915(plane_state->base.plane->dev);
 	const struct drm_framebuffer *fb = plane_state->base.fb;
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	u32 plane_color_ctl = 0;
@@ -3786,7 +3788,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
 	plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
 	plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
 
-	if (fb->format->is_yuv && !icl_is_hdr_plane(plane)) {
+	if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
 		if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
 			plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
 		else
@@ -5102,13 +5104,14 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 {
 	struct intel_plane *intel_plane =
 		to_intel_plane(plane_state->base.plane);
+	struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
 	struct drm_framebuffer *fb = plane_state->base.fb;
 	int ret;
 	bool force_detach = !fb || !plane_state->base.visible;
 	bool need_scaler = false;
 
 	/* Pre-gen11 and SDR planes always need a scaler for planar formats. */
-	if (!icl_is_hdr_plane(intel_plane) &&
+	if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
 	    fb && fb->format->format == DRM_FORMAT_NV12)
 		need_scaler = true;
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5eb0b66..1aa1d7b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2331,12 +2331,13 @@ static inline bool icl_is_nv12_y_plane(enum plane_id id)
 	return false;
 }
 
-static inline bool icl_is_hdr_plane(struct intel_plane *plane)
+static inline bool icl_is_hdr_plane(struct drm_i915_private *dev_priv,
+				    enum plane_id plane_id)
 {
-	if (INTEL_GEN(to_i915(plane->base.dev)) < 11)
+	if (INTEL_GEN(dev_priv) < 11)
 		return false;
 
-	return plane->id < PLANE_SPRITE2;
+	return plane_id < PLANE_SPRITE2;
 }
 
 /* intel_tv.c */
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 6103986..9da8d27 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -336,7 +336,7 @@ skl_program_scaler(struct intel_plane *plane,
 
 	/* TODO: handle sub-pixel coordinates */
 	if (plane_state->base.fb->format->format == DRM_FORMAT_NV12 &&
-	    !icl_is_hdr_plane(plane)) {
+	    !icl_is_hdr_plane(dev_priv, plane->id)) {
 		y_hphase = skl_scaler_calc_phase(1, hscale, false);
 		y_vphase = skl_scaler_calc_phase(1, vscale, false);
 
@@ -518,7 +518,7 @@ skl_program_plane(struct intel_plane *plane,
 	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
 		      (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
 
-	if (icl_is_hdr_plane(plane)) {
+	if (icl_is_hdr_plane(dev_priv, plane_id)) {
 		u32 cus_ctl = 0;
 
 		if (linked) {
@@ -542,7 +542,7 @@ skl_program_plane(struct intel_plane *plane,
 	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
 
-	if (fb->format->is_yuv && icl_is_hdr_plane(plane))
+	if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
 		icl_program_input_csc(plane, crtc_state, plane_state);
 
 	skl_write_plane_wm(plane, crtc_state);
-- 
2.7.4

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[PATCH v5 3/3] drm/i915/icl: Implement half float formats

[Kevin Strasser]

64 bpp half float formats are supported on hdr planes only and are subject
to the following restrictions:
  * 90/270 rotation not supported
  * Yf Tiling not supported
  * Frame Buffer Compression not supported
  * Color Keying not supported

v2:
- Drop handling pixel normalize register
- Don't use icl_is_hdr_plane too early

v3:
- Use refactored icl_is_hdr_plane (Ville)
- Use u32 instead of uint32_t (Ville)

Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 22 ++++++++++++
 drivers/gpu/drm/i915/intel_sprite.c  | 67 ++++++++++++++++++++++++++++++++----
 2 files changed, 83 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 68f7dae..2044d78 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2677,6 +2677,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
 		return DRM_FORMAT_RGB565;
 	case PLANE_CTL_FORMAT_NV12:
 		return DRM_FORMAT_NV12;
+	case PLANE_CTL_FORMAT_XRGB_16161616F:
+		if (rgb_order) {
+			if (alpha)
+				return DRM_FORMAT_ABGR16161616F;
+			else
+				return DRM_FORMAT_XBGR16161616F;
+		} else {
+			if (alpha)
+				return DRM_FORMAT_ARGB16161616F;
+			else
+				return DRM_FORMAT_XRGB16161616F;
+		}
 	default:
 	case PLANE_CTL_FORMAT_XRGB_8888:
 		if (rgb_order) {
@@ -3601,6 +3613,12 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
 		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
 	case DRM_FORMAT_NV12:
 		return PLANE_CTL_FORMAT_NV12;
+	case DRM_FORMAT_XBGR16161616F:
+	case DRM_FORMAT_ABGR16161616F:
+		return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
+	case DRM_FORMAT_XRGB16161616F:
+	case DRM_FORMAT_ARGB16161616F:
+		return PLANE_CTL_FORMAT_XRGB_16161616F;
 	default:
 		MISSING_CASE(pixel_format);
 	}
@@ -5149,6 +5167,10 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
 	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_XBGR16161616F:
+	case DRM_FORMAT_ABGR16161616F:
+	case DRM_FORMAT_XRGB16161616F:
+	case DRM_FORMAT_ARGB16161616F:
 		break;
 	default:
 		DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 9da8d27..178dbaa 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1495,8 +1495,6 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 		/*
 		 * 90/270 is not allowed with RGB64 16:16:16:16 and
 		 * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
-		 * TBD: Add RGB64 case once its added in supported format
-		 * list.
 		 */
 		switch (fb->format->format) {
 		case DRM_FORMAT_RGB565:
@@ -1504,6 +1502,10 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 				break;
 			/* fall through */
 		case DRM_FORMAT_C8:
+		case DRM_FORMAT_XRGB16161616F:
+		case DRM_FORMAT_XBGR16161616F:
+		case DRM_FORMAT_ARGB16161616F:
+		case DRM_FORMAT_ABGR16161616F:
 			DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
 				      drm_get_format_name(fb->format->format,
 							  &format_name));
@@ -1819,6 +1821,45 @@ static const u32 skl_planar_formats[] = {
 	DRM_FORMAT_NV12,
 };
 
+static const u32 icl_hdr_plane_formats[] = {
+	DRM_FORMAT_C8,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_XRGB2101010,
+	DRM_FORMAT_XBGR2101010,
+	DRM_FORMAT_XRGB16161616F,
+	DRM_FORMAT_XBGR16161616F,
+	DRM_FORMAT_ARGB16161616F,
+	DRM_FORMAT_ABGR16161616F,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+};
+
+static const u32 icl_hdr_planar_formats[] = {
+	DRM_FORMAT_C8,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_XRGB2101010,
+	DRM_FORMAT_XBGR2101010,
+	DRM_FORMAT_XRGB16161616F,
+	DRM_FORMAT_XBGR16161616F,
+	DRM_FORMAT_ARGB16161616F,
+	DRM_FORMAT_ABGR16161616F,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+	DRM_FORMAT_NV12,
+};
+
 static const u64 skl_plane_format_modifiers_noccs[] = {
 	I915_FORMAT_MOD_Yf_TILED,
 	I915_FORMAT_MOD_Y_TILED,
@@ -1962,6 +2003,10 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 			return true;
 		/* fall through */
 	case DRM_FORMAT_C8:
+	case DRM_FORMAT_XBGR16161616F:
+	case DRM_FORMAT_ABGR16161616F:
+	case DRM_FORMAT_XRGB16161616F:
+	case DRM_FORMAT_ARGB16161616F:
 		if (modifier == DRM_FORMAT_MOD_LINEAR ||
 		    modifier == I915_FORMAT_MOD_X_TILED ||
 		    modifier == I915_FORMAT_MOD_Y_TILED)
@@ -2098,11 +2143,21 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 		plane->update_slave = icl_update_slave;
 
 	if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
-		formats = skl_planar_formats;
-		num_formats = ARRAY_SIZE(skl_planar_formats);
+		if (icl_is_hdr_plane(dev_priv, plane_id)) {
+			formats = icl_hdr_planar_formats;
+			num_formats = ARRAY_SIZE(icl_hdr_planar_formats);
+		} else {
+			formats = skl_planar_formats;
+			num_formats = ARRAY_SIZE(skl_planar_formats);
+		}
 	} else {
-		formats = skl_plane_formats;
-		num_formats = ARRAY_SIZE(skl_plane_formats);
+		if (icl_is_hdr_plane(dev_priv, plane_id)) {
+			formats = icl_hdr_plane_formats;
+			num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
+		} else {
+			formats = skl_plane_formats;
+			num_formats = ARRAY_SIZE(skl_plane_formats);
+		}
 	}
 
 	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
-- 
2.7.4

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✗ Fi.CI.CHECKPATCH: warning for Support 64 bpp half float formats (rev6)

[Patchwork]

== Series Details ==

Series: Support 64 bpp half float formats (rev6)
URL   : https://patchwork.freedesktop.org/series/53212/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
adafd20058ef drm/fourcc: Add 64 bpp half float formats
-:44: WARNING:LONG_LINE: line over 100 characters
#44: FILE: drivers/gpu/drm/drm_fourcc.c:201:
+		{ .format = DRM_FORMAT_XRGB16161616F,	.depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },

-:45: WARNING:LONG_LINE: line over 100 characters
#45: FILE: drivers/gpu/drm/drm_fourcc.c:202:
+		{ .format = DRM_FORMAT_XBGR16161616F,	.depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },

-:46: WARNING:LONG_LINE: line over 100 characters
#46: FILE: drivers/gpu/drm/drm_fourcc.c:203:
+		{ .format = DRM_FORMAT_ARGB16161616F,	.depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

-:47: WARNING:LONG_LINE: line over 100 characters
#47: FILE: drivers/gpu/drm/drm_fourcc.c:204:
+		{ .format = DRM_FORMAT_ABGR16161616F,	.depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

-:64: WARNING:LONG_LINE_COMMENT: line over 100 characters
#64: FILE: include/uapi/drm/drm_fourcc.h:152:
+#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */

-:65: WARNING:LONG_LINE_COMMENT: line over 100 characters
#65: FILE: include/uapi/drm/drm_fourcc.h:153:
+#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */

-:67: WARNING:LONG_LINE_COMMENT: line over 100 characters
#67: FILE: include/uapi/drm/drm_fourcc.h:155:
+#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */

-:68: WARNING:LONG_LINE_COMMENT: line over 100 characters
#68: FILE: include/uapi/drm/drm_fourcc.h:156:
+#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */

total: 0 errors, 8 warnings, 0 checks, 27 lines checked
bcef4fb5cdbc drm/i915: Refactor icl_is_hdr_plane
234a25ce4937 drm/i915/icl: Implement half float formats

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✓ Fi.CI.BAT: success for Support 64 bpp half float formats (rev6)

[Patchwork]

== Series Details ==

Series: Support 64 bpp half float formats (rev6)
URL   : https://patchwork.freedesktop.org/series/53212/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5570 -> Patchwork_12184
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/53212/revisions/6/mbox/

Known issues
------------

  Here are the changes found in Patchwork_12184 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_flip@basic-flip-vs-modeset:
    - fi-skl-6700hq:      PASS -> DMESG-WARN [fdo#105998]

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - fi-byt-clapper:     PASS -> FAIL [fdo#103191] / [fdo#107362]

  
#### Possible fixes ####

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - fi-blb-e6850:       INCOMPLETE [fdo#107718] -> PASS

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - fi-hsw-4770:        {SKIP} [fdo#109271] -> PASS +4

  * igt@pm_rpm@basic-rte:
    - {fi-icl-u2}:        DMESG-WARN [fdo#108654] -> PASS

  
#### Warnings ####

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-7567u:       DMESG-FAIL [fdo#105079] -> DMESG-WARN [fdo#103558] / [fdo#105079] / [fdo#105602]

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
  [fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#105998]: https://bugs.freedesktop.org/show_bug.cgi?id=105998
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315


Participating hosts (49 -> 43)
------------------------------

  Missing    (6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-gdg-551 fi-icl-y fi-bdw-samus 


Build changes
-------------

    * Linux: CI_DRM_5570 -> Patchwork_12184

  CI_DRM_5570: 6d060d6f4f68ddaa40ef2102f3f654f8bfff5bca @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4815: 947301563259726b65ce47d3a3fe37931ed42efe @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12184: 234a25ce4937f0b373fa1ec3f4f3d42e1d4a7f29 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

234a25ce4937 drm/i915/icl: Implement half float formats
bcef4fb5cdbc drm/i915: Refactor icl_is_hdr_plane
adafd20058ef drm/fourcc: Add 64 bpp half float formats

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12184/
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✓ Fi.CI.IGT: success for Support 64 bpp half float formats (rev6)

[Patchwork]

== Series Details ==

Series: Support 64 bpp half float formats (rev6)
URL   : https://patchwork.freedesktop.org/series/53212/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5570_full -> Patchwork_12184_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_12184_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
    - shard-snb:          NOTRUN -> DMESG-WARN [fdo#107956]

  * igt@kms_cursor_crc@cursor-64x21-random:
    - shard-apl:          PASS -> FAIL [fdo#103232] +4

  * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
    - shard-glk:          PASS -> FAIL [fdo#105454] / [fdo#106509]

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-glk:          PASS -> FAIL [fdo#105363]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-apl:          PASS -> FAIL [fdo#103167] +1

  * igt@kms_frontbuffer_tracking@fbc-farfromfence:
    - shard-snb:          NOTRUN -> INCOMPLETE [fdo#105411]

  * igt@kms_plane@plane-position-covered-pipe-a-planes:
    - shard-glk:          PASS -> FAIL [fdo#103166]

  * igt@kms_plane@plane-position-covered-pipe-c-planes:
    - shard-apl:          PASS -> FAIL [fdo#103166] +3

  * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
    - shard-apl:          PASS -> FAIL [fdo#108145]

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
    - shard-kbl:          NOTRUN -> FAIL [fdo#103166]

  * igt@kms_setmode@basic:
    - shard-hsw:          PASS -> FAIL [fdo#99912]

  
#### Possible fixes ####

  * igt@gem_mmap_gtt@basic-write:
    - shard-snb:          INCOMPLETE [fdo#105411] -> PASS

  * igt@kms_cursor_crc@cursor-128x128-random:
    - shard-apl:          FAIL [fdo#103232] -> PASS +1

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
    - shard-apl:          FAIL [fdo#103167] -> PASS +1

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-glk:          FAIL [fdo#103167] -> PASS +4

  * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
    - shard-apl:          FAIL [fdo#108145] -> PASS

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
    - shard-glk:          FAIL [fdo#103166] -> PASS
    - shard-apl:          FAIL [fdo#103166] -> PASS

  * igt@sw_sync@sync_busy_fork:
    - shard-apl:          INCOMPLETE [fdo#103927] -> PASS

  
#### Warnings ####

  * igt@i915_suspend@shrink:
    - shard-snb:          INCOMPLETE [fdo#105411] / [fdo#106886] -> DMESG-WARN [fdo#109244]

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#105454]: https://bugs.freedesktop.org/show_bug.cgi?id=105454
  [fdo#106509]: https://bugs.freedesktop.org/show_bug.cgi?id=106509
  [fdo#106886]: https://bugs.freedesktop.org/show_bug.cgi?id=106886
  [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109244]: https://bugs.freedesktop.org/show_bug.cgi?id=109244
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109373]: https://bugs.freedesktop.org/show_bug.cgi?id=109373
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
  [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321


Participating hosts (7 -> 5)
------------------------------

  Missing    (2): shard-skl shard-iclb 


Build changes
-------------

    * Linux: CI_DRM_5570 -> Patchwork_12184

  CI_DRM_5570: 6d060d6f4f68ddaa40ef2102f3f654f8bfff5bca @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4815: 947301563259726b65ce47d3a3fe37931ed42efe @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12184: 234a25ce4937f0b373fa1ec3f4f3d42e1d4a7f29 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12184/
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Re: [PATCH v5 0/3] Support 64 bpp half float formats

[Ville Syrjälä via dri-devel]

On Fri, Feb 08, 2019 at 01:49:40PM -0800, Kevin Strasser wrote:
> This series defines new formats and adds implementation to the i915 driver.
> Since posting v1 I have removed the pixel normalize property, as it's not needed
> for basic functionality. Also, I have been working on adding support to
> userspace, but we can't land any patches until drm_fourcc.h has been updated
> here.
> 
> I have submitted a series to Mesa to make use of the RGBA ordered formats:
>   https://patchwork.freedesktop.org/series/54759/
> 
> My igt branch is reworked to drop usage of pixel normalize and includes use
> of f16c intrinsics to speed up conversion:
>   https://gitlab.freedesktop.org/strassek/igt-gpu-tools/commits/fp16

Was that posted to the ml? I can't seem to find it.

Anyways, a quick look at the web thing tells me this predates
Maarten's cairo float stuff. I believe that has now landed so you
should probably switch to using that instead of rendering at 8bpc.

> 
> I also have a libdrm branch with fp16 coverage added to modetest:
>   https://gitlab.freedesktop.org/strassek/drm/commits/fp16
> 
> To serve as a smoke test of the whole stack I have a modified version of
> kmscube:
>   https://gitlab.freedesktop.org/strassek/kmscube/commits/fp16
> 
> Kevin Strasser (3):
>   drm/fourcc: Add 64 bpp half float formats
>   drm/i915: Refactor icl_is_hdr_plane
>   drm/i915/icl: Implement half float formats
> 
>  drivers/gpu/drm/drm_fourcc.c         |  4 ++
>  drivers/gpu/drm/i915/intel_atomic.c  |  3 +-
>  drivers/gpu/drm/i915/intel_display.c | 29 +++++++++++++-
>  drivers/gpu/drm/i915/intel_drv.h     |  7 ++--
>  drivers/gpu/drm/i915/intel_sprite.c  | 73 +++++++++++++++++++++++++++++++-----
>  include/uapi/drm/drm_fourcc.h        | 11 ++++++
>  6 files changed, 112 insertions(+), 15 deletions(-)
> 
> -- 
> 2.7.4

-- 
Ville Syrjälä
Intel
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Re: [PATCH v5 0/3] Support 64 bpp half float formats

[Maarten Lankhorst]

Op 13-02-2019 om 16:53 schreef Ville Syrjälä:
> On Fri, Feb 08, 2019 at 01:49:40PM -0800, Kevin Strasser wrote:
>> This series defines new formats and adds implementation to the i915 driver.
>> Since posting v1 I have removed the pixel normalize property, as it's not needed
>> for basic functionality. Also, I have been working on adding support to
>> userspace, but we can't land any patches until drm_fourcc.h has been updated
>> here.
>>
>> I have submitted a series to Mesa to make use of the RGBA ordered formats:
>>   https://patchwork.freedesktop.org/series/54759/
>>
>> My igt branch is reworked to drop usage of pixel normalize and includes use
>> of f16c intrinsics to speed up conversion:
>>   https://gitlab.freedesktop.org/strassek/igt-gpu-tools/commits/fp16
> Was that posted to the ml? I can't seem to find it.
>
> Anyways, a quick look at the web thing tells me this predates
> Maarten's cairo float stuff. I believe that has now landed so you
> should probably switch to using that instead of rendering at 8bpc.

Yes, it's now in upstream igt. :)

RGB96F is just a float[3] = { r, g, b }; RGBA128F is the same with the alpha channel at the end,

should be possible to convert to half float with the right changes to the conversion function.

~Maarten

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Re: [PATCH v5 0/3] Support 64 bpp half float formats

[Strasser, Kevin]

Maarten Lankhorst wrote:
> Op 13-02-2019 om 16:53 schreef Ville Syrjälä:
> > On Fri, Feb 08, 2019 at 01:49:40PM -0800, Kevin Strasser wrote:
> >> This series defines new formats and adds implementation to the i915 driver.
> >> Since posting v1 I have removed the pixel normalize property, as it's not
> >> needed
> >> for basic functionality. Also, I have been working on adding support to
> >> userspace, but we can't land any patches until drm_fourcc.h has been updated
> >> here.
> >>
> >> I have submitted a series to Mesa to make use of the RGBA ordered formats:
> >>   https://patchwork.freedesktop.org/series/54759/
> >>
> >> My igt branch is reworked to drop usage of pixel normalize and includes use
> >> of f16c intrinsics to speed up conversion:
> >>   https://gitlab.freedesktop.org/strassek/igt-gpu-tools/commits/fp16
> > Was that posted to the ml? I can't seem to find it.
> >
> > Anyways, a quick look at the web thing tells me this predates
> > Maarten's cairo float stuff. I believe that has now landed so you
> > should probably switch to using that instead of rendering at 8bpc.
>
> Yes, it's now in upstream igt. :)
>
> RGB96F is just a float[3] = { r, g, b }; RGBA128F is the same with the alpha
> channel at the end,
>
> should be possible to convert to half float with the right changes to the
> conversion function.

I've updated my branch to use the new float formats. Here is a link to the relevant commit:
https://gitlab.freedesktop.org/strassek/igt-gpu-tools/commit/11d14a37859e9dfd43755feb631e4b530d666392

Thanks,
Kevin
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Re: [PATCH v5 0/3] Support 64 bpp half float formats

[Adam Jackson]

On Fri, 2019-02-08 at 13:49 -0800, Kevin Strasser wrote:
> This series defines new formats and adds implementation to the i915 driver.
> Since posting v1 I have removed the pixel normalize property, as it's not needed
> for basic functionality. Also, I have been working on adding support to
> userspace, but we can't land any patches until drm_fourcc.h has been updated
> here.

Series is:

Reviewed-by: Adam Jackson <ajax@redhat.com>

- ajax

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