From: Andrew Lunn <andrew@lunn.ch>
To: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Cc: "Florian Fainelli" <f.fainelli@gmail.com>,
"Heiner Kallweit" <hkallweit1@gmail.com>,
netdev@vger.kernel.org,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Mylène Josserand" <mylene.josserand@bootlin.com>
Subject: Re: Handling an Extra Signal at PHY Reset
Date: Tue, 19 Feb 2019 16:40:52 +0100 [thread overview]
Message-ID: <20190219154052.GC1981@lunn.ch> (raw)
In-Reply-To: <5a23b65bb9209cab5616ea06cbbb9c86dcaad1df.camel@bootlin.com>
> I think the reason why we need to deal with the CONFIG pin is more
> about setting the correct I/O voltage than the PHY address (it just
> happens that the CONFIG pin configures both at once).
Hi Paul
I don't have the datasheet...
What I/O voltages are we talking about? Is the device addressable over
the MDIO bus without this configuration? Can the voltages be
configured via register writes during probe? I assume not, or you
would be doing that...
Andrew
next prev parent reply other threads:[~2019-02-19 15:40 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-19 9:14 Handling an Extra Signal at PHY Reset Paul Kocialkowski
2019-02-19 9:36 ` Thomas Petazzoni
2019-02-19 12:53 ` Paul Kocialkowski
2019-02-19 13:36 ` Andrew Lunn
2019-02-19 15:06 ` Paul Kocialkowski
2019-02-19 15:40 ` Andrew Lunn [this message]
2019-02-20 8:06 ` Thomas Petazzoni
2019-02-19 16:07 ` Florian Fainelli
2019-02-21 9:05 ` Paul Kocialkowski
2019-02-21 1:49 ` Andrew Lunn
2019-02-21 8:50 ` Paul Kocialkowski
2019-02-21 14:04 ` Andrew Lunn
2019-02-27 8:19 ` Paul Kocialkowski
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