Re: [PATCH v6] powerpc/64s: reimplement book3s idle code in C

[Paul Mackerras <paulus@ozlabs.org>]

On Tue, Feb 19, 2019 at 02:13:51PM +1000, Nicholas Piggin wrote:
> Paul Mackerras's on February 18, 2019 9:06 am:
> > On Sat, Oct 13, 2018 at 10:04:09PM +1000, Nicholas Piggin wrote:
> >> Reimplement Book3S idle code in C, moving POWER7/8/9 implementation
> >> speific HV idle code to the powernv platform code.
> >> 
> > 
> > [...]
> > 
> >> @@ -2760,21 +2744,47 @@ BEGIN_FTR_SECTION
> >>  	li	r4, LPCR_PECE_HVEE@higher
> >>  	sldi	r4, r4, 32
> >>  	or	r5, r5, r4
> >> -END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
> >> +FTR_SECTION_ELSE
> >> +	li	r3, PNV_THREAD_NAP
> >> +ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
> >>  	mtspr	SPRN_LPCR,r5
> >>  	isync
> >> -	li	r0, 0
> >> -	std	r0, HSTATE_SCRATCH0(r13)
> >> -	ptesync
> >> -	ld	r0, HSTATE_SCRATCH0(r13)
> >> -1:	cmpd	r0, r0
> >> -	bne	1b
> >> +
> >> +	mr	r0, r1
> >> +	ld	r1, PACAEMERGSP(r13)
> >> +	subi	r1, r1, STACK_FRAME_OVERHEAD
> >> +	std	r0, 0(r1)
> >> +	ld	r0, PACAR1(r13)
> >> +	std	r0, 8(r1)
> > 
> > This bit seems wrong to me.  If this is a secondary thread on POWER8,
> > we were already on the emergency stack, and now we've reset r1 back to
> > the top of the emergency stack and we're overwriting it.
> 
> I'll have to find some time to take another look at this stuff. The KVM
> stuff was a bit hasty.
> 
> > I wonder why you didn't see secondary threads going off into lala land
> > in your tests?
> 
> It must have been because I wasn't testing the guest SMT properly 
> because I did get it to break trivially sometime after posting this 
> patch out. So we were on the emergency stack here, that should make
> things easier, that may be what's wrong.

In fact I don't see why you need to load up a new stack here at all;
you could just use whatever stack we're currently on AFAICS.

Paul.