* [PATCH 0/6] SPD EEPROM improvements
@ 2019-03-04 11:38 Sascha Hauer
2019-03-04 11:38 ` [PATCH 1/6] crc: import crc_itu_t() from kernel Sascha Hauer
` (5 more replies)
0 siblings, 6 replies; 12+ messages in thread
From: Sascha Hauer @ 2019-03-04 11:38 UTC (permalink / raw)
To: Barebox List
This series adds the SPD EEPROM definitions for DDR4, also we get a
function to read SPD EEPROMs in the PBL, using the early i.MX I2C driver
added in another series in "[PATCH 10/10] i2c: i.MX: Add early driver for use in PBL"
Sascha
Sascha Hauer (6):
crc: import crc_itu_t() from kernel
crc: Add PBL variant for crc_itu_t()
ddr_spd: Update from U-Boot
ddr_spd: Add function to read eeprom
ddr_spd: provide common SPD type
ddr_spd: Enable in PBL
arch/ppc/ddr-8xxx/ddr2_dimm_params.c | 6 +-
arch/ppc/ddr-8xxx/ddr3_dimm_params.c | 10 +-
arch/ppc/include/asm/fsl_ddr_sdram.h | 4 +-
commands/Kconfig | 2 +-
common/Kconfig | 2 +-
common/Makefile | 2 +-
common/ddr_spd.c | 203 +++++++-
common/ratp/Kconfig | 2 +-
crypto/Kconfig | 3 +-
crypto/Makefile | 2 +-
crypto/crc-itu-t.c | 60 +++
crypto/crc16.c | 103 ----
drivers/mci/Kconfig | 2 +-
drivers/mci/mci_spi.c | 4 +-
include/crc.h | 32 +-
include/ddr_spd.h | 695 ++++++++++++++++++++-------
lib/Kconfig | 4 +-
lib/ratp.c | 4 +-
lib/xymodem.c | 2 +-
19 files changed, 805 insertions(+), 337 deletions(-)
create mode 100644 crypto/crc-itu-t.c
delete mode 100644 crypto/crc16.c
--
2.20.1
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^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 1/6] crc: import crc_itu_t() from kernel 2019-03-04 11:38 [PATCH 0/6] SPD EEPROM improvements Sascha Hauer @ 2019-03-04 11:38 ` Sascha Hauer 2019-03-04 11:50 ` Sam Ravnborg 2019-03-04 11:38 ` [PATCH 2/6] crc: Add PBL variant for crc_itu_t() Sascha Hauer ` (4 subsequent siblings) 5 siblings, 1 reply; 12+ messages in thread From: Sascha Hauer @ 2019-03-04 11:38 UTC (permalink / raw) To: Barebox List Out cyc_crc16() function is the same function as crc_itu_t() in the Linux kernel. Import and use crc_itu_t() from the Kernel for consistency. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- commands/Kconfig | 2 +- common/Kconfig | 2 +- common/ddr_spd.c | 2 +- common/ratp/Kconfig | 2 +- crypto/Kconfig | 3 +- crypto/Makefile | 2 +- crypto/crc-itu-t.c | 60 ++++++++++++++++++++++++ crypto/crc16.c | 103 ------------------------------------------ drivers/mci/Kconfig | 2 +- drivers/mci/mci_spi.c | 4 +- include/crc.h | 16 ++++++- lib/Kconfig | 4 +- lib/ratp.c | 4 +- lib/xymodem.c | 2 +- 14 files changed, 88 insertions(+), 120 deletions(-) create mode 100644 crypto/crc-itu-t.c delete mode 100644 crypto/crc16.c diff --git a/commands/Kconfig b/commands/Kconfig index c14332c9d7..4f5d84ac18 100644 --- a/commands/Kconfig +++ b/commands/Kconfig @@ -394,7 +394,7 @@ config CMD_GO config CMD_LOADB depends on CONSOLE_FULL - select CRC16 + select CRC_ITU_T tristate prompt "loadb" help diff --git a/common/Kconfig b/common/Kconfig index 21b33f06f7..749bdcf271 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -1229,4 +1229,4 @@ config HAS_DEBUG_LL config DDR_SPD bool - select CRC16 + select CRC_ITU_T diff --git a/common/ddr_spd.c b/common/ddr_spd.c index 7e2945ed96..2110972f5b 100644 --- a/common/ddr_spd.c +++ b/common/ddr_spd.c @@ -51,7 +51,7 @@ uint32_t ddr3_spd_checksum_pass(const struct ddr3_spd_eeprom_s *spd) */ len = !(spd->info_size_crc & 0x80) ? 126 : 117; - csum16 = cyg_crc16((char *)spd, len); + csum16 = crc_itu_t(0, (char *)spd, len); crc_lsb = (char) (csum16 & 0xff); crc_msb = (char) (csum16 >> 8); diff --git a/common/ratp/Kconfig b/common/ratp/Kconfig index 25c931b978..30462c6c97 100644 --- a/common/ratp/Kconfig +++ b/common/ratp/Kconfig @@ -2,7 +2,7 @@ config CONSOLE_RATP bool select RATP - select CRC16 + select CRC_ITU_T select POLLER select CMDLINE_EDITING depends on CONSOLE_FULL diff --git a/crypto/Kconfig b/crypto/Kconfig index 6d65c24d4f..c06d3c054e 100644 --- a/crypto/Kconfig +++ b/crypto/Kconfig @@ -3,8 +3,7 @@ menu "Crypto support" config CRC32 bool -config CRC16 - default y +config CRC_ITU_T bool config CRC7 diff --git a/crypto/Makefile b/crypto/Makefile index a7240d1d6e..0014b0f4ce 100644 --- a/crypto/Makefile +++ b/crypto/Makefile @@ -1,5 +1,5 @@ obj-$(CONFIG_CRC32) += crc32.o -obj-$(CONFIG_CRC16) += crc16.o +obj-$(CONFIG_CRC_ITU_T) += crc-itu-t.o obj-$(CONFIG_CRC7) += crc7.o obj-$(CONFIG_DIGEST) += digest.o obj-$(CONFIG_DIGEST_CRC32_GENERIC) += crc32_digest.o diff --git a/crypto/crc-itu-t.c b/crypto/crc-itu-t.c new file mode 100644 index 0000000000..64bccfb742 --- /dev/null +++ b/crypto/crc-itu-t.c @@ -0,0 +1,60 @@ +/* + * crc-itu-t.c + * + * This source code is licensed under the GNU General Public License, + * Version 2. See the file COPYING for more details. + */ + +#include <crc.h> + +/** CRC table for the CRC ITU-T V.41 0x1021 (x^16 + x^12 + x^15 + 1) */ +const u16 crc_itu_t_table[256] = { + 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, + 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, + 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, + 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, + 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, + 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, + 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, + 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, + 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, + 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, + 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, + 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, + 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, + 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, + 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, + 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, + 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0 +}; + +/** + * crc_itu_t - Compute the CRC-ITU-T for the data buffer + * + * @crc: previous CRC value + * @buffer: data pointer + * @len: number of bytes in the buffer + * + * Returns the updated CRC value + */ +u16 crc_itu_t(u16 crc, const u8 *buffer, size_t len) +{ + while (len--) + crc = crc_itu_t_byte(crc, *buffer++); + return crc; +} diff --git a/crypto/crc16.c b/crypto/crc16.c deleted file mode 100644 index 0b08e9ccde..0000000000 --- a/crypto/crc16.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - *========================================================================== - * - * crc16.c - * - * 16 bit CRC with polynomial x^16+x^12+x^5+1 - * - *========================================================================== - *####ECOSGPLCOPYRIGHTBEGIN#### - * ------------------------------------------- - * This file is part of eCos, the Embedded Configurable Operating System. - * Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. - * Copyright (C) 2002 Gary Thomas - * - * eCos is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 or (at your option) any later version. - * - * eCos is distributed in the hope that it will be useful, but WITHOUT ANY - * WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * As a special exception, if other files instantiate templates or use macros - * or inline functions from this file, or you compile this file and link it - * with other works to produce a work based on this file, this file does not - * by itself cause the resulting work to be covered by the GNU General Public - * License. However the source code for this file must still be made available - * in accordance with section (3) of the GNU General Public License. - * - * This exception does not invalidate any other reasons why a work based on - * this file might be covered by the GNU General Public License. - * - * Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. - * at http: *sources.redhat.com/ecos/ecos-license/ - * ------------------------------------------- - *####ECOSGPLCOPYRIGHTEND#### - *========================================================================== - *#####DESCRIPTIONBEGIN#### - * - * Author(s): gthomas - * Contributors: gthomas,asl - * Date: 2001-01-31 - * Purpose: - * Description: - * - * This code is part of eCos (tm). - * - *####DESCRIPTIONEND#### - * - *========================================================================== - */ - -#include "crc.h" - -/* Table of CRC constants - implements x^16+x^12+x^5+1 */ -static const uint16_t crc16_tab[] = { - 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, - 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, - 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, - 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, - 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, - 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, - 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, - 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, - 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, - 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, - 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, - 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, - 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, - 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, - 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, - 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, - 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, - 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, - 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, - 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, - 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, - 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, - 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, - 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, - 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, - 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, - 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, - 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, - 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, - 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, - 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, - 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0, -}; - -uint16_t -cyg_crc16(const unsigned char *buf, int len) -{ - int i; - uint16_t cksum; - - cksum = 0; - for (i = 0; i < len; i++) { - cksum = crc16_tab[((cksum>>8) ^ *buf++) & 0xFF] ^ (cksum << 8); - } - return cksum; -} diff --git a/drivers/mci/Kconfig b/drivers/mci/Kconfig index 2075151d67..397dcf1377 100644 --- a/drivers/mci/Kconfig +++ b/drivers/mci/Kconfig @@ -141,7 +141,7 @@ config MCI_SPI config MMC_SPI_CRC_ON bool "Enable CRC protection for transfers" - select CRC16 + select CRC_ITU_T depends on MCI_SPI help Enable CRC protection for transfers diff --git a/drivers/mci/mci_spi.c b/drivers/mci/mci_spi.c index 011947c8c1..42072da58a 100644 --- a/drivers/mci/mci_spi.c +++ b/drivers/mci/mci_spi.c @@ -166,7 +166,7 @@ static uint mmc_spi_readdata(struct mmc_spi_host *host, void *xbuf, mmc_spi_readbytes(host, bsize, buf); mmc_spi_readbytes(host, 2, &crc); #ifdef CONFIG_MMC_SPI_CRC_ON - if (be16_to_cpu(cyg_crc16(buf, bsize)) != crc) { + if (be16_to_cpu(crc_itu_t(0, buf, bsize)) != crc) { dev_dbg(host->dev, "%s: CRC error\n", __func__); r1 = R1_SPI_COM_CRC; break; @@ -197,7 +197,7 @@ static uint mmc_spi_writedata(struct mmc_spi_host *host, const void *xbuf, while (bcnt--) { #ifdef CONFIG_MMC_SPI_CRC_ON - crc = be16_to_cpu(cyg_crc16((u8 *)buf, bsize)); + crc = be16_to_cpu(crc_itu_t(0, (u8 *)buf, bsize)); #endif mmc_spi_writebytes(host, 2, tok); mmc_spi_writebytes(host, bsize, (void *)buf); diff --git a/include/crc.h b/include/crc.h index 847a0a4b64..317f6f5494 100644 --- a/include/crc.h +++ b/include/crc.h @@ -3,8 +3,20 @@ #include <linux/types.h> -/* 16 bit CRC with polynomial x^16+x^12+x^5+1 */ -extern uint16_t cyg_crc16(const unsigned char *s, int len); +/* + * Implements the standard CRC ITU-T V.41: + * Width 16 + * Poly 0x1021 (x^16 + x^12 + x^15 + 1) + * Init 0 + */ +extern u16 const crc_itu_t_table[256]; + +extern u16 crc_itu_t(u16 crc, const u8 *buffer, size_t len); + +static inline u16 crc_itu_t_byte(u16 crc, const u8 data) +{ + return (crc << 8) ^ crc_itu_t_table[((crc >> 8) ^ data) & 0xff]; +} uint32_t crc32(uint32_t, const void *, unsigned int); uint32_t crc32_no_comp(uint32_t, const void *, unsigned int); diff --git a/lib/Kconfig b/lib/Kconfig index e048aded8b..ecf578a34e 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -79,7 +79,7 @@ config QSORT config XYMODEM bool - select CRC16 + select CRC_ITU_T config LIBSCAN bool @@ -94,7 +94,7 @@ config STMP_DEVICE bool config RATP - select CRC16 + select CRC_ITU_T bool "RATP protocol support" help Reliable Asynchronous Transfer Protocol (RATP) is a protocol for reliably diff --git a/lib/ratp.c b/lib/ratp.c index 7801cae519..8167c5bd4c 100644 --- a/lib/ratp.c +++ b/lib/ratp.c @@ -315,7 +315,7 @@ static int ratp_recv_pkt_data(struct ratp_internal *ri, void *data, uint8_t len, return ret; } - crc_expect = cyg_crc16(data, len); + crc_expect = crc_itu_t(0, data, len); crc_read = get_unaligned_be16(data + len); @@ -419,7 +419,7 @@ static int ratp_send_next_data(struct ratp_internal *ri) pktlen = sizeof(struct ratp_header); if (len > 1) { pktlen += len + 2; - crc = cyg_crc16(data, len); + crc = crc_itu_t(0, data, len); put_unaligned_be16(crc, data + len); } else if (len == 1) { control |= RATP_CONTROL_SO; diff --git a/lib/xymodem.c b/lib/xymodem.c index 9e4ce58b60..136741ab4a 100644 --- a/lib/xymodem.c +++ b/lib/xymodem.c @@ -210,7 +210,7 @@ static int check_crc(unsigned char *buf, int len, int crc, int crc_mode) crc8 += buf[i]; return crc8 == crc ? 0 : -EBADMSG; case CRC_CRC16: - crc16 = cyg_crc16(buf, len); + crc16 = crc_itu_t(0, buf, len); xy_dbg("crc16: received = %x, calculated=%x\n", crc, crc16); return crc16 == crc ? 0 : -EBADMSG; case CRC_NONE: -- 2.20.1 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 1/6] crc: import crc_itu_t() from kernel 2019-03-04 11:38 ` [PATCH 1/6] crc: import crc_itu_t() from kernel Sascha Hauer @ 2019-03-04 11:50 ` Sam Ravnborg 2019-03-04 13:19 ` Sascha Hauer 0 siblings, 1 reply; 12+ messages in thread From: Sam Ravnborg @ 2019-03-04 11:50 UTC (permalink / raw) To: Sascha Hauer; +Cc: Barebox List On Mon, Mar 04, 2019 at 12:38:18PM +0100, Sascha Hauer wrote: > Out cyc_crc16() function is the same function as crc_itu_t() in the s/Out/barebox/ > Linux kernel. Import and use crc_itu_t() from the Kernel for > consistency. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sam _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/6] crc: import crc_itu_t() from kernel 2019-03-04 11:50 ` Sam Ravnborg @ 2019-03-04 13:19 ` Sascha Hauer 0 siblings, 0 replies; 12+ messages in thread From: Sascha Hauer @ 2019-03-04 13:19 UTC (permalink / raw) To: Sam Ravnborg; +Cc: Barebox List On Mon, Mar 04, 2019 at 12:50:06PM +0100, Sam Ravnborg wrote: > On Mon, Mar 04, 2019 at 12:38:18PM +0100, Sascha Hauer wrote: > > Out cyc_crc16() function is the same function as crc_itu_t() in the > s/Out/barebox/ Should read "Our". Thanks, fixed. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/6] crc: Add PBL variant for crc_itu_t() 2019-03-04 11:38 [PATCH 0/6] SPD EEPROM improvements Sascha Hauer 2019-03-04 11:38 ` [PATCH 1/6] crc: import crc_itu_t() from kernel Sascha Hauer @ 2019-03-04 11:38 ` Sascha Hauer 2019-03-04 11:38 ` [PATCH 3/6] ddr_spd: Update from U-Boot Sascha Hauer ` (3 subsequent siblings) 5 siblings, 0 replies; 12+ messages in thread From: Sascha Hauer @ 2019-03-04 11:38 UTC (permalink / raw) To: Barebox List Enable crc_itu_t() for PBL. For the PBL use the slower-but-smaller variant without table. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- crypto/Makefile | 2 +- include/crc.h | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/crypto/Makefile b/crypto/Makefile index 0014b0f4ce..3402f57255 100644 --- a/crypto/Makefile +++ b/crypto/Makefile @@ -1,5 +1,5 @@ obj-$(CONFIG_CRC32) += crc32.o -obj-$(CONFIG_CRC_ITU_T) += crc-itu-t.o +obj-pbl-$(CONFIG_CRC_ITU_T) += crc-itu-t.o obj-$(CONFIG_CRC7) += crc7.o obj-$(CONFIG_DIGEST) += digest.o obj-$(CONFIG_DIGEST_CRC32_GENERIC) += crc32_digest.o diff --git a/include/crc.h b/include/crc.h index 317f6f5494..a67388f732 100644 --- a/include/crc.h +++ b/include/crc.h @@ -13,10 +13,26 @@ extern u16 const crc_itu_t_table[256]; extern u16 crc_itu_t(u16 crc, const u8 *buffer, size_t len); +#ifdef __PBL__ +static inline u16 crc_itu_t_byte(u16 crc, const u8 data) +{ + int i; + + crc = crc ^ data << 8; + for (i = 0; i < 8; ++i) { + if (crc & 0x8000) + crc = crc << 1 ^ 0x1021; + else + crc = crc << 1; + } + return crc; +} +#else static inline u16 crc_itu_t_byte(u16 crc, const u8 data) { return (crc << 8) ^ crc_itu_t_table[((crc >> 8) ^ data) & 0xff]; } +#endif uint32_t crc32(uint32_t, const void *, unsigned int); uint32_t crc32_no_comp(uint32_t, const void *, unsigned int); -- 2.20.1 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/6] ddr_spd: Update from U-Boot 2019-03-04 11:38 [PATCH 0/6] SPD EEPROM improvements Sascha Hauer 2019-03-04 11:38 ` [PATCH 1/6] crc: import crc_itu_t() from kernel Sascha Hauer 2019-03-04 11:38 ` [PATCH 2/6] crc: Add PBL variant for crc_itu_t() Sascha Hauer @ 2019-03-04 11:38 ` Sascha Hauer 2019-03-04 11:38 ` [PATCH 4/6] ddr_spd: Add function to read eeprom Sascha Hauer ` (2 subsequent siblings) 5 siblings, 0 replies; 12+ messages in thread From: Sascha Hauer @ 2019-03-04 11:38 UTC (permalink / raw) To: Barebox List This updates the ddr_spd.h header file from U-Boot-2019.01 with some small changes: - typedefs are removed - "_s" suffix from struct types removed - remove unnecessary "extern" from function declarations Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- arch/ppc/ddr-8xxx/ddr2_dimm_params.c | 6 +- arch/ppc/ddr-8xxx/ddr3_dimm_params.c | 10 +- arch/ppc/include/asm/fsl_ddr_sdram.h | 4 +- common/ddr_spd.c | 122 ++++- include/ddr_spd.h | 679 +++++++++++++++++++-------- 5 files changed, 604 insertions(+), 217 deletions(-) diff --git a/arch/ppc/ddr-8xxx/ddr2_dimm_params.c b/arch/ppc/ddr-8xxx/ddr2_dimm_params.c index cc7f3fa6ba..22c05ca6da 100644 --- a/arch/ppc/ddr-8xxx/ddr2_dimm_params.c +++ b/arch/ppc/ddr-8xxx/ddr2_dimm_params.c @@ -190,13 +190,13 @@ uint32_t compute_dimm_parameters(const generic_spd_eeprom_t *spdin, struct dimm_params_s *pdimm) { - const struct ddr2_spd_eeprom_s *spd = spdin; - uint32_t retval; + const struct ddr2_spd_eeprom *spd = spdin; + int retval; if (spd->mem_type != SPD_MEMTYPE_DDR2) goto error; - retval = ddr2_spd_checksum_pass(spd); + retval = ddr2_spd_check(spd); if (retval) goto error; diff --git a/arch/ppc/ddr-8xxx/ddr3_dimm_params.c b/arch/ppc/ddr-8xxx/ddr3_dimm_params.c index d510c5b265..4f44925ab9 100644 --- a/arch/ppc/ddr-8xxx/ddr3_dimm_params.c +++ b/arch/ppc/ddr-8xxx/ddr3_dimm_params.c @@ -50,7 +50,7 @@ * 010 16bits * 011 32bits */ -static uint64_t compute_ranksize(const struct ddr3_spd_eeprom_s *spd) +static uint64_t compute_ranksize(const struct ddr3_spd_eeprom *spd) { uint64_t bsize; int sdram_cap_bsize = 0, prim_bus_width = 0, sdram_width = 0; @@ -78,14 +78,14 @@ uint32_t compute_dimm_parameters(const generic_spd_eeprom_t *spdin, struct dimm_params_s *pdimm) { - const struct ddr3_spd_eeprom_s *spd = spdin; - uint32_t retval, mtb_ps; - int ftb_tmp; + const struct ddr3_spd_eeprom *spd = spdin; + uint32_t mtb_ps; + int retval, ftb_tmp; if (spd->mem_type != SPD_MEMTYPE_DDR3) goto error; - retval = ddr3_spd_checksum_pass(spd); + retval = ddr3_spd_check(spd); if (retval) goto error; diff --git a/arch/ppc/include/asm/fsl_ddr_sdram.h b/arch/ppc/include/asm/fsl_ddr_sdram.h index 2c45608e5d..f4732389f6 100644 --- a/arch/ppc/include/asm/fsl_ddr_sdram.h +++ b/arch/ppc/include/asm/fsl_ddr_sdram.h @@ -32,10 +32,10 @@ #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) #if defined(CONFIG_FSL_DDR2) -typedef struct ddr2_spd_eeprom_s generic_spd_eeprom_t; +typedef struct ddr2_spd_eeprom generic_spd_eeprom_t; #define FSL_SDRAM_TYPE SDRAM_TYPE_DDR2 #elif defined(CONFIG_FSL_DDR3) -typedef struct ddr3_spd_eeprom_s generic_spd_eeprom_t; +typedef struct ddr3_spd_eeprom generic_spd_eeprom_t; #define FSL_SDRAM_TYPE SDRAM_TYPE_DDR3 #endif diff --git a/common/ddr_spd.c b/common/ddr_spd.c index 2110972f5b..9394c57fa3 100644 --- a/common/ddr_spd.c +++ b/common/ddr_spd.c @@ -10,39 +10,65 @@ #include <crc.h> #include <ddr_spd.h> -uint32_t ddr2_spd_checksum_pass(const struct ddr2_spd_eeprom_s *spd) +/* used for ddr1 and ddr2 spd */ +static int spd_check(const u8 *buf, u8 spd_rev, u8 spd_cksum) { - uint32_t i, cksum = 0; - const uint8_t *buf = (const uint8_t *)spd; - uint8_t rev, spd_cksum; + unsigned int cksum = 0; + unsigned int i; - rev = spd->spd_rev; - spd_cksum = spd->cksum; - - /* Rev 1.X or less supported by this code */ - if (rev >= 0x20) - goto error; + /* + * Check SPD revision supported + * Rev 1.X or less supported by this code + */ + if (spd_rev >= 0x20) { + printf("SPD revision %02X not supported by this code\n", + spd_rev); + return 1; + } + if (spd_rev > 0x13) { + printf("SPD revision %02X not verified by this code\n", + spd_rev); + } /* - * The checksum is calculated on the first 64 bytes - * of the SPD as per JEDEC specification. + * Calculate checksum */ for (i = 0; i < 63; i++) cksum += *buf++; + cksum &= 0xFF; - if (cksum != spd_cksum) - goto error; + if (cksum != spd_cksum) { + printf("SPD checksum unexpected. " + "Checksum in SPD = %02X, computed SPD = %02X\n", + spd_cksum, cksum); + return -EBADMSG; + } return 0; -error: - return 1; } -uint32_t ddr3_spd_checksum_pass(const struct ddr3_spd_eeprom_s *spd) +int ddr1_spd_check(const struct ddr1_spd_eeprom *spd) { - char crc_lsb, crc_msb; - int csum16, len; + const u8 *p = (const u8 *)spd; + + return spd_check(p, spd->spd_rev, spd->cksum); +} + +int ddr2_spd_check(const struct ddr2_spd_eeprom *spd) +{ + const u8 *p = (const u8 *)spd; + + return spd_check(p, spd->spd_rev, spd->cksum); +} + +int ddr3_spd_check(const struct ddr3_spd_eeprom *spd) +{ + char *p = (char *)spd; + int csum16; + int len; + char crc_lsb; /* byte 126 */ + char crc_msb; /* byte 127 */ /* * SPD byte0[7] - CRC coverage @@ -51,13 +77,61 @@ uint32_t ddr3_spd_checksum_pass(const struct ddr3_spd_eeprom_s *spd) */ len = !(spd->info_size_crc & 0x80) ? 126 : 117; - csum16 = crc_itu_t(0, (char *)spd, len); + csum16 = crc_itu_t(0, p, len); crc_lsb = (char) (csum16 & 0xff); crc_msb = (char) (csum16 >> 8); - if (spd->crc[0] != crc_lsb || spd->crc[1] != crc_msb) - return 1; + if (spd->crc[0] == crc_lsb && spd->crc[1] == crc_msb) { + return 0; + } else { + printf("SPD checksum unexpected.\n" + "Checksum lsb in SPD = %02X, computed SPD = %02X\n" + "Checksum msb in SPD = %02X, computed SPD = %02X\n", + spd->crc[0], crc_lsb, spd->crc[1], crc_msb); + return -EBADMSG; + } +} + +int ddr4_spd_check(const struct ddr4_spd_eeprom *spd) +{ + char *p = (char *)spd; + int csum16; + int len; + char crc_lsb; /* byte 126 */ + char crc_msb; /* byte 127 */ + + len = 126; + csum16 = crc_itu_t(0, p, len); + + crc_lsb = (char) (csum16 & 0xff); + crc_msb = (char) (csum16 >> 8); + + if (spd->crc[0] != crc_lsb || spd->crc[1] != crc_msb) { + printf("SPD checksum unexpected.\n" + "Checksum lsb in SPD = %02X, computed SPD = %02X\n" + "Checksum msb in SPD = %02X, computed SPD = %02X\n", + spd->crc[0], crc_lsb, spd->crc[1], crc_msb); + return -EBADMSG; + } + + p = (char *)((ulong)spd + 128); + len = 126; + csum16 = crc_itu_t(0, p, len); + + crc_lsb = (char) (csum16 & 0xff); + crc_msb = (char) (csum16 >> 8); + + if (spd->mod_section.uc[126] != crc_lsb || + spd->mod_section.uc[127] != crc_msb) { + printf("SPD checksum unexpected.\n" + "Checksum lsb in SPD = %02X, computed SPD = %02X\n" + "Checksum msb in SPD = %02X, computed SPD = %02X\n", + spd->mod_section.uc[126], + crc_lsb, spd->mod_section.uc[127], + crc_msb); + return -EBADMSG; + } return 0; } @@ -172,7 +246,7 @@ void ddr_spd_print(uint8_t *record) int ctime; uint8_t parity; char *ref, *sum; - struct ddr2_spd_eeprom_s *s = (struct ddr2_spd_eeprom_s *)record; + struct ddr2_spd_eeprom *s = (struct ddr2_spd_eeprom *)record; if (s->mem_type != SPD_MEMTYPE_DDR2) { printf("Can't dump information for non-DDR2 memory\n"); @@ -201,7 +275,7 @@ void ddr_spd_print(uint8_t *record) } } - if (ddr2_spd_checksum_pass(s)) + if (ddr2_spd_check(s)) sum = "ERR"; else sum = "OK"; diff --git a/include/ddr_spd.h b/include/ddr_spd.h index 01fe73c615..051275141f 100644 --- a/include/ddr_spd.h +++ b/include/ddr_spd.h @@ -1,242 +1,520 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * Copyright 2008-2014 Freescale Semiconductor, Inc. */ #ifndef _DDR_SPD_H_ #define _DDR_SPD_H_ +/* + * Format from "JEDEC Standard No. 21-C, + * Appendix D: Rev 1.0: SPD's for DDR SDRAM + */ +struct ddr1_spd_eeprom { + unsigned char info_size; /* 0 # bytes written into serial memory */ + unsigned char chip_size; /* 1 Total # bytes of SPD memory device */ + unsigned char mem_type; /* 2 Fundamental memory type */ + unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */ + unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */ + unsigned char nrows; /* 5 Number of DIMM Banks */ + unsigned char dataw_lsb; /* 6 Data Width of this assembly */ + unsigned char dataw_msb; /* 7 ... Data Width continuation */ + unsigned char voltage; /* 8 Voltage intf std of this assembly */ + unsigned char clk_cycle; /* 9 SDRAM Cycle time @ CL=X */ + unsigned char clk_access; /* 10 SDRAM Access from Clk @ CL=X (tAC) */ + unsigned char config; /* 11 DIMM Configuration type */ + unsigned char refresh; /* 12 Refresh Rate/Type */ + unsigned char primw; /* 13 Primary SDRAM Width */ + unsigned char ecw; /* 14 Error Checking SDRAM width */ + unsigned char min_delay; /* 15 for Back to Back Random Address */ + unsigned char burstl; /* 16 Burst Lengths Supported */ + unsigned char nbanks; /* 17 # of Banks on SDRAM Device */ + unsigned char cas_lat; /* 18 CAS# Latencies Supported */ + unsigned char cs_lat; /* 19 CS# Latency */ + unsigned char write_lat; /* 20 Write Latency (aka Write Recovery) */ + unsigned char mod_attr; /* 21 SDRAM Module Attributes */ + unsigned char dev_attr; /* 22 SDRAM Device Attributes */ + unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-0.5 */ + unsigned char clk_access2; /* 24 SDRAM Access from + Clk @ CL=X-0.5 (tAC) */ + unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-1 */ + unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */ + unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ + unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ + unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ + unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ + unsigned char bank_dens; /* 31 Density of each bank on module */ + unsigned char ca_setup; /* 32 Addr + Cmd Setup Time Before Clk */ + unsigned char ca_hold; /* 33 Addr + Cmd Hold Time After Clk */ + unsigned char data_setup; /* 34 Data Input Setup Time Before Strobe */ + unsigned char data_hold; /* 35 Data Input Hold Time After Strobe */ + unsigned char res_36_40[5];/* 36-40 reserved for VCSDRAM */ + unsigned char trc; /* 41 Min Active to Auto refresh time tRC */ + unsigned char trfc; /* 42 Min Auto to Active period tRFC */ + unsigned char tckmax; /* 43 Max device cycle time tCKmax */ + unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */ + unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */ + unsigned char res_46; /* 46 Reserved */ + unsigned char dimm_height; /* 47 DDR SDRAM DIMM Height */ + unsigned char res_48_61[14]; /* 48-61 Reserved */ + unsigned char spd_rev; /* 62 SPD Data Revision Code */ + unsigned char cksum; /* 63 Checksum for bytes 0-62 */ + unsigned char mid[8]; /* 64-71 Mfr's JEDEC ID code per JEP-106 */ + unsigned char mloc; /* 72 Manufacturing Location */ + unsigned char mpart[18]; /* 73 Manufacturer's Part Number */ + unsigned char rev[2]; /* 91 Revision Code */ + unsigned char mdate[2]; /* 93 Manufacturing Date */ + unsigned char sernum[4]; /* 95 Assembly Serial Number */ + unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */ + +}; + /* * Format from "JEDEC Appendix X: Serial Presence Detects for DDR2 SDRAM", * SPD Revision 1.2 */ -struct ddr2_spd_eeprom_s { - uint8_t info_size; /* 0 # bytes written into serial memory */ - uint8_t chip_size; /* 1 Total # bytes of SPD memory device */ - uint8_t mem_type; /* 2 Fundamental memory type */ - uint8_t nrow_addr; /* 3 # of Row Addresses on this assembly */ - uint8_t ncol_addr; /* 4 # of Column Addrs on this assembly */ - uint8_t mod_ranks; /* 5 Number of DIMM Ranks */ - uint8_t dataw; /* 6 Module Data Width */ - uint8_t res_7; /* 7 Reserved */ - uint8_t voltage; /* 8 Voltage intf std of this assembly */ - uint8_t clk_cycle; /* 9 SDRAM Cycle time @ CL=X */ - uint8_t clk_access; /* 10 SDRAM Access from Clk @ CL=X (tAC) */ - uint8_t config; /* 11 DIMM Configuration type */ - uint8_t refresh; /* 12 Refresh Rate/Type */ - uint8_t primw; /* 13 Primary SDRAM Width */ - uint8_t ecw; /* 14 Error Checking SDRAM width */ - uint8_t res_15; /* 15 Reserved */ - uint8_t burstl; /* 16 Burst Lengths Supported */ - uint8_t nbanks; /* 17 # of Banks on Each SDRAM Device */ - uint8_t cas_lat; /* 18 CAS# Latencies Supported */ - uint8_t mech_char; /* 19 DIMM Mechanical Characteristics */ - uint8_t dimm_type; /* 20 DIMM type information */ - uint8_t mod_attr; /* 21 SDRAM Module Attributes */ - uint8_t dev_attr; /* 22 SDRAM Device Attributes */ - uint8_t clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-1 */ - uint8_t clk_access2; /* 24 SDRAM Access from Clk @ CL=X-1 (tAC) */ - uint8_t clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-2 */ - uint8_t clk_access3; /* 26 Max Access from Clk @ CL=X-2 (tAC) */ - uint8_t trp; /* 27 Min Row Precharge Time (tRP)*/ - uint8_t trrd; /* 28 Min Row Active to Row Active (tRRD) */ - uint8_t trcd; /* 29 Min RAS to CAS Delay (tRCD) */ - uint8_t tras; /* 30 Minimum RAS Pulse Width (tRAS) */ - uint8_t rank_dens; /* 31 Density of each rank on module */ - uint8_t ca_setup; /* 32 Addr+Cmd Setup Time Before Clk (tIS) */ - uint8_t ca_hold; /* 33 Addr+Cmd Hold Time After Clk (tIH) */ - uint8_t data_setup; /* 34 Data Input Setup Time Before Strobe - (tDS) */ - uint8_t data_hold; /* 35 Data Input Hold Time - After Strobe (tDH) */ - uint8_t twr; /* 36 Write Recovery time tWR */ - uint8_t twtr; /* 37 Int write to read delay tWTR */ - uint8_t trtp; /* 38 Int read to precharge delay tRTP */ - uint8_t mem_probe; /* 39 Mem analysis probe characteristics */ - uint8_t trctrfc_ext; /* 40 Extensions to trc and trfc */ - uint8_t trc; /* 41 Min Active to Auto refresh time tRC */ - uint8_t trfc; /* 42 Min Auto to Active period tRFC */ - uint8_t tckmax; /* 43 Max device cycle time tCKmax */ - uint8_t tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */ - uint8_t tqhs; /* 45 Max Read DataHold skew (tQHS) */ - uint8_t pll_relock; /* 46 PLL Relock time */ - uint8_t Tcasemax; /* 47 Tcasemax */ - uint8_t psiTAdram; /* 48 Thermal Resistance of DRAM Package - from Top (Case) to Ambient - (Psi T-A DRAM) */ - uint8_t dt0_mode; /* 49 DRAM Case Temperature Rise from - Ambient due to Activate-Precharge/Mode - Bits (DT0/Mode Bits) */ - uint8_t dt2n_dt2q; /* 50 DRAM Case Temperature Rise from - Ambient due to Precharge/Quiet Standby - (DT2N/DT2Q) */ - uint8_t dt2p; /* 51 DRAM Case Temperature Rise from - Ambient due to Precharge Power-Down - (DT2P) */ - uint8_t dt3n; /* 52 DRAM Case Temperature Rise from - Ambient due to Active Standby (DT3N) */ - uint8_t dt3pfast; /* 53 DRAM Case Temperature Rise from - Ambient due to Active Power-Down with - Fast PDN Exit (DT3Pfast) */ - uint8_t dt3pslow; /* 54 DRAM Case Temperature Rise from - Ambient due to Active Power-Down with - Slow PDN Exit (DT3Pslow) */ - uint8_t dt4r_dt4r4w; /* 55 DRAM Case Temperature Rise from - Ambient due to Page Open Burst - Read/DT4R4W Mode Bit - (DT4R/DT4R4W Mode Bit) */ - uint8_t dt5b; /* 56 DRAM Case Temperature Rise from - Ambient due to Burst Refresh (DT5B) */ - uint8_t dt7; /* 57 DRAM Case Temperature Rise from - Ambient due to Bank Interleave Reads - with Auto-Precharge (DT7) */ - uint8_t psiTApll; /* 58 Thermal Resistance of PLL Package - form Top (Case) to Ambient - (Psi T-A PLL) */ - uint8_t psiTAreg; /* 59 Thermal Reisitance of Register - Package from Top (Case) to Ambient - (Psi T-A Register) */ - uint8_t dtpllactive; /* 60 PLL Case Temperature Rise from - Ambient due to PLL Active - (DT PLL Active) */ - uint8_t dtregact; /* 61 Register Case Temperature Rise from - Ambient due to Register Active/Mode - Bit (DT Register Active/Mode Bit) */ - uint8_t spd_rev; /* 62 SPD Data Revision Code */ - uint8_t cksum; /* 63 Checksum for bytes 0-62 */ - uint8_t mid[8]; /* 64 Mfr's JEDEC ID code per JEP-106 */ - uint8_t mloc; /* 72 Manufacturing Location */ - uint8_t mpart[18]; /* 73 Manufacturer's Part Number */ - uint8_t rev[2]; /* 91 Revision Code */ - uint8_t mdate[2]; /* 93 Manufacturing Date */ - uint8_t sernum[4]; /* 95 Assembly Serial Number */ - uint8_t mspec[27]; /* 99-127 Manufacturer Specific Data */ +struct ddr2_spd_eeprom { + unsigned char info_size; /* 0 # bytes written into serial memory */ + unsigned char chip_size; /* 1 Total # bytes of SPD memory device */ + unsigned char mem_type; /* 2 Fundamental memory type */ + unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */ + unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */ + unsigned char mod_ranks; /* 5 Number of DIMM Ranks */ + unsigned char dataw; /* 6 Module Data Width */ + unsigned char res_7; /* 7 Reserved */ + unsigned char voltage; /* 8 Voltage intf std of this assembly */ + unsigned char clk_cycle; /* 9 SDRAM Cycle time @ CL=X */ + unsigned char clk_access; /* 10 SDRAM Access from Clk @ CL=X (tAC) */ + unsigned char config; /* 11 DIMM Configuration type */ + unsigned char refresh; /* 12 Refresh Rate/Type */ + unsigned char primw; /* 13 Primary SDRAM Width */ + unsigned char ecw; /* 14 Error Checking SDRAM width */ + unsigned char res_15; /* 15 Reserved */ + unsigned char burstl; /* 16 Burst Lengths Supported */ + unsigned char nbanks; /* 17 # of Banks on Each SDRAM Device */ + unsigned char cas_lat; /* 18 CAS# Latencies Supported */ + unsigned char mech_char; /* 19 DIMM Mechanical Characteristics */ + unsigned char dimm_type; /* 20 DIMM type information */ + unsigned char mod_attr; /* 21 SDRAM Module Attributes */ + unsigned char dev_attr; /* 22 SDRAM Device Attributes */ + unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-1 */ + unsigned char clk_access2; /* 24 SDRAM Access from Clk @ CL=X-1 (tAC) */ + unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-2 */ + unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-2 (tAC) */ + unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ + unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ + unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ + unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ + unsigned char rank_dens; /* 31 Density of each rank on module */ + unsigned char ca_setup; /* 32 Addr+Cmd Setup Time Before Clk (tIS) */ + unsigned char ca_hold; /* 33 Addr+Cmd Hold Time After Clk (tIH) */ + unsigned char data_setup; /* 34 Data Input Setup Time + Before Strobe (tDS) */ + unsigned char data_hold; /* 35 Data Input Hold Time + After Strobe (tDH) */ + unsigned char twr; /* 36 Write Recovery time tWR */ + unsigned char twtr; /* 37 Int write to read delay tWTR */ + unsigned char trtp; /* 38 Int read to precharge delay tRTP */ + unsigned char mem_probe; /* 39 Mem analysis probe characteristics */ + unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */ + unsigned char trc; /* 41 Min Active to Auto refresh time tRC */ + unsigned char trfc; /* 42 Min Auto to Active period tRFC */ + unsigned char tckmax; /* 43 Max device cycle time tCKmax */ + unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */ + unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */ + unsigned char pll_relock; /* 46 PLL Relock time */ + unsigned char t_casemax; /* 47 Tcasemax */ + unsigned char psi_ta_dram; /* 48 Thermal Resistance of DRAM Package from + Top (Case) to Ambient (Psi T-A DRAM) */ + unsigned char dt0_mode; /* 49 DRAM Case Temperature Rise from Ambient + due to Activate-Precharge/Mode Bits + (DT0/Mode Bits) */ + unsigned char dt2n_dt2q; /* 50 DRAM Case Temperature Rise from Ambient + due to Precharge/Quiet Standby + (DT2N/DT2Q) */ + unsigned char dt2p; /* 51 DRAM Case Temperature Rise from Ambient + due to Precharge Power-Down (DT2P) */ + unsigned char dt3n; /* 52 DRAM Case Temperature Rise from Ambient + due to Active Standby (DT3N) */ + unsigned char dt3pfast; /* 53 DRAM Case Temperature Rise from Ambient + due to Active Power-Down with + Fast PDN Exit (DT3Pfast) */ + unsigned char dt3pslow; /* 54 DRAM Case Temperature Rise from Ambient + due to Active Power-Down with Slow + PDN Exit (DT3Pslow) */ + unsigned char dt4r_dt4r4w; /* 55 DRAM Case Temperature Rise from Ambient + due to Page Open Burst Read/DT4R4W + Mode Bit (DT4R/DT4R4W Mode Bit) */ + unsigned char dt5b; /* 56 DRAM Case Temperature Rise from Ambient + due to Burst Refresh (DT5B) */ + unsigned char dt7; /* 57 DRAM Case Temperature Rise from Ambient + due to Bank Interleave Reads with + Auto-Precharge (DT7) */ + unsigned char psi_ta_pll; /* 58 Thermal Resistance of PLL Package form + Top (Case) to Ambient (Psi T-A PLL) */ + unsigned char psi_ta_reg; /* 59 Thermal Reisitance of Register Package + from Top (Case) to Ambient + (Psi T-A Register) */ + unsigned char dtpllactive; /* 60 PLL Case Temperature Rise from Ambient + due to PLL Active (DT PLL Active) */ + unsigned char dtregact; /* 61 Register Case Temperature Rise from + Ambient due to Register Active/Mode Bit + (DT Register Active/Mode Bit) */ + unsigned char spd_rev; /* 62 SPD Data Revision Code */ + unsigned char cksum; /* 63 Checksum for bytes 0-62 */ + unsigned char mid[8]; /* 64 Mfr's JEDEC ID code per JEP-106 */ + unsigned char mloc; /* 72 Manufacturing Location */ + unsigned char mpart[18]; /* 73 Manufacturer's Part Number */ + unsigned char rev[2]; /* 91 Revision Code */ + unsigned char mdate[2]; /* 93 Manufacturing Date */ + unsigned char sernum[4]; /* 95 Assembly Serial Number */ + unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */ + }; -struct ddr3_spd_eeprom_s { +struct ddr3_spd_eeprom { /* General Section: Bytes 0-59 */ - uint8_t info_size_crc; /* 0 # bytes written into serial memory, + unsigned char info_size_crc; /* 0 # bytes written into serial memory, CRC coverage */ - uint8_t spd_rev; /* 1 Total # bytes of SPD mem device */ - uint8_t mem_type; /* 2 Key Byte / Fundamental mem type */ - uint8_t module_type; /* 3 Key Byte / Module Type */ - uint8_t density_banks; /* 4 SDRAM Density and Banks */ - uint8_t addressing; /* 5 SDRAM Addressing */ - uint8_t module_vdd; /* 6 Module nominal voltage, VDD */ - uint8_t organization; /* 7 Module Organization */ - uint8_t bus_width; /* 8 Module Memory Bus Width */ - uint8_t ftb_div; /* 9 Fine Timebase (FTB) + unsigned char spd_rev; /* 1 Total # bytes of SPD mem device */ + unsigned char mem_type; /* 2 Key Byte / Fundamental mem type */ + unsigned char module_type; /* 3 Key Byte / Module Type */ + unsigned char density_banks; /* 4 SDRAM Density and Banks */ + unsigned char addressing; /* 5 SDRAM Addressing */ + unsigned char module_vdd; /* 6 Module nominal voltage, VDD */ + unsigned char organization; /* 7 Module Organization */ + unsigned char bus_width; /* 8 Module Memory Bus Width */ + unsigned char ftb_div; /* 9 Fine Timebase (FTB) Dividend / Divisor */ - uint8_t mtb_dividend; /* 10 Medium Timebase (MTB) Dividend */ - uint8_t mtb_divisor; /* 11 Medium Timebase (MTB) Divisor */ - uint8_t tck_min; /* 12 SDRAM Minimum Cycle Time */ - uint8_t res_13; /* 13 Reserved */ - uint8_t caslat_lsb; /* 14 CAS Latencies Supported, + unsigned char mtb_dividend; /* 10 Medium Timebase (MTB) Dividend */ + unsigned char mtb_divisor; /* 11 Medium Timebase (MTB) Divisor */ + unsigned char tck_min; /* 12 SDRAM Minimum Cycle Time */ + unsigned char res_13; /* 13 Reserved */ + unsigned char caslat_lsb; /* 14 CAS Latencies Supported, Least Significant Byte */ - uint8_t caslat_msb; /* 15 CAS Latencies Supported, + unsigned char caslat_msb; /* 15 CAS Latencies Supported, Most Significant Byte */ - uint8_t taa_min; /* 16 Min CAS Latency Time */ - uint8_t twr_min; /* 17 Min Write REcovery Time */ - uint8_t trcd_min; /* 18 Min RAS# to CAS# Delay Time */ - uint8_t trrd_min; /* 19 Min Row Active to + unsigned char taa_min; /* 16 Min CAS Latency Time */ + unsigned char twr_min; /* 17 Min Write REcovery Time */ + unsigned char trcd_min; /* 18 Min RAS# to CAS# Delay Time */ + unsigned char trrd_min; /* 19 Min Row Active to Row Active Delay Time */ - uint8_t trp_min; /* 20 Min Row Precharge Delay Time */ - uint8_t tras_trc_ext; /* 21 Upper Nibbles for tRAS and tRC */ - uint8_t tras_min_lsb; /* 22 Min Active to Precharge + unsigned char trp_min; /* 20 Min Row Precharge Delay Time */ + unsigned char tras_trc_ext; /* 21 Upper Nibbles for tRAS and tRC */ + unsigned char tras_min_lsb; /* 22 Min Active to Precharge Delay Time */ - uint8_t trc_min_lsb; /* 23 Min Active to Active/Refresh + unsigned char trc_min_lsb; /* 23 Min Active to Active/Refresh Delay Time, LSB */ - uint8_t trfc_min_lsb; /* 24 Min Refresh Recovery Delay Time */ - uint8_t trfc_min_msb; /* 25 Min Refresh Recovery Delay Time */ - uint8_t twtr_min; /* 26 Min Internal Write to + unsigned char trfc_min_lsb; /* 24 Min Refresh Recovery Delay Time */ + unsigned char trfc_min_msb; /* 25 Min Refresh Recovery Delay Time */ + unsigned char twtr_min; /* 26 Min Internal Write to Read Command Delay Time */ - uint8_t trtp_min; /* 27 Min Internal Read to Precharge + unsigned char trtp_min; /* 27 Min Internal Read to Precharge Command Delay Time */ - uint8_t tfaw_msb; /* 28 Upper Nibble for tFAW */ - uint8_t tfaw_min; /* 29 Min Four Activate Window + unsigned char tfaw_msb; /* 28 Upper Nibble for tFAW */ + unsigned char tfaw_min; /* 29 Min Four Activate Window Delay Time*/ - uint8_t opt_features; /* 30 SDRAM Optional Features */ - uint8_t therm_ref_opt; /* 31 SDRAM Thermal and Refresh Opts */ - uint8_t therm_sensor; /* 32 Module Thermal Sensor */ - uint8_t device_type; /* 33 SDRAM device type */ - int8_t fine_tck_min; /* 34 Fine offset for tCKmin */ - int8_t fine_taa_min; /* 35 Fine offset for tAAmin */ - int8_t fine_trcd_min; /* 36 Fine offset for tRCDmin */ - int8_t fine_trp_min; /* 37 Fine offset for tRPmin */ - int8_t fine_trc_min; /* 38 Fine offset for tRCmin */ - uint8_t res_39_59[21]; /* 39-59 Reserved, General Section */ + unsigned char opt_features; /* 30 SDRAM Optional Features */ + unsigned char therm_ref_opt; /* 31 SDRAM Thermal and Refresh Opts */ + unsigned char therm_sensor; /* 32 Module Thermal Sensor */ + unsigned char device_type; /* 33 SDRAM device type */ + int8_t fine_tck_min; /* 34 Fine offset for tCKmin */ + int8_t fine_taa_min; /* 35 Fine offset for tAAmin */ + int8_t fine_trcd_min; /* 36 Fine offset for tRCDmin */ + int8_t fine_trp_min; /* 37 Fine offset for tRPmin */ + int8_t fine_trc_min; /* 38 Fine offset for tRCmin */ + unsigned char res_39_59[21]; /* 39-59 Reserved, General Section */ /* Module-Specific Section: Bytes 60-116 */ union { struct { /* 60 (Unbuffered) Module Nominal Height */ - uint8_t mod_height; + unsigned char mod_height; /* 61 (Unbuffered) Module Maximum Thickness */ - uint8_t mod_thickness; + unsigned char mod_thickness; /* 62 (Unbuffered) Reference Raw Card Used */ - uint8_t ref_raw_card; + unsigned char ref_raw_card; /* 63 (Unbuffered) Address Mapping from Edge Connector to DRAM */ - uint8_t addr_mapping; + unsigned char addr_mapping; /* 64-116 (Unbuffered) Reserved */ - uint8_t res_64_116[53]; + unsigned char res_64_116[53]; } unbuffered; struct { /* 60 (Registered) Module Nominal Height */ - uint8_t mod_height; + unsigned char mod_height; /* 61 (Registered) Module Maximum Thickness */ - uint8_t mod_thickness; + unsigned char mod_thickness; /* 62 (Registered) Reference Raw Card Used */ - uint8_t ref_raw_card; + unsigned char ref_raw_card; /* 63 DIMM Module Attributes */ - uint8_t modu_attr; + unsigned char modu_attr; /* 64 RDIMM Thermal Heat Spreader Solution */ - uint8_t thermal; - /* 65 Register Manufacturer ID Code, LSB */ - uint8_t reg_id_lo; - /* 66 Register Manufacturer ID Code, MSB */ - uint8_t reg_id_hi; + unsigned char thermal; + /* 65 Register Manufacturer ID Code, Least Significant Byte */ + unsigned char reg_id_lo; + /* 66 Register Manufacturer ID Code, Most Significant Byte */ + unsigned char reg_id_hi; /* 67 Register Revision Number */ - uint8_t reg_rev; + unsigned char reg_rev; /* 68 Register Type */ - uint8_t reg_type; - /* 69-76 RC1,3,5..15 (MS Nib.)/RC0,2,4..14 (LS Nib.) */ - uint8_t rcw[8]; + unsigned char reg_type; + /* 69-76 RC1,3,5...15 (MS Nibble) / RC0,2,4...14 (LS Nibble) */ + unsigned char rcw[8]; } registered; - uint8_t uc[57]; /* 60-116 Module-Specific Section */ + unsigned char uc[57]; /* 60-116 Module-Specific Section */ } mod_section; /* Unique Module ID: Bytes 117-125 */ - uint8_t mmid_lsb; /* 117 Module MfgID Code LSB - JEP-106 */ - uint8_t mmid_msb; /* 118 Module MfgID Code MSB - JEP-106 */ - uint8_t mloc; /* 119 Mfg Location */ - uint8_t mdate[2]; /* 120-121 Mfg Date */ - uint8_t sernum[4]; /* 122-125 Module Serial Number */ + unsigned char mmid_lsb; /* 117 Module MfgID Code LSB - JEP-106 */ + unsigned char mmid_msb; /* 118 Module MfgID Code MSB - JEP-106 */ + unsigned char mloc; /* 119 Mfg Location */ + unsigned char mdate[2]; /* 120-121 Mfg Date */ + unsigned char sernum[4]; /* 122-125 Module Serial Number */ /* CRC: Bytes 126-127 */ - uint8_t crc[2]; /* 126-127 SPD CRC */ + unsigned char crc[2]; /* 126-127 SPD CRC */ /* Other Manufacturer Fields and User Space: Bytes 128-255 */ - uint8_t mpart[18]; /* 128-145 Mfg's Module Part Number */ - uint8_t mrev[2]; /* 146-147 Module Revision Code */ - uint8_t dmid_lsb; /* 148 DRAM MfgID Code LSB - JEP-106 */ - uint8_t dmid_msb; /* 149 DRAM MfgID Code MSB - JEP-106 */ - uint8_t msd[26]; /* 150-175 Mfg's Specific Data */ - uint8_t cust[80]; /* 176-255 Open for Customer Use */ + unsigned char mpart[18]; /* 128-145 Mfg's Module Part Number */ + unsigned char mrev[2]; /* 146-147 Module Revision Code */ + + unsigned char dmid_lsb; /* 148 DRAM MfgID Code LSB - JEP-106 */ + unsigned char dmid_msb; /* 149 DRAM MfgID Code MSB - JEP-106 */ + + unsigned char msd[26]; /* 150-175 Mfg's Specific Data */ + unsigned char cust[80]; /* 176-255 Open for Customer Use */ + }; -extern void ddr_spd_print(uint8_t *record); -extern uint32_t ddr3_spd_checksum_pass(const struct ddr3_spd_eeprom_s *spd); -extern uint32_t ddr2_spd_checksum_pass(const struct ddr2_spd_eeprom_s *spd); +/* From JEEC Standard No. 21-C release 23A */ +struct ddr4_spd_eeprom { + /* General Section: Bytes 0-127 */ + uint8_t info_size_crc; /* 0 # bytes */ + uint8_t spd_rev; /* 1 Total # bytes of SPD */ + uint8_t mem_type; /* 2 Key Byte / mem type */ + uint8_t module_type; /* 3 Key Byte / Module Type */ + uint8_t density_banks; /* 4 Density and Banks */ + uint8_t addressing; /* 5 Addressing */ + uint8_t package_type; /* 6 Package type */ + uint8_t opt_feature; /* 7 Optional features */ + uint8_t thermal_ref; /* 8 Thermal and refresh */ + uint8_t oth_opt_features; /* 9 Other optional features */ + uint8_t res_10; /* 10 Reserved */ + uint8_t module_vdd; /* 11 Module nominal voltage */ + uint8_t organization; /* 12 Module Organization */ + uint8_t bus_width; /* 13 Module Memory Bus Width */ + uint8_t therm_sensor; /* 14 Module Thermal Sensor */ + uint8_t ext_type; /* 15 Extended module type */ + uint8_t res_16; + uint8_t timebases; /* 17 MTb and FTB */ + uint8_t tck_min; /* 18 tCKAVGmin */ + uint8_t tck_max; /* 19 TCKAVGmax */ + uint8_t caslat_b1; /* 20 CAS latencies, 1st byte */ + uint8_t caslat_b2; /* 21 CAS latencies, 2nd byte */ + uint8_t caslat_b3; /* 22 CAS latencies, 3rd byte */ + uint8_t caslat_b4; /* 23 CAS latencies, 4th byte */ + uint8_t taa_min; /* 24 Min CAS Latency Time */ + uint8_t trcd_min; /* 25 Min RAS# to CAS# Delay Time */ + uint8_t trp_min; /* 26 Min Row Precharge Delay Time */ + uint8_t tras_trc_ext; /* 27 Upper Nibbles for tRAS and tRC */ + uint8_t tras_min_lsb; /* 28 tRASmin, lsb */ + uint8_t trc_min_lsb; /* 29 tRCmin, lsb */ + uint8_t trfc1_min_lsb; /* 30 Min Refresh Recovery Delay Time */ + uint8_t trfc1_min_msb; /* 31 Min Refresh Recovery Delay Time */ + uint8_t trfc2_min_lsb; /* 32 Min Refresh Recovery Delay Time */ + uint8_t trfc2_min_msb; /* 33 Min Refresh Recovery Delay Time */ + uint8_t trfc4_min_lsb; /* 34 Min Refresh Recovery Delay Time */ + uint8_t trfc4_min_msb; /* 35 Min Refresh Recovery Delay Time */ + uint8_t tfaw_msb; /* 36 Upper Nibble for tFAW */ + uint8_t tfaw_min; /* 37 tFAW, lsb */ + uint8_t trrds_min; /* 38 tRRD_Smin, MTB */ + uint8_t trrdl_min; /* 39 tRRD_Lmin, MTB */ + uint8_t tccdl_min; /* 40 tCCS_Lmin, MTB */ + uint8_t res_41[60-41]; /* 41 Rserved */ + uint8_t mapping[78-60]; /* 60~77 Connector to SDRAM bit map */ + uint8_t res_78[117-78]; /* 78~116, Reserved */ + int8_t fine_tccdl_min; /* 117 Fine offset for tCCD_Lmin */ + int8_t fine_trrdl_min; /* 118 Fine offset for tRRD_Lmin */ + int8_t fine_trrds_min; /* 119 Fine offset for tRRD_Smin */ + int8_t fine_trc_min; /* 120 Fine offset for tRCmin */ + int8_t fine_trp_min; /* 121 Fine offset for tRPmin */ + int8_t fine_trcd_min; /* 122 Fine offset for tRCDmin */ + int8_t fine_taa_min; /* 123 Fine offset for tAAmin */ + int8_t fine_tck_max; /* 124 Fine offset for tCKAVGmax */ + int8_t fine_tck_min; /* 125 Fine offset for tCKAVGmin */ + /* CRC: Bytes 126-127 */ + uint8_t crc[2]; /* 126-127 SPD CRC */ + + /* Module-Specific Section: Bytes 128-255 */ + union { + struct { + /* 128 (Unbuffered) Module Nominal Height */ + uint8_t mod_height; + /* 129 (Unbuffered) Module Maximum Thickness */ + uint8_t mod_thickness; + /* 130 (Unbuffered) Reference Raw Card Used */ + uint8_t ref_raw_card; + /* 131 (Unbuffered) Address Mapping from + Edge Connector to DRAM */ + uint8_t addr_mapping; + /* 132~253 (Unbuffered) Reserved */ + uint8_t res_132[254-132]; + /* 254~255 CRC */ + uint8_t crc[2]; + } unbuffered; + struct { + /* 128 (Registered) Module Nominal Height */ + uint8_t mod_height; + /* 129 (Registered) Module Maximum Thickness */ + uint8_t mod_thickness; + /* 130 (Registered) Reference Raw Card Used */ + uint8_t ref_raw_card; + /* 131 DIMM Module Attributes */ + uint8_t modu_attr; + /* 132 RDIMM Thermal Heat Spreader Solution */ + uint8_t thermal; + /* 133 Register Manufacturer ID Code, LSB */ + uint8_t reg_id_lo; + /* 134 Register Manufacturer ID Code, MSB */ + uint8_t reg_id_hi; + /* 135 Register Revision Number */ + uint8_t reg_rev; + /* 136 Address mapping from register to DRAM */ + u8 reg_map; + u8 ca_stren; + u8 clk_stren; + /* 139~253 Reserved */ + u8 res_137[254 - 139]; + /* 254~255 CRC */ + uint8_t crc[2]; + } registered; + struct { + /* 128 (Loadreduced) Module Nominal Height */ + uint8_t mod_height; + /* 129 (Loadreduced) Module Maximum Thickness */ + uint8_t mod_thickness; + /* 130 (Loadreduced) Reference Raw Card Used */ + uint8_t ref_raw_card; + /* 131 DIMM Module Attributes */ + uint8_t modu_attr; + /* 132 RDIMM Thermal Heat Spreader Solution */ + uint8_t thermal; + /* 133 Register Manufacturer ID Code, LSB */ + uint8_t reg_id_lo; + /* 134 Register Manufacturer ID Code, MSB */ + uint8_t reg_id_hi; + /* 135 Register Revision Number */ + uint8_t reg_rev; + /* 136 Address mapping from register to DRAM */ + uint8_t reg_map; + /* 137 Register Output Drive Strength for CMD/Add*/ + uint8_t reg_drv; + /* 138 Register Output Drive Strength for CK */ + uint8_t reg_drv_ck; + /* 139 Data Buffer Revision Number */ + uint8_t data_buf_rev; + /* 140 DRAM VrefDQ for Package Rank 0 */ + uint8_t vrefqe_r0; + /* 141 DRAM VrefDQ for Package Rank 1 */ + uint8_t vrefqe_r1; + /* 142 DRAM VrefDQ for Package Rank 2 */ + uint8_t vrefqe_r2; + /* 143 DRAM VrefDQ for Package Rank 3 */ + uint8_t vrefqe_r3; + /* 144 Data Buffer VrefDQ for DRAM Interface */ + uint8_t data_intf; + /* + * 145 Data Buffer MDQ Drive Strength and RTT + * for data rate <= 1866 + */ + uint8_t data_drv_1866; + /* + * 146 Data Buffer MDQ Drive Strength and RTT + * for 1866 < data rate <= 2400 + */ + uint8_t data_drv_2400; + /* + * 147 Data Buffer MDQ Drive Strength and RTT + * for 2400 < data rate <= 3200 + */ + uint8_t data_drv_3200; + /* 148 DRAM Drive Strength */ + uint8_t dram_drv; + /* + * 149 DRAM ODT (RTT_WR, RTT_NOM) + * for data rate <= 1866 + */ + uint8_t dram_odt_1866; + /* + * 150 DRAM ODT (RTT_WR, RTT_NOM) + * for 1866 < data rate <= 2400 + */ + uint8_t dram_odt_2400; + /* + * 151 DRAM ODT (RTT_WR, RTT_NOM) + * for 2400 < data rate <= 3200 + */ + uint8_t dram_odt_3200; + /* + * 152 DRAM ODT (RTT_PARK) + * for data rate <= 1866 + */ + uint8_t dram_odt_park_1866; + /* + * 153 DRAM ODT (RTT_PARK) + * for 1866 < data rate <= 2400 + */ + uint8_t dram_odt_park_2400; + /* + * 154 DRAM ODT (RTT_PARK) + * for 2400 < data rate <= 3200 + */ + uint8_t dram_odt_park_3200; + uint8_t res_155[254-155]; /* Reserved */ + /* 254~255 CRC */ + uint8_t crc[2]; + } loadreduced; + uint8_t uc[128]; /* 128-255 Module-Specific Section */ + } mod_section; + + uint8_t res_256[320-256]; /* 256~319 Reserved */ + + /* Module supplier's data: Byte 320~383 */ + uint8_t mmid_lsb; /* 320 Module MfgID Code LSB */ + uint8_t mmid_msb; /* 321 Module MfgID Code MSB */ + uint8_t mloc; /* 322 Mfg Location */ + uint8_t mdate[2]; /* 323~324 Mfg Date */ + uint8_t sernum[4]; /* 325~328 Module Serial Number */ + uint8_t mpart[20]; /* 329~348 Mfg's Module Part Number */ + uint8_t mrev; /* 349 Module Revision Code */ + uint8_t dmid_lsb; /* 350 DRAM MfgID Code LSB */ + uint8_t dmid_msb; /* 351 DRAM MfgID Code MSB */ + uint8_t stepping; /* 352 DRAM stepping */ + uint8_t msd[29]; /* 353~381 Mfg's Specific Data */ + uint8_t res_382[2]; /* 382~383 Reserved */ -/* * Byte 2 Fundamental Memory Types. */ + uint8_t user[512-384]; /* 384~511 End User Programmable */ +}; + +/* + * Byte 2 Fundamental Memory Types. + */ +#define SPD_MEMTYPE_FPM (0x01) +#define SPD_MEMTYPE_EDO (0x02) +#define SPD_MEMTYPE_PIPE_NIBBLE (0x03) +#define SPD_MEMTYPE_SDRAM (0x04) +#define SPD_MEMTYPE_ROM (0x05) +#define SPD_MEMTYPE_SGRAM (0x06) +#define SPD_MEMTYPE_DDR (0x07) #define SPD_MEMTYPE_DDR2 (0x08) +#define SPD_MEMTYPE_DDR2_FBDIMM (0x09) +#define SPD_MEMTYPE_DDR2_FBDIMM_PROBE (0x0A) #define SPD_MEMTYPE_DDR3 (0x0B) +#define SPD_MEMTYPE_DDR4 (0x0C) /* DIMM Type for DDR2 SPD (according to v1.3) */ +#define DDR2_SPD_DIMMTYPE_UNDEFINED (0x00) #define DDR2_SPD_DIMMTYPE_RDIMM (0x01) #define DDR2_SPD_DIMMTYPE_UDIMM (0x02) #define DDR2_SPD_DIMMTYPE_SO_DIMM (0x04) @@ -247,6 +525,41 @@ extern uint32_t ddr2_spd_checksum_pass(const struct ddr2_spd_eeprom_s *spd); #define DDR2_SPD_DIMMTYPE_MINI_UDIMM (0x20) /* Byte 3 Key Byte / Module Type for DDR3 SPD */ -#define DDR3_SPD_MODULETYPE_MASK (0x0F) +#define DDR3_SPD_MODULETYPE_MASK (0x0f) +#define DDR3_SPD_MODULETYPE_RDIMM (0x01) #define DDR3_SPD_MODULETYPE_UDIMM (0x02) +#define DDR3_SPD_MODULETYPE_SO_DIMM (0x03) +#define DDR3_SPD_MODULETYPE_MICRO_DIMM (0x04) +#define DDR3_SPD_MODULETYPE_MINI_RDIMM (0x05) +#define DDR3_SPD_MODULETYPE_MINI_UDIMM (0x06) +#define DDR3_SPD_MODULETYPE_MINI_CDIMM (0x07) +#define DDR3_SPD_MODULETYPE_72B_SO_UDIMM (0x08) +#define DDR3_SPD_MODULETYPE_72B_SO_RDIMM (0x09) +#define DDR3_SPD_MODULETYPE_72B_SO_CDIMM (0x0A) +#define DDR3_SPD_MODULETYPE_LRDIMM (0x0B) +#define DDR3_SPD_MODULETYPE_16B_SO_DIMM (0x0C) +#define DDR3_SPD_MODULETYPE_32B_SO_DIMM (0x0D) + +/* DIMM Type for DDR4 SPD */ +#define DDR4_SPD_MODULETYPE_MASK (0x0f) +#define DDR4_SPD_MODULETYPE_EXT (0x00) +#define DDR4_SPD_MODULETYPE_RDIMM (0x01) +#define DDR4_SPD_MODULETYPE_UDIMM (0x02) +#define DDR4_SPD_MODULETYPE_SO_DIMM (0x03) +#define DDR4_SPD_MODULETYPE_LRDIMM (0x04) +#define DDR4_SPD_MODULETYPE_MINI_RDIMM (0x05) +#define DDR4_SPD_MODULETYPE_MINI_UDIMM (0x06) +#define DDR4_SPD_MODULETYPE_72B_SO_UDIMM (0x08) +#define DDR4_SPD_MODULETYPE_72B_SO_RDIMM (0x09) +#define DDR4_SPD_MODULETYPE_16B_SO_DIMM (0x0C) +#define DDR4_SPD_MODULETYPE_32B_SO_DIMM (0x0D) + +void ddr_spd_print(uint8_t *record); +int ddr1_spd_check(const struct ddr1_spd_eeprom *spd); +void ddr1_spd_dump(const struct ddr1_spd_eeprom *spd); +int ddr2_spd_check(const struct ddr2_spd_eeprom *spd); +void ddr2_spd_dump(const struct ddr2_spd_eeprom *spd); +int ddr3_spd_check(const struct ddr3_spd_eeprom *spd); +int ddr4_spd_check(const struct ddr4_spd_eeprom *spd); + #endif /* _DDR_SPD_H_ */ -- 2.20.1 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 4/6] ddr_spd: Add function to read eeprom 2019-03-04 11:38 [PATCH 0/6] SPD EEPROM improvements Sascha Hauer ` (2 preceding siblings ...) 2019-03-04 11:38 ` [PATCH 3/6] ddr_spd: Update from U-Boot Sascha Hauer @ 2019-03-04 11:38 ` Sascha Hauer 2019-03-04 11:53 ` Sam Ravnborg 2019-03-04 12:02 ` Sam Ravnborg 2019-03-04 11:38 ` [PATCH 5/6] ddr_spd: provide common SPD type Sascha Hauer 2019-03-04 11:38 ` [PATCH 6/6] ddr_spd: Enable in PBL Sascha Hauer 5 siblings, 2 replies; 12+ messages in thread From: Sascha Hauer @ 2019-03-04 11:38 UTC (permalink / raw) To: Barebox List Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- common/ddr_spd.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++ include/ddr_spd.h | 6 ++++ 2 files changed, 87 insertions(+) diff --git a/common/ddr_spd.c b/common/ddr_spd.c index 9394c57fa3..a878790550 100644 --- a/common/ddr_spd.c +++ b/common/ddr_spd.c @@ -429,3 +429,84 @@ void ddr_spd_print(uint8_t *record) printf("%02X", record[i]); printf("\n"); } + +#define SPD_SPA0_ADDRESS 0x36 +#define SPD_SPA1_ADDRESS 0x37 + +static int select_page(void *ctx, + int (*xfer)(void *ctx, struct i2c_msg *msgs, int num), + uint8_t addr) +{ + struct i2c_msg msg = { + .addr = addr, + .len = 0, + }; + int ret; + + ret = xfer(ctx, &msg, 1); + if (ret < 0) + return ret; + + return 0; +} + +static int read_buf(void *ctx, + int (*xfer)(void *ctx, struct i2c_msg *msgs, int num), + uint8_t addr, int page, void *buf) +{ + uint8_t pos = 0; + int ret; + struct i2c_msg msg[2] = { + { + .addr = addr, + .len = 1, + .buf = &pos, + }, { + .addr = addr, + .len = 256, + .flags = I2C_M_RD, + .buf = buf, + } + }; + + ret = select_page(ctx, xfer, page); + if (ret < 0) + return ret; + + ret = xfer(ctx, msg, 2); + if (ret < 0) + return ret; + + return 0; +} + +/** + * spd_read_eeprom - Read contents of a SPD EEPROM + * @ctx: Context pointer for the xfer function + * @xfer: I2C message transfer function + * @addr: I2C bus address for the EEPROM + * @buf: buffer to read the SPD data to + * + * This function takes a I2C message transfer function and reads the contents + * from a SPD EEPROM to the buffer provided at @buf. Returns 0 for success or a + * negative error code otherwise. + */ +int spd_read_eeprom(void *ctx, + int (*xfer)(void *ctx, struct i2c_msg *msgs, int num), + uint8_t addr, void *buf) +{ + unsigned char *buf8 = buf; + int ret; + + ret = read_buf(ctx, xfer, addr, SPD_SPA0_ADDRESS, buf); + if (ret < 0) + return ret; + + if (buf8[2] == SPD_MEMTYPE_DDR4) { + ret = read_buf(ctx, xfer, addr, SPD_SPA1_ADDRESS, buf + 256); + if (ret < 0) + return ret; + } + + return 0; +} diff --git a/include/ddr_spd.h b/include/ddr_spd.h index 051275141f..95d0eb04b6 100644 --- a/include/ddr_spd.h +++ b/include/ddr_spd.h @@ -6,6 +6,8 @@ #ifndef _DDR_SPD_H_ #define _DDR_SPD_H_ +#include <i2c/i2c.h> + /* * Format from "JEDEC Standard No. 21-C, * Appendix D: Rev 1.0: SPD's for DDR SDRAM @@ -562,4 +564,8 @@ void ddr2_spd_dump(const struct ddr2_spd_eeprom *spd); int ddr3_spd_check(const struct ddr3_spd_eeprom *spd); int ddr4_spd_check(const struct ddr4_spd_eeprom *spd); +int spd_read_eeprom(void *ctx, + int (*xfer)(void *ctx, struct i2c_msg *msgs, int num), + uint8_t addr, void *buf); + #endif /* _DDR_SPD_H_ */ -- 2.20.1 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 4/6] ddr_spd: Add function to read eeprom 2019-03-04 11:38 ` [PATCH 4/6] ddr_spd: Add function to read eeprom Sascha Hauer @ 2019-03-04 11:53 ` Sam Ravnborg 2019-03-04 12:02 ` Sam Ravnborg 1 sibling, 0 replies; 12+ messages in thread From: Sam Ravnborg @ 2019-03-04 11:53 UTC (permalink / raw) To: Sascha Hauer; +Cc: Barebox List On Mon, Mar 04, 2019 at 12:38:21PM +0100, Sascha Hauer wrote: > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > common/ddr_spd.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++ > include/ddr_spd.h | 6 ++++ > 2 files changed, 87 insertions(+) > > diff --git a/common/ddr_spd.c b/common/ddr_spd.c > index 9394c57fa3..a878790550 100644 > --- a/common/ddr_spd.c > +++ b/common/ddr_spd.c > @@ -429,3 +429,84 @@ void ddr_spd_print(uint8_t *record) > printf("%02X", record[i]); > printf("\n"); > } > + > +#define SPD_SPA0_ADDRESS 0x36 > +#define SPD_SPA1_ADDRESS 0x37 > + > +static int select_page(void *ctx, > + int (*xfer)(void *ctx, struct i2c_msg *msgs, int num), > + uint8_t addr) Indent looks strange. > + > +static int read_buf(void *ctx, > + int (*xfer)(void *ctx, struct i2c_msg *msgs, int num), > + uint8_t addr, int page, void *buf) Same here. > +/** > + * spd_read_eeprom - Read contents of a SPD EEPROM > + * @ctx: Context pointer for the xfer function > + * @xfer: I2C message transfer function > + * @addr: I2C bus address for the EEPROM > + * @buf: buffer to read the SPD data to > + * > + * This function takes a I2C message transfer function and reads the contents > + * from a SPD EEPROM to the buffer provided at @buf. Returns 0 for success or a > + * negative error code otherwise. > + */ > +int spd_read_eeprom(void *ctx, > + int (*xfer)(void *ctx, struct i2c_msg *msgs, int num), > + uint8_t addr, void *buf) > +{ This looks okay. I may have missed some trivial logic problems while my focus was at the very important indentation - sorry :-) Sam _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 4/6] ddr_spd: Add function to read eeprom 2019-03-04 11:38 ` [PATCH 4/6] ddr_spd: Add function to read eeprom Sascha Hauer 2019-03-04 11:53 ` Sam Ravnborg @ 2019-03-04 12:02 ` Sam Ravnborg 2019-03-04 13:22 ` Sascha Hauer 1 sibling, 1 reply; 12+ messages in thread From: Sam Ravnborg @ 2019-03-04 12:02 UTC (permalink / raw) To: Sascha Hauer; +Cc: Barebox List Hi Sascha On Mon, Mar 04, 2019 at 12:38:21PM +0100, Sascha Hauer wrote: > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > common/ddr_spd.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++ > include/ddr_spd.h | 6 ++++ > 2 files changed, 87 insertions(+) > > diff --git a/common/ddr_spd.c b/common/ddr_spd.c > index 9394c57fa3..a878790550 100644 > --- a/common/ddr_spd.c > +++ b/common/ddr_spd.c > @@ -429,3 +429,84 @@ void ddr_spd_print(uint8_t *record) > printf("%02X", record[i]); > printf("\n"); > } > + > +#define SPD_SPA0_ADDRESS 0x36 > +#define SPD_SPA1_ADDRESS 0x37 > + > +static int select_page(void *ctx, > + int (*xfer)(void *ctx, struct i2c_msg *msgs, int num), > + uint8_t addr) > +{ > + struct i2c_msg msg = { > + .addr = addr, > + .len = 0, > + }; > + int ret; > + > + ret = xfer(ctx, &msg, 1); > + if (ret < 0) > + return ret; > + > + return 0; > +} > + > +static int read_buf(void *ctx, > + int (*xfer)(void *ctx, struct i2c_msg *msgs, int num), > + uint8_t addr, int page, void *buf) > +{ > + uint8_t pos = 0; > + int ret; > + struct i2c_msg msg[2] = { > + { > + .addr = addr, > + .len = 1, > + .buf = &pos, > + }, { > + .addr = addr, > + .len = 256, > + .flags = I2C_M_RD, > + .buf = buf, > + } > + }; > + > + ret = select_page(ctx, xfer, page); > + if (ret < 0) > + return ret; > + > + ret = xfer(ctx, msg, 2); > + if (ret < 0) > + return ret; > + > + return 0; > +} > + > +/** > + * spd_read_eeprom - Read contents of a SPD EEPROM > + * @ctx: Context pointer for the xfer function > + * @xfer: I2C message transfer function > + * @addr: I2C bus address for the EEPROM > + * @buf: buffer to read the SPD data to It is not obvious what buffer size to provide here. And if it happens to be SPD_MEMTYPE_DDR4 then we suddenly start to write data at offset 256 in the buffer. So maybe add a small comment that this should always be 512 bytes. Or even better 2 x SPD_PAGE_SIZE (defined to 256) > + * > + * This function takes a I2C message transfer function and reads the contents > + * from a SPD EEPROM to the buffer provided at @buf. Returns 0 for success or a > + * negative error code otherwise. > + */ > +int spd_read_eeprom(void *ctx, > + int (*xfer)(void *ctx, struct i2c_msg *msgs, int num), > + uint8_t addr, void *buf) > +{ > + unsigned char *buf8 = buf; > + int ret; > + > + ret = read_buf(ctx, xfer, addr, SPD_SPA0_ADDRESS, buf); > + if (ret < 0) > + return ret; > + > + if (buf8[2] == SPD_MEMTYPE_DDR4) { > + ret = read_buf(ctx, xfer, addr, SPD_SPA1_ADDRESS, buf + 256); > + if (ret < 0) > + return ret; > + } > + > + return 0; > +} > diff --git a/include/ddr_spd.h b/include/ddr_spd.h > index 051275141f..95d0eb04b6 100644 > --- a/include/ddr_spd.h > +++ b/include/ddr_spd.h > @@ -6,6 +6,8 @@ > #ifndef _DDR_SPD_H_ > #define _DDR_SPD_H_ > > +#include <i2c/i2c.h> > + > /* > * Format from "JEDEC Standard No. 21-C, > * Appendix D: Rev 1.0: SPD's for DDR SDRAM > @@ -562,4 +564,8 @@ void ddr2_spd_dump(const struct ddr2_spd_eeprom *spd); > int ddr3_spd_check(const struct ddr3_spd_eeprom *spd); > int ddr4_spd_check(const struct ddr4_spd_eeprom *spd); > > +int spd_read_eeprom(void *ctx, > + int (*xfer)(void *ctx, struct i2c_msg *msgs, int num), > + uint8_t addr, void *buf); > + > #endif /* _DDR_SPD_H_ */ > -- > 2.20.1 > > > _______________________________________________ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 4/6] ddr_spd: Add function to read eeprom 2019-03-04 12:02 ` Sam Ravnborg @ 2019-03-04 13:22 ` Sascha Hauer 0 siblings, 0 replies; 12+ messages in thread From: Sascha Hauer @ 2019-03-04 13:22 UTC (permalink / raw) To: Sam Ravnborg; +Cc: Barebox List Hi Sam, On Mon, Mar 04, 2019 at 01:02:52PM +0100, Sam Ravnborg wrote: > Hi Sascha > > On Mon, Mar 04, 2019 at 12:38:21PM +0100, Sascha Hauer wrote: > > +/** > > + * spd_read_eeprom - Read contents of a SPD EEPROM > > + * @ctx: Context pointer for the xfer function > > + * @xfer: I2C message transfer function > > + * @addr: I2C bus address for the EEPROM > > + * @buf: buffer to read the SPD data to > It is not obvious what buffer size to provide here. > And if it happens to be SPD_MEMTYPE_DDR4 then we suddenly start to > write data at offset 256 in the buffer. > So maybe add a small comment that this should always be 512 bytes. > Or even better 2 x SPD_PAGE_SIZE (defined to 256) Make sense, I added such a comment. Thanks Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 5/6] ddr_spd: provide common SPD type 2019-03-04 11:38 [PATCH 0/6] SPD EEPROM improvements Sascha Hauer ` (3 preceding siblings ...) 2019-03-04 11:38 ` [PATCH 4/6] ddr_spd: Add function to read eeprom Sascha Hauer @ 2019-03-04 11:38 ` Sascha Hauer 2019-03-04 11:38 ` [PATCH 6/6] ddr_spd: Enable in PBL Sascha Hauer 5 siblings, 0 replies; 12+ messages in thread From: Sascha Hauer @ 2019-03-04 11:38 UTC (permalink / raw) To: Barebox List Provide a common struct type for the different SPD EEPROM types. Can be used to pass around SPD data without specifying the DDR type. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- include/ddr_spd.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/ddr_spd.h b/include/ddr_spd.h index 95d0eb04b6..6e63d90e5e 100644 --- a/include/ddr_spd.h +++ b/include/ddr_spd.h @@ -499,6 +499,16 @@ struct ddr4_spd_eeprom { uint8_t user[512-384]; /* 384~511 End User Programmable */ }; +struct spd_eeprom { + union { + struct ddr1_spd_eeprom ddr1; + struct ddr2_spd_eeprom ddr2; + struct ddr3_spd_eeprom ddr3; + struct ddr4_spd_eeprom ddr4; + uint8_t data[512]; + }; +}; + /* * Byte 2 Fundamental Memory Types. */ -- 2.20.1 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 6/6] ddr_spd: Enable in PBL 2019-03-04 11:38 [PATCH 0/6] SPD EEPROM improvements Sascha Hauer ` (4 preceding siblings ...) 2019-03-04 11:38 ` [PATCH 5/6] ddr_spd: provide common SPD type Sascha Hauer @ 2019-03-04 11:38 ` Sascha Hauer 5 siblings, 0 replies; 12+ messages in thread From: Sascha Hauer @ 2019-03-04 11:38 UTC (permalink / raw) To: Barebox List SPD EEPROMs are typically needed in PBL when the SDRAM is not yet initialized. Enable compilation of the SPD support in PBL. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- common/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/Makefile b/common/Makefile index b617642242..a284655fc1 100644 --- a/common/Makefile +++ b/common/Makefile @@ -24,7 +24,7 @@ obj-$(CONFIG_COMMAND_SUPPORT) += command.o obj-$(CONFIG_CONSOLE_FULL) += console.o obj-$(CONFIG_CONSOLE_SIMPLE) += console_simple.o obj-y += console_countdown.o -obj-$(CONFIG_DDR_SPD) += ddr_spd.o +obj-pbl-$(CONFIG_DDR_SPD) += ddr_spd.o obj-$(CONFIG_ENV_HANDLING) += environment.o obj-$(CONFIG_ENVIRONMENT_VARIABLES) += env.o obj-$(CONFIG_FILETYPE) += filetype.o -- 2.20.1 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply related [flat|nested] 12+ messages in thread
end of thread, other threads:[~2019-03-04 13:22 UTC | newest] Thread overview: 12+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-03-04 11:38 [PATCH 0/6] SPD EEPROM improvements Sascha Hauer 2019-03-04 11:38 ` [PATCH 1/6] crc: import crc_itu_t() from kernel Sascha Hauer 2019-03-04 11:50 ` Sam Ravnborg 2019-03-04 13:19 ` Sascha Hauer 2019-03-04 11:38 ` [PATCH 2/6] crc: Add PBL variant for crc_itu_t() Sascha Hauer 2019-03-04 11:38 ` [PATCH 3/6] ddr_spd: Update from U-Boot Sascha Hauer 2019-03-04 11:38 ` [PATCH 4/6] ddr_spd: Add function to read eeprom Sascha Hauer 2019-03-04 11:53 ` Sam Ravnborg 2019-03-04 12:02 ` Sam Ravnborg 2019-03-04 13:22 ` Sascha Hauer 2019-03-04 11:38 ` [PATCH 5/6] ddr_spd: provide common SPD type Sascha Hauer 2019-03-04 11:38 ` [PATCH 6/6] ddr_spd: Enable in PBL Sascha Hauer
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