From: Sven Schnelle <svens@stackframe.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, Sven Schnelle <svens@stackframe.org>,
Richard Henderson <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH 09/11] target/hppa: add TLB protection id check
Date: Mon, 11 Mar 2019 20:16:00 +0100 [thread overview]
Message-ID: <20190311191602.25796-10-svens@stackframe.org> (raw)
In-Reply-To: <20190311191602.25796-1-svens@stackframe.org>
Signed-off-by: Sven Schnelle <svens@stackframe.org>
---
target/hppa/cpu.h | 4 ++++
target/hppa/mem_helper.c | 28 ++++++++++++++++++++++++++--
2 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 861bbb1f16..d808796ee3 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -143,6 +143,10 @@
#endif
#define CR_RC 0
+#define CR_PID1 8
+#define CR_PID2 9
+#define CR_PID3 12
+#define CR_PID4 13
#define CR_SCRCCR 10
#define CR_SAR 11
#define CR_IVA 14
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index fc1b6a4fcd..a52d691d15 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -85,7 +85,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
int type, hwaddr *pphys, int *pprot)
{
hwaddr phys;
- int prot, r_prot, w_prot, x_prot;
+ int prot, r_prot, w_prot, x_prot, wd;
hppa_tlb_entry *ent;
int ret = -1;
@@ -130,7 +130,31 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
break;
}
- /* ??? Check PSW_P and ent->access_prot. This can remove PAGE_WRITE. */
+ /* access_id == 0 means public page and no check is performed */
+ if ((env->psw & PSW_P) && ent->access_id) {
+ wd = 1;
+
+ if (ent->access_id == (env->cr[CR_PID1] >> 1)) {
+ wd &= env->cr[CR_PID1];
+ }
+
+ if (ent->access_id == (env->cr[CR_PID2] >> 1)) {
+ wd &= env->cr[CR_PID2];
+ }
+
+ if (ent->access_id == (env->cr[CR_PID3] >> 1)) {
+ wd &= env->cr[CR_PID3];
+ }
+
+ if (ent->access_id == (env->cr[CR_PID4] >> 1)) {
+ wd &= env->cr[CR_PID4];
+ }
+
+ if (wd && (type & w_prot)) {
+ ret = EXCP_DMPI;
+ goto egress;
+ }
+ }
/* No guest access type indicates a non-architectural access from
within QEMU. Bypass checks for access, D, B and T bits. */
--
2.20.1
next prev parent reply other threads:[~2019-03-11 19:28 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-11 19:15 [Qemu-devel] [PATCH 00/11] target/hppa patches Sven Schnelle
2019-03-11 19:15 ` [Qemu-devel] [PATCH 01/11] target/hppa: fix overwriting source reg in addb Sven Schnelle
2019-03-12 3:24 ` Richard Henderson
2019-03-11 19:15 ` [Qemu-devel] [PATCH 02/11] target/hppa: fix TLB handling for page 0 Sven Schnelle
2019-03-12 3:24 ` Richard Henderson
2019-03-11 19:15 ` [Qemu-devel] [PATCH 03/11] target/hppa: report ITLB_EXCP_MISS for ITLB misses Sven Schnelle
2019-03-12 3:26 ` Richard Henderson
2019-03-11 19:15 ` [Qemu-devel] [PATCH 04/11] target/hppa: add TLB trace events Sven Schnelle
2019-03-12 3:26 ` Richard Henderson
2019-03-11 19:15 ` [Qemu-devel] [PATCH 05/11] target/hppa: remove PSW I/R/Q bit check Sven Schnelle
2019-03-12 3:26 ` Richard Henderson
2019-03-11 19:15 ` [Qemu-devel] [PATCH 06/11] target/hppa: ignore DIAG opcode Sven Schnelle
2019-03-12 0:22 ` Richard Henderson
2019-03-11 19:15 ` [Qemu-devel] [PATCH 07/11] target/hppa: fix b,gate instruction Sven Schnelle
2019-03-12 1:17 ` Richard Henderson
2019-03-11 19:15 ` [Qemu-devel] [PATCH 08/11] target/hppa: allow multiple itlbp without itlba Sven Schnelle
2019-03-12 1:22 ` Richard Henderson
2019-03-11 19:16 ` Sven Schnelle [this message]
2019-03-12 3:23 ` [Qemu-devel] [PATCH 09/11] target/hppa: add TLB protection id check Richard Henderson
2019-03-11 19:16 ` [Qemu-devel] [PATCH 10/11] target/hppa: exit TB if either Data or Instruction TLB changes Sven Schnelle
2019-03-12 3:27 ` Richard Henderson
2019-03-11 19:16 ` [Qemu-devel] [PATCH 11/11] target/hppa: call eval_interrupt() after ssm Sven Schnelle
2019-03-12 3:28 ` Richard Henderson
2019-03-12 4:01 ` Richard Henderson
2019-03-11 19:48 ` [Qemu-devel] [PATCH 00/11] target/hppa patches no-reply
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