From: Rob Herring <robh@kernel.org>
To: Vishal Sagar <vishal.sagar@xilinx.com>
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
Dinesh Kumar <dineshk@xilinx.com>, Hyun Kwon <hyunk@xilinx.com>,
Sandip Kothari <sandipk@xilinx.com>,
linux-kernel@vger.kernel.org, robh+dt@kernel.org,
Michal Simek <michals@xilinx.com>,
laurent.pinchart@ideasonboard.com, sakari.ailus@linux.intel.com,
Vishal Sagar <vishal.sagar@xilinx.com>,
hans.verkuil@cisco.com, mchehab@kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-media@vger.kernel.org
Subject: Re: [PATCH v5 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem
Date: Mon, 11 Mar 2019 17:41:40 -0500 [thread overview]
Message-ID: <20190311224140.GA23484@bogus> (raw)
In-Reply-To: <1552297257-145919-2-git-send-email-vishal.sagar@xilinx.com>
On Mon, 11 Mar 2019 15:10:56 +0530, Vishal Sagar wrote:
> Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.
>
> The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a
> DPHY in Rx mode, an optional I2C controller and a Video Format Bridge.
>
> Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
> ---
> v5
> - Incorporated comments by Luca Cersoli
> - Removed DPHY clock from description and example
> - Removed bayer pattern from device tree MIPI CSI IP
> doesn't deal with bayer pattern.
>
> v4
> - Added reviewed by Hyun Kwon
>
> v3
> - removed interrupt parent as suggested by Rob
> - removed dphy clock
> - moved vfb to optional properties
> - Added required and optional port properties section
> - Added endpoint property section
>
> v2
> - updated the compatible string to latest version supported
> - removed DPHY related parameters
> - added CSI v2.0 related property (including VCX for supporting upto 16
> virtual channels).
> - modified csi-pxl-format from string to unsigned int type where the value
> is as per the CSI specification
> - Defined port 0 and port 1 as sink and source ports.
> - Removed max-lanes property as suggested by Rob and Sakari
>
> .../bindings/media/xilinx/xlnx,csi2rxss.txt | 118 +++++++++++++++++++++
> 1 file changed, 118 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
>
Reviewed-by: Rob Herring <robh@kernel.org>
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WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
Cc: Hyun Kwon <hyunk@xilinx.com>,
laurent.pinchart@ideasonboard.com, mchehab@kernel.org,
robh+dt@kernel.org, mark.rutland@arm.com,
Michal Simek <michals@xilinx.com>,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
sakari.ailus@linux.intel.com, hans.verkuil@cisco.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Dinesh Kumar <dineshk@xilinx.com>,
Sandip Kothari <sandipk@xilinx.com>,
Vishal Sagar <vishal.sagar@xilinx.com>
Subject: Re: [PATCH v5 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem
Date: Mon, 11 Mar 2019 17:41:40 -0500 [thread overview]
Message-ID: <20190311224140.GA23484@bogus> (raw)
In-Reply-To: <1552297257-145919-2-git-send-email-vishal.sagar@xilinx.com>
On Mon, 11 Mar 2019 15:10:56 +0530, Vishal Sagar wrote:
> Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.
>
> The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a
> DPHY in Rx mode, an optional I2C controller and a Video Format Bridge.
>
> Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
> ---
> v5
> - Incorporated comments by Luca Cersoli
> - Removed DPHY clock from description and example
> - Removed bayer pattern from device tree MIPI CSI IP
> doesn't deal with bayer pattern.
>
> v4
> - Added reviewed by Hyun Kwon
>
> v3
> - removed interrupt parent as suggested by Rob
> - removed dphy clock
> - moved vfb to optional properties
> - Added required and optional port properties section
> - Added endpoint property section
>
> v2
> - updated the compatible string to latest version supported
> - removed DPHY related parameters
> - added CSI v2.0 related property (including VCX for supporting upto 16
> virtual channels).
> - modified csi-pxl-format from string to unsigned int type where the value
> is as per the CSI specification
> - Defined port 0 and port 1 as sink and source ports.
> - Removed max-lanes property as suggested by Rob and Sakari
>
> .../bindings/media/xilinx/xlnx,csi2rxss.txt | 118 +++++++++++++++++++++
> 1 file changed, 118 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
>
Reviewed-by: Rob Herring <robh@kernel.org>
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Vishal Sagar <vishal.sagar@xilinx.com>
Cc: Hyun Kwon <hyunk@xilinx.com>,
laurent.pinchart@ideasonboard.com, mchehab@kernel.org,
robh+dt@kernel.org, mark.rutland@arm.com,
Michal Simek <michals@xilinx.com>,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
sakari.ailus@linux.intel.com, hans.verkuil@cisco.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Dinesh Kumar <dineshk@xilinx.com>,
Sandip Kothari <sandipk@xilinx.com>,
Vishal Sagar <vishal.sagar@xilinx.com>
Subject: Re: [PATCH v5 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem
Date: Mon, 11 Mar 2019 17:41:40 -0500 [thread overview]
Message-ID: <20190311224140.GA23484@bogus> (raw)
In-Reply-To: <1552297257-145919-2-git-send-email-vishal.sagar@xilinx.com>
On Mon, 11 Mar 2019 15:10:56 +0530, Vishal Sagar wrote:
> Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.
>
> The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a
> DPHY in Rx mode, an optional I2C controller and a Video Format Bridge.
>
> Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
> ---
> v5
> - Incorporated comments by Luca Cersoli
> - Removed DPHY clock from description and example
> - Removed bayer pattern from device tree MIPI CSI IP
> doesn't deal with bayer pattern.
>
> v4
> - Added reviewed by Hyun Kwon
>
> v3
> - removed interrupt parent as suggested by Rob
> - removed dphy clock
> - moved vfb to optional properties
> - Added required and optional port properties section
> - Added endpoint property section
>
> v2
> - updated the compatible string to latest version supported
> - removed DPHY related parameters
> - added CSI v2.0 related property (including VCX for supporting upto 16
> virtual channels).
> - modified csi-pxl-format from string to unsigned int type where the value
> is as per the CSI specification
> - Defined port 0 and port 1 as sink and source ports.
> - Removed max-lanes property as suggested by Rob and Sakari
>
> .../bindings/media/xilinx/xlnx,csi2rxss.txt | 118 +++++++++++++++++++++
> 1 file changed, 118 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
>
Reviewed-by: Rob Herring <robh@kernel.org>
next prev parent reply other threads:[~2019-03-11 22:41 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-11 9:40 [PATCH v5 0/2] Add support for Xilinx CSI2 Receiver Subsystem Vishal Sagar
2019-03-11 9:40 ` Vishal Sagar
2019-03-11 9:40 ` Vishal Sagar
2019-03-11 9:40 ` [PATCH v5 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem Vishal Sagar
2019-03-11 9:40 ` Vishal Sagar
2019-03-11 9:40 ` Vishal Sagar
2019-03-11 22:41 ` Rob Herring [this message]
2019-03-11 22:41 ` Rob Herring
2019-03-11 22:41 ` Rob Herring
2019-03-12 4:38 ` Vishal Sagar
2019-03-12 4:38 ` Vishal Sagar
2019-03-12 4:38 ` Vishal Sagar
2019-03-11 9:40 ` [PATCH v5 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver Vishal Sagar
2019-03-11 9:40 ` Vishal Sagar
2019-03-11 9:40 ` Vishal Sagar
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