From: Marek Behun <marek.behun@nic.cz>
To: Christian Lamparter <chunkeey@gmail.com>
Cc: "Florian Fainelli" <f.fainelli@gmail.com>,
netdev@vger.kernel.org, "Andrew Lunn" <andrew@lunn.ch>,
"Michal Vokáč" <vokac.m@gmail.com>,
"John Crispin" <john@phrozen.org>,
"Wei Yongjun" <weiyongjun1@huawei.com>
Subject: Re: [PATCH net-next 1/1] net: dsa: qca8k: Fix internal PHY MDIO address
Date: Fri, 22 Mar 2019 00:01:20 +0100 [thread overview]
Message-ID: <20190322000120.7a87fde5@nic.cz> (raw)
In-Reply-To: <2275278.j5OWp99DLc@debian64>
> Hm, it's not really a "external mode". But let's try one more time.
> The idea is that if an external mdio-bus (from the SoC) has already
> registered the PHY 0x0 - 0x4 from the QCA8337, the qca8k should not
> expose the same PHYs as it's own mdio-bus because then the PHYs end
> up being registered twice.
Hi,
yes, I understand this bit. What I was talking about was that the MDIO
addresses of internal PHYs are 0 to 4, it does not matter if you access
them via switch or directly. But the current code for direct access is
using addresses 1 to 5, which does not work at all. It should also
substract 1 from the port number.
Marek
next prev parent reply other threads:[~2019-03-21 23:01 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-21 18:23 [PATCH net-next 1/1] net: dsa: qca8k: Fix internal PHY MDIO address Marek Behún
2019-03-21 18:26 ` Florian Fainelli
2019-03-21 19:55 ` Marek Behun
2019-03-21 22:24 ` Christian Lamparter
2019-03-21 23:01 ` Marek Behun [this message]
2019-03-22 0:05 ` Christian Lamparter
2019-03-25 17:51 ` Christian Lamparter
2019-03-25 19:34 ` Marek Behun
2019-03-21 19:56 ` Christian Lamparter
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