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From: Joseph Lo <josephl@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-tegra@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Joseph Lo <josephl@nvidia.com>
Subject: [PATCH 2/2] arm64: tegra: Enable DFLL clock on Shield platform
Date: Fri, 22 Mar 2019 15:11:11 +0800	[thread overview]
Message-ID: <20190322071111.32432-2-josephl@nvidia.com> (raw)
In-Reply-To: <20190322071111.32432-1-josephl@nvidia.com>

Enable DFLL clock on Shield platform.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
 .../arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi
index c668f16c8574..5385816a83a9 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi
@@ -1600,6 +1600,27 @@
 		status = "okay";
 	};
 
+	clock@70110000 {
+		status = "okay";
+
+		nvidia,cf = <6>;
+		nvidia,ci = <0>;
+		nvidia,cg = <2>;
+		nvidia,droop-ctrl = <0x00000f00>;
+		nvidia,force-mode = <1>;
+		nvidia,sample-rate = <25000>;
+
+		nvidia,pwm-min-microvolts = <708000>;
+		nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
+		nvidia,pwm-to-pmic;
+		nvidia,pwm-tristate-microvolts = <1000000>;
+		nvidia,pwm-voltage-step-microvolts = <19200>;
+
+		pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
+		pinctrl-0 = <&dvfs_pwm_active_state>;
+		pinctrl-1 = <&dvfs_pwm_inactive_state>;
+	};
+
 	clocks {
 		compatible = "simple-bus";
 		#address-cells = <1>;
-- 
2.21.0

WARNING: multiple messages have this Message-ID (diff)
From: Joseph Lo <josephl@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-tegra@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Joseph Lo <josephl@nvidia.com>
Subject: [PATCH 2/2] arm64: tegra: Enable DFLL clock on Shield platform
Date: Fri, 22 Mar 2019 15:11:11 +0800	[thread overview]
Message-ID: <20190322071111.32432-2-josephl@nvidia.com> (raw)
In-Reply-To: <20190322071111.32432-1-josephl@nvidia.com>

Enable DFLL clock on Shield platform.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
 .../arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi
index c668f16c8574..5385816a83a9 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi
@@ -1600,6 +1600,27 @@
 		status = "okay";
 	};
 
+	clock@70110000 {
+		status = "okay";
+
+		nvidia,cf = <6>;
+		nvidia,ci = <0>;
+		nvidia,cg = <2>;
+		nvidia,droop-ctrl = <0x00000f00>;
+		nvidia,force-mode = <1>;
+		nvidia,sample-rate = <25000>;
+
+		nvidia,pwm-min-microvolts = <708000>;
+		nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
+		nvidia,pwm-to-pmic;
+		nvidia,pwm-tristate-microvolts = <1000000>;
+		nvidia,pwm-voltage-step-microvolts = <19200>;
+
+		pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
+		pinctrl-0 = <&dvfs_pwm_active_state>;
+		pinctrl-1 = <&dvfs_pwm_inactive_state>;
+	};
+
 	clocks {
 		compatible = "simple-bus";
 		#address-cells = <1>;
-- 
2.21.0


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  reply	other threads:[~2019-03-22  7:11 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-22  7:11 [PATCH 1/2] arm64: tegra: Add pinmux for PWM-based DFLL support on Shield platform Joseph Lo
2019-03-22  7:11 ` Joseph Lo
2019-03-22  7:11 ` Joseph Lo [this message]
2019-03-22  7:11   ` [PATCH 2/2] arm64: tegra: Enable DFLL clock " Joseph Lo
2019-03-22  9:52 ` [PATCH 1/2] arm64: tegra: Add pinmux for PWM-based DFLL support " Thierry Reding
2019-04-02  3:06   ` Joseph Lo
2019-04-02  3:06     ` Joseph Lo
2019-04-15  1:27     ` Joseph Lo

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