From: Rob Herring <robh@kernel.org>
To: Fabien Dessenne <fabien.dessenne@st.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@st.com>,
Ohad Ben-Cohen <ohad@wizery.com>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
devicetree@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org,
Loic Pallardy <loic.pallardy@st.com>,
Arnaud Pouliquen <arnaud.pouliquen@st.com>,
Ludovic Barre <ludovic.barre@st.com>,
Benjamin Gaignard <benjamin.gaignard@st.com>
Subject: Re: [PATCH 1/8] dt-bindings: stm32: add bindings for ML-AHB interconnect
Date: Wed, 27 Mar 2019 18:07:22 -0500 [thread overview]
Message-ID: <20190327230722.GA13708@bogus> (raw)
In-Reply-To: <1551795849-13672-2-git-send-email-fabien.dessenne@st.com>
On Tue, Mar 05, 2019 at 03:24:02PM +0100, Fabien Dessenne wrote:
> Document the ML-AHB interconnect for stm32 SoCs.
>
> Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
> ---
> .../devicetree/bindings/arm/stm32/mlahb.txt | 30 ++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/stm32/mlahb.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/stm32/mlahb.txt b/Documentation/devicetree/bindings/arm/stm32/mlahb.txt
> new file mode 100644
> index 0000000..880cb38
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/stm32/mlahb.txt
> @@ -0,0 +1,30 @@
> +ML-AHB interconnect bindings
> +
> +These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
> +a Cortex-M subsystem with dedicated memories.
> +
> +Required properties:
> +- compatible: should be "simple-bus"
A binding for simple-bus was the first thing that looked odd.
> +- ranges: describes memory addresses translation between the local CPU and the
> + remote Cortex-M processor. Each memory region, is declared with 3
> + parameters:
> + - param 1: device base address (Cortex-M processor address)
> + - param 2: physical base address (local CPU address)
> + - param 3: size of the memory region.
Given that the driver is parsing ranges itself, this looks like abuse of
ranges.
What exactly is address 0 supposed to be here? If it is the M4's view of
memory, then dma-ranges is what you want to use here.
> +
> +The Cortex-M remote processor accessed via the mlahb interconnect is described
> +by a child node.
> +
> +Example:
> +mlahb: mlahb@0 {
Note that the unit-address is wrong here as it should be 38000000.
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x00000000 0x38000000 0x10000>,
> + <0x10000000 0x10000000 0x60000>,
> + <0x30000000 0x30000000 0x60000>;
> +
> + m4_rproc: m4@0 {
> + ...
> + };
> +};
> --
> 2.7.4
>
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Fabien Dessenne <fabien.dessenne@st.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
Ohad Ben-Cohen <ohad@wizery.com>,
Alexandre Torgue <alexandre.torgue@st.com>,
Loic Pallardy <loic.pallardy@st.com>,
devicetree@vger.kernel.org,
Arnaud Pouliquen <arnaud.pouliquen@st.com>,
linux-remoteproc@vger.kernel.org, linux-kernel@vger.kernel.org,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Ludovic Barre <ludovic.barre@st.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org,
Benjamin Gaignard <benjamin.gaignard@st.com>
Subject: Re: [PATCH 1/8] dt-bindings: stm32: add bindings for ML-AHB interconnect
Date: Wed, 27 Mar 2019 18:07:22 -0500 [thread overview]
Message-ID: <20190327230722.GA13708@bogus> (raw)
In-Reply-To: <1551795849-13672-2-git-send-email-fabien.dessenne@st.com>
On Tue, Mar 05, 2019 at 03:24:02PM +0100, Fabien Dessenne wrote:
> Document the ML-AHB interconnect for stm32 SoCs.
>
> Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
> ---
> .../devicetree/bindings/arm/stm32/mlahb.txt | 30 ++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/stm32/mlahb.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/stm32/mlahb.txt b/Documentation/devicetree/bindings/arm/stm32/mlahb.txt
> new file mode 100644
> index 0000000..880cb38
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/stm32/mlahb.txt
> @@ -0,0 +1,30 @@
> +ML-AHB interconnect bindings
> +
> +These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
> +a Cortex-M subsystem with dedicated memories.
> +
> +Required properties:
> +- compatible: should be "simple-bus"
A binding for simple-bus was the first thing that looked odd.
> +- ranges: describes memory addresses translation between the local CPU and the
> + remote Cortex-M processor. Each memory region, is declared with 3
> + parameters:
> + - param 1: device base address (Cortex-M processor address)
> + - param 2: physical base address (local CPU address)
> + - param 3: size of the memory region.
Given that the driver is parsing ranges itself, this looks like abuse of
ranges.
What exactly is address 0 supposed to be here? If it is the M4's view of
memory, then dma-ranges is what you want to use here.
> +
> +The Cortex-M remote processor accessed via the mlahb interconnect is described
> +by a child node.
> +
> +Example:
> +mlahb: mlahb@0 {
Note that the unit-address is wrong here as it should be 38000000.
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x00000000 0x38000000 0x10000>,
> + <0x10000000 0x10000000 0x60000>,
> + <0x30000000 0x30000000 0x60000>;
> +
> + m4_rproc: m4@0 {
> + ...
> + };
> +};
> --
> 2.7.4
>
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next prev parent reply other threads:[~2019-03-27 23:07 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-05 14:24 [PATCH 0/8] stm32 m4 remoteproc on STM32MP157c Fabien Dessenne
2019-03-05 14:24 ` Fabien Dessenne
2019-03-05 14:24 ` Fabien Dessenne
2019-03-05 14:24 ` Fabien Dessenne
2019-03-05 14:24 ` [PATCH 1/8] dt-bindings: stm32: add bindings for ML-AHB interconnect Fabien Dessenne
2019-03-05 14:24 ` Fabien Dessenne
2019-03-05 14:24 ` Fabien Dessenne
2019-03-05 14:24 ` Fabien Dessenne
2019-03-27 23:07 ` Rob Herring [this message]
2019-03-27 23:07 ` Rob Herring
2019-03-29 15:59 ` Fabien DESSENNE
2019-03-29 15:59 ` Fabien DESSENNE
2019-04-04 1:29 ` Rob Herring
2019-04-04 1:29 ` Rob Herring
2019-04-04 1:29 ` Rob Herring
2019-03-05 14:24 ` [PATCH 2/8] dt-bindings: remoteproc: add bindings for stm32 remote processor driver Fabien Dessenne
2019-03-05 14:24 ` Fabien Dessenne
2019-03-05 14:24 ` Fabien Dessenne
2019-03-27 23:23 ` Rob Herring
2019-03-27 23:23 ` Rob Herring
2019-03-05 14:24 ` [PATCH 3/8] remoteproc: stm32: add an ST stm32_rproc driver Fabien Dessenne
2019-03-05 14:24 ` Fabien Dessenne
2019-03-05 14:24 ` Fabien Dessenne
2019-03-05 14:24 ` [PATCH 4/8] ARM: dts: stm32: add m4 remoteproc support on STM32MP157c Fabien Dessenne
2019-03-05 14:24 ` Fabien Dessenne
2019-03-05 14:24 ` Fabien Dessenne
2019-03-05 14:24 ` Fabien Dessenne
2019-03-05 14:24 ` [PATCH 5/8] ARM: dts: stm32: declare copro reserved memories on STM32MP157c-ed1 Fabien Dessenne
2019-03-05 14:24 ` Fabien Dessenne
2019-03-05 14:24 ` Fabien Dessenne
2019-03-05 14:24 ` [PATCH 6/8] ARM: dts: stm32: enable m4 coprocessor support " Fabien Dessenne
2019-03-05 14:24 ` Fabien Dessenne
2019-03-05 14:24 ` Fabien Dessenne
2019-03-05 14:24 ` [PATCH 7/8] ARM: dts: stm32: declare copro reserved memories on STM32MP157a-dk1 Fabien Dessenne
2019-03-05 14:24 ` Fabien Dessenne
2019-03-05 14:24 ` Fabien Dessenne
2019-03-05 14:24 ` [PATCH 8/8] ARM: dts: stm32: enable m4 coprocessor support " Fabien Dessenne
2019-03-05 14:24 ` Fabien Dessenne
2019-03-05 14:24 ` Fabien Dessenne
2019-03-26 10:37 ` [PATCH 0/8] stm32 m4 remoteproc on STM32MP157c Alexandre Torgue
2019-03-26 10:37 ` Alexandre Torgue
2019-03-26 10:37 ` Alexandre Torgue
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