[PATCH v2 3/3] mwait-idle: add enablement for AMD Naples and Rome

["Woods, Brian" <Brian.Woods@amd.com>]

From: Brian Woods <brian.woods@amd.com>

Add the needed data structures for enabling Naples (F17h M01h).  Since
Rome (F17h M31h) has the same c-state latencies and entry methods, the
c-state information can be used for Rome as well.  For both Naples and
Rome, mwait is used for c1 (cc1) and halt is functionally the same as
c2 (cc6).  If c2 (cc6) is disabled in BIOS, then halt functions similar
to c1 (cc1).

Signed-off-by: Brian Woods <brian.woods@amd.com>
---
 xen/arch/x86/cpu/mwait-idle.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c
index 58629f1c29..0d5d4caa4d 100644
--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -720,6 +720,22 @@ static const struct cpuidle_state dnv_cstates[] = {
 	{}
 };
 
+static const struct cpuidle_state naples_cstates[] = {
+	{
+		.name = "CC1",
+		.flags = MWAIT2flg(0x00),
+		.exit_latency = 1,
+		.target_residency = 2,
+	},
+	{
+		.name = "CC6",
+		.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_USE_HALT,
+		.exit_latency = 400,
+		.target_residency = 1000,
+	},
+	{}
+};
+
 static void mwait_idle(void)
 {
 	unsigned int cpu = smp_processor_id();
@@ -964,10 +980,16 @@ static const struct x86_cpu_id intel_idle_ids[] __initconstrel = {
 	{}
 };
 
+static const struct idle_cpu idle_cpu_naples = {
+	.state_table = naples_cstates,
+};
+
 #define ACPU(family, model, cpu) \
 	{ X86_VENDOR_AMD, family, model, X86_FEATURE_ALWAYS, &idle_cpu_##cpu}
 
 static const struct x86_cpu_id amd_idle_ids[] __initconstrel = {
+	ACPU(0x17, 0x01, naples),
+	ACPU(0x17, 0x31, naples), /* Rome shares the same c-state config */
 	{}
 };
 
-- 
2.11.0


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