[PATCH V7 0/8] Add CPUidle support for Tegra210

[PATCH V7 0/8] Add CPUidle support for Tegra210

[Joseph Lo]

This patch series adds CPUidle support for Tegra210, which supports
cpu-sleep state for CPU cores. And due to arch timer cannot work
across CPU core power-down and power on reset signal event. We introduce
Tegra210 timer driver to work as clock event device. So it can be the
wake-up source of CPU cores when they idled in the power-down state.

Fix in V7:
 * kconfig fix for 'depends on ARM || ARM64'
 * move suspend/resume to clkevt
 * refine the usage of the macro of TIMER_OF_DECLARE
 * update the 'entry/exit-latency-us' properties in the idle-states node
 * add one patch for Shield platform support

Fix in V6:
 * refine the timer defines in the timer driver (PATCH 2)
 * add ack tags from Jon Hunter.

Fixed in V5:
 * Just resend this whole series again with timer and Tegra maintainers
   included

Fixed in V4:
 * merge timer-tegra210.c into timer-tegra20.c
 * add a new patch to select TEGRA_TIMER by default for Tegra210

Fixed in V3:
 * use timer-of API for Tegra210 timer driver

Fixed in V2:
 * list all the timer IRQs in the binding doc and dts file
 * add error clean-up code in timer driver
 * add entry-latency-us and exit-latency-us properties for idle-states
   DT node

Joseph Lo (7):
  dt-bindings: timer: add Tegra210 timer
  clocksource: tegra: add Tegra210 timer support
  soc/tegra: default select TEGRA_TIMER for Tegra210
  arm64: tegra: fix timer node for Tegra210
  arm64: tegra: add CPU idle states properties for Tegra210
  arm64: tegra: Enable CPU idle support for Jetson TX1
  arm64: tegra: Enable CPU idle support for Smaug
  arm64: tegra: Enable CPU idle support for Shield

 .../bindings/timer/nvidia,tegra210-timer.txt  |  36 ++
 .../arm64/boot/dts/nvidia/tegra210-p2180.dtsi |   6 +
 .../arm64/boot/dts/nvidia/tegra210-p2894.dtsi |   6 +
 arch/arm64/boot/dts/nvidia/tegra210-smaug.dts |   7 +
 arch/arm64/boot/dts/nvidia/tegra210.dtsi      |  33 +-
 drivers/clocksource/Kconfig                   |   3 +-
 drivers/clocksource/timer-tegra20.c           | 370 ++++++++++++------
 drivers/soc/tegra/Kconfig                     |   1 +
 include/linux/cpuhotplug.h                    |   1 +
 9 files changed, 348 insertions(+), 115 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt

-- 
2.20.1

[PATCH V7 0/8] Add CPUidle support for Tegra210

[Joseph Lo]

This patch series adds CPUidle support for Tegra210, which supports
cpu-sleep state for CPU cores. And due to arch timer cannot work
across CPU core power-down and power on reset signal event. We introduce
Tegra210 timer driver to work as clock event device. So it can be the
wake-up source of CPU cores when they idled in the power-down state.

Fix in V7:
 * kconfig fix for 'depends on ARM || ARM64'
 * move suspend/resume to clkevt
 * refine the usage of the macro of TIMER_OF_DECLARE
 * update the 'entry/exit-latency-us' properties in the idle-states node
 * add one patch for Shield platform support

Fix in V6:
 * refine the timer defines in the timer driver (PATCH 2)
 * add ack tags from Jon Hunter.

Fixed in V5:
 * Just resend this whole series again with timer and Tegra maintainers
   included

Fixed in V4:
 * merge timer-tegra210.c into timer-tegra20.c
 * add a new patch to select TEGRA_TIMER by default for Tegra210

Fixed in V3:
 * use timer-of API for Tegra210 timer driver

Fixed in V2:
 * list all the timer IRQs in the binding doc and dts file
 * add error clean-up code in timer driver
 * add entry-latency-us and exit-latency-us properties for idle-states
   DT node

Joseph Lo (7):
  dt-bindings: timer: add Tegra210 timer
  clocksource: tegra: add Tegra210 timer support
  soc/tegra: default select TEGRA_TIMER for Tegra210
  arm64: tegra: fix timer node for Tegra210
  arm64: tegra: add CPU idle states properties for Tegra210
  arm64: tegra: Enable CPU idle support for Jetson TX1
  arm64: tegra: Enable CPU idle support for Smaug
  arm64: tegra: Enable CPU idle support for Shield

 .../bindings/timer/nvidia,tegra210-timer.txt  |  36 ++
 .../arm64/boot/dts/nvidia/tegra210-p2180.dtsi |   6 +
 .../arm64/boot/dts/nvidia/tegra210-p2894.dtsi |   6 +
 arch/arm64/boot/dts/nvidia/tegra210-smaug.dts |   7 +
 arch/arm64/boot/dts/nvidia/tegra210.dtsi      |  33 +-
 drivers/clocksource/Kconfig                   |   3 +-
 drivers/clocksource/timer-tegra20.c           | 370 ++++++++++++------
 drivers/soc/tegra/Kconfig                     |   1 +
 include/linux/cpuhotplug.h                    |   1 +
 9 files changed, 348 insertions(+), 115 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt

-- 
2.20.1


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[PATCH V7 1/8] dt-bindings: timer: add Tegra210 timer

[Joseph Lo]

The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit
timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived
from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock
(TMR10-TMR13). Each TMR can be programmed to generate one-shot periodic,
or watchdog interrupts.

Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
v7:
 * no change
v6:
 * add ack tag from Jon.
v5:
 * no change
v4:
 * no change
v3:
 * no change
v2:
 * list all the interrupts that are supported by tegra210 timers block
 * add RB tag from Rob.
---
 .../bindings/timer/nvidia,tegra210-timer.txt  | 36 +++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt

diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt
new file mode 100644
index 000000000000..032cda96fe0d
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt
@@ -0,0 +1,36 @@
+NVIDIA Tegra210 timer
+
+The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit
+timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived
+from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock
+(TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic,
+or watchdog interrupts.
+
+Required properties:
+- compatible : "nvidia,tegra210-timer".
+- reg : Specifies base physical address and size of the registers.
+- interrupts : A list of 14 interrupts; one per each timer channels 0 through
+  13.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
+
+timer@60005000 {
+	compatible = "nvidia,tegra210-timer";
+	reg = <0x0 0x60005000 0x0 0x400>;
+	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&tegra_car TEGRA210_CLK_TIMER>;
+	clock-names = "timer";
+};
-- 
2.20.1

[PATCH V7 1/8] dt-bindings: timer: add Tegra210 timer

[Joseph Lo]

The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit
timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived
from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock
(TMR10-TMR13). Each TMR can be programmed to generate one-shot periodic,
or watchdog interrupts.

Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
v7:
 * no change
v6:
 * add ack tag from Jon.
v5:
 * no change
v4:
 * no change
v3:
 * no change
v2:
 * list all the interrupts that are supported by tegra210 timers block
 * add RB tag from Rob.
---
 .../bindings/timer/nvidia,tegra210-timer.txt  | 36 +++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt

diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt
new file mode 100644
index 000000000000..032cda96fe0d
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt
@@ -0,0 +1,36 @@
+NVIDIA Tegra210 timer
+
+The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit
+timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived
+from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock
+(TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic,
+or watchdog interrupts.
+
+Required properties:
+- compatible : "nvidia,tegra210-timer".
+- reg : Specifies base physical address and size of the registers.
+- interrupts : A list of 14 interrupts; one per each timer channels 0 through
+  13.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
+
+timer@60005000 {
+	compatible = "nvidia,tegra210-timer";
+	reg = <0x0 0x60005000 0x0 0x400>;
+	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&tegra_car TEGRA210_CLK_TIMER>;
+	clock-names = "timer";
+};
-- 
2.20.1

[PATCH V7 1/8] dt-bindings: timer: add Tegra210 timer

[Joseph Lo]

The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit
timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived
from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock
(TMR10-TMR13). Each TMR can be programmed to generate one-shot periodic,
or watchdog interrupts.

Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
v7:
 * no change
v6:
 * add ack tag from Jon.
v5:
 * no change
v4:
 * no change
v3:
 * no change
v2:
 * list all the interrupts that are supported by tegra210 timers block
 * add RB tag from Rob.
---
 .../bindings/timer/nvidia,tegra210-timer.txt  | 36 +++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt

diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt
new file mode 100644
index 000000000000..032cda96fe0d
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt
@@ -0,0 +1,36 @@
+NVIDIA Tegra210 timer
+
+The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit
+timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived
+from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock
+(TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic,
+or watchdog interrupts.
+
+Required properties:
+- compatible : "nvidia,tegra210-timer".
+- reg : Specifies base physical address and size of the registers.
+- interrupts : A list of 14 interrupts; one per each timer channels 0 through
+  13.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
+
+timer@60005000 {
+	compatible = "nvidia,tegra210-timer";
+	reg = <0x0 0x60005000 0x0 0x400>;
+	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&tegra_car TEGRA210_CLK_TIMER>;
+	clock-names = "timer";
+};
-- 
2.20.1


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linux-arm-kernel@lists.infradead.org
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[PATCH V7 2/8] clocksource: tegra: add Tegra210 timer support

[Joseph Lo]

Add support for the Tegra210 timer that runs at oscillator clock
(TMR10-TMR13). We need these timers to work as clock event device and to
replace the ARMv8 architected timer due to it can't survive across the
power cycle of the CPU core or CPUPORESET signal. So it can't be a wake-up
source when CPU suspends in power down state.

Also convert the original driver to use timer-of API.

Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
v7:
 * kconfig fix for 'depends on ARM || ARM64'
 * move suspend/resume to clkevt
 * refine the usage for the macro of TIMER_OF_DECLARE
v6:
 * refine the timer defines
 * add ack tag from Jon.
v5:
 * add ack tag from Thierry
v4:
 * merge timer-tegra210.c in previous version into timer-tegra20.c
v3:
 * use timer-of API
v2:
 * add error clean-up code
---
 drivers/clocksource/Kconfig         |   3 +-
 drivers/clocksource/timer-tegra20.c | 370 +++++++++++++++++++---------
 include/linux/cpuhotplug.h          |   1 +
 3 files changed, 262 insertions(+), 112 deletions(-)

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 8dfd3bc448d0..5d93e580e5dc 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -131,7 +131,8 @@ config SUN5I_HSTIMER
 config TEGRA_TIMER
 	bool "Tegra timer driver" if COMPILE_TEST
 	select CLKSRC_MMIO
-	depends on ARM
+	select TIMER_OF
+	depends on ARM || ARM64
 	help
 	  Enables support for the Tegra driver.
 
diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c
index 4293943f4e2b..fdb3d795a409 100644
--- a/drivers/clocksource/timer-tegra20.c
+++ b/drivers/clocksource/timer-tegra20.c
@@ -15,21 +15,24 @@
  *
  */
 
-#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/cpu.h>
+#include <linux/cpumask.h>
+#include <linux/delay.h>
 #include <linux/err.h>
-#include <linux/time.h>
 #include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/clockchips.h>
-#include <linux/clocksource.h>
-#include <linux/clk.h>
-#include <linux/io.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <linux/percpu.h>
 #include <linux/sched_clock.h>
-#include <linux/delay.h>
+#include <linux/time.h>
+
+#include "timer-of.h"
 
+#ifdef CONFIG_ARM
 #include <asm/mach/time.h>
+#endif
 
 #define RTC_SECONDS            0x08
 #define RTC_SHADOW_SECONDS     0x0c
@@ -39,74 +42,161 @@
 #define TIMERUS_USEC_CFG 0x14
 #define TIMERUS_CNTR_FREEZE 0x4c
 
-#define TIMER1_BASE 0x0
-#define TIMER2_BASE 0x8
-#define TIMER3_BASE 0x50
-#define TIMER4_BASE 0x58
-
-#define TIMER_PTV 0x0
-#define TIMER_PCR 0x4
-
+#define TIMER_PTV		0x0
+#define TIMER_PTV_EN		BIT(31)
+#define TIMER_PTV_PER		BIT(30)
+#define TIMER_PCR		0x4
+#define TIMER_PCR_INTR_CLR	BIT(30)
+
+#ifdef CONFIG_ARM
+#define TIMER_CPU0		0x50 /* TIMER3 */
+#else
+#define TIMER_CPU0		0x90 /* TIMER10 */
+#define TIMER10_IRQ_IDX		10
+#define IRQ_IDX_FOR_CPU(cpu)	(TIMER10_IRQ_IDX + cpu)
+#endif
+#define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8)
+
+static u32 usec_config;
 static void __iomem *timer_reg_base;
+#ifdef CONFIG_ARM
 static void __iomem *rtc_base;
-
 static struct timespec64 persistent_ts;
 static u64 persistent_ms, last_persistent_ms;
-
 static struct delay_timer tegra_delay_timer;
-
-#define timer_writel(value, reg) \
-	writel_relaxed(value, timer_reg_base + (reg))
-#define timer_readl(reg) \
-	readl_relaxed(timer_reg_base + (reg))
+#endif
 
 static int tegra_timer_set_next_event(unsigned long cycles,
 					 struct clock_event_device *evt)
 {
-	u32 reg;
+	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
 
-	reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
-	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
+	writel(TIMER_PTV_EN |
+	       ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
+	       reg_base + TIMER_PTV);
 
 	return 0;
 }
 
-static inline void timer_shutdown(struct clock_event_device *evt)
+static int tegra_timer_shutdown(struct clock_event_device *evt)
 {
-	timer_writel(0, TIMER3_BASE + TIMER_PTV);
+	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
+
+	writel(0, reg_base + TIMER_PTV);
+
+	return 0;
 }
 
-static int tegra_timer_shutdown(struct clock_event_device *evt)
+static int tegra_timer_set_periodic(struct clock_event_device *evt)
 {
-	timer_shutdown(evt);
+	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
+
+	writel(TIMER_PTV_EN | TIMER_PTV_PER |
+	       ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
+	       reg_base + TIMER_PTV);
+
 	return 0;
 }
 
-static int tegra_timer_set_periodic(struct clock_event_device *evt)
+static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
+	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
+
+	writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
+	evt->event_handler(evt);
+
+	return IRQ_HANDLED;
+}
+
+static void tegra_timer_suspend(struct clock_event_device *evt)
+{
+	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
+
+	writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
+}
+
+static void tegra_timer_resume(struct clock_event_device *evt)
+{
+	writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
+}
+
+#ifdef CONFIG_ARM64
+static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
+	.flags = TIMER_OF_CLOCK | TIMER_OF_BASE,
+
+	.clkevt = {
+		.name = "tegra_timer",
+		.rating = 460,
+		.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
+		.set_next_event = tegra_timer_set_next_event,
+		.set_state_shutdown = tegra_timer_shutdown,
+		.set_state_periodic = tegra_timer_set_periodic,
+		.set_state_oneshot = tegra_timer_shutdown,
+		.tick_resume = tegra_timer_shutdown,
+		.suspend = tegra_timer_suspend,
+		.resume = tegra_timer_resume,
+	},
+};
+
+static int tegra_timer_setup(unsigned int cpu)
 {
-	u32 reg = 0xC0000000 | ((1000000 / HZ) - 1);
+	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
+
+	irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
+	enable_irq(to->clkevt.irq);
+
+	clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
+					1, /* min */
+					0x1fffffff); /* 29 bits */
 
-	timer_shutdown(evt);
-	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
 	return 0;
 }
 
-static struct clock_event_device tegra_clockevent = {
-	.name			= "timer0",
-	.rating			= 300,
-	.features		= CLOCK_EVT_FEAT_ONESHOT |
-				  CLOCK_EVT_FEAT_PERIODIC |
-				  CLOCK_EVT_FEAT_DYNIRQ,
-	.set_next_event		= tegra_timer_set_next_event,
-	.set_state_shutdown	= tegra_timer_shutdown,
-	.set_state_periodic	= tegra_timer_set_periodic,
-	.set_state_oneshot	= tegra_timer_shutdown,
-	.tick_resume		= tegra_timer_shutdown,
+static int tegra_timer_stop(unsigned int cpu)
+{
+	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
+
+	to->clkevt.set_state_shutdown(&to->clkevt);
+	disable_irq_nosync(to->clkevt.irq);
+
+	return 0;
+}
+#else /* CONFIG_ARM */
+static struct timer_of tegra_to = {
+	.flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ,
+
+	.clkevt = {
+		.name = "tegra_timer",
+		.rating	= 300,
+		.features = CLOCK_EVT_FEAT_ONESHOT |
+			    CLOCK_EVT_FEAT_PERIODIC |
+			    CLOCK_EVT_FEAT_DYNIRQ,
+		.set_next_event	= tegra_timer_set_next_event,
+		.set_state_shutdown = tegra_timer_shutdown,
+		.set_state_periodic = tegra_timer_set_periodic,
+		.set_state_oneshot = tegra_timer_shutdown,
+		.tick_resume = tegra_timer_shutdown,
+		.suspend = tegra_timer_suspend,
+		.resume = tegra_timer_resume,
+		.cpumask = cpu_possible_mask,
+	},
+
+	.of_irq = {
+		.index = 2,
+		.flags = IRQF_TIMER | IRQF_TRIGGER_HIGH,
+		.handler = tegra_timer_isr,
+	},
 };
 
 static u64 notrace tegra_read_sched_clock(void)
 {
-	return timer_readl(TIMERUS_CNTR_1US);
+	return readl(timer_reg_base + TIMERUS_CNTR_1US);
+}
+
+static unsigned long tegra_delay_timer_read_counter_long(void)
+{
+	return readl(timer_reg_base + TIMERUS_CNTR_1US);
 }
 
 /*
@@ -143,100 +233,155 @@ static void tegra_read_persistent_clock64(struct timespec64 *ts)
 	timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC);
 	*ts = persistent_ts;
 }
+#endif
 
-static unsigned long tegra_delay_timer_read_counter_long(void)
-{
-	return readl(timer_reg_base + TIMERUS_CNTR_1US);
-}
-
-static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
-{
-	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
-	timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
-	evt->event_handler(evt);
-	return IRQ_HANDLED;
-}
-
-static struct irqaction tegra_timer_irq = {
-	.name		= "timer0",
-	.flags		= IRQF_TIMER | IRQF_TRIGGER_HIGH,
-	.handler	= tegra_timer_interrupt,
-	.dev_id		= &tegra_clockevent,
-};
-
-static int __init tegra20_init_timer(struct device_node *np)
+static int tegra_timer_common_init(struct device_node *np, struct timer_of *to)
 {
-	struct clk *clk;
-	unsigned long rate;
-	int ret;
-
-	timer_reg_base = of_iomap(np, 0);
-	if (!timer_reg_base) {
-		pr_err("Can't map timer registers\n");
-		return -ENXIO;
-	}
+	int ret = 0;
 
-	tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
-	if (tegra_timer_irq.irq <= 0) {
-		pr_err("Failed to map timer IRQ\n");
-		return -EINVAL;
-	}
+	ret = timer_of_init(np, to);
+	if (ret < 0)
+		goto out;
 
-	clk = of_clk_get(np, 0);
-	if (IS_ERR(clk)) {
-		pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
-		rate = 12000000;
-	} else {
-		clk_prepare_enable(clk);
-		rate = clk_get_rate(clk);
-	}
+	timer_reg_base = timer_of_base(to);
 
-	switch (rate) {
+	/*
+	 * Configure microsecond timers to have 1MHz clock
+	 * Config register is 0xqqww, where qq is "dividend", ww is "divisor"
+	 * Uses n+1 scheme
+	 */
+	switch (timer_of_rate(to)) {
 	case 12000000:
-		timer_writel(0x000b, TIMERUS_USEC_CFG);
+		usec_config = 0x000b; /* (11+1)/(0+1) */
+		break;
+	case 12800000:
+		usec_config = 0x043f; /* (63+1)/(4+1) */
 		break;
 	case 13000000:
-		timer_writel(0x000c, TIMERUS_USEC_CFG);
+		usec_config = 0x000c; /* (12+1)/(0+1) */
+		break;
+	case 16800000:
+		usec_config = 0x0453; /* (83+1)/(4+1) */
 		break;
 	case 19200000:
-		timer_writel(0x045f, TIMERUS_USEC_CFG);
+		usec_config = 0x045f; /* (95+1)/(4+1) */
 		break;
 	case 26000000:
-		timer_writel(0x0019, TIMERUS_USEC_CFG);
+		usec_config = 0x0019; /* (25+1)/(0+1) */
+		break;
+	case 38400000:
+		usec_config = 0x04bf; /* (191+1)/(4+1) */
+		break;
+	case 48000000:
+		usec_config = 0x002f; /* (47+1)/(0+1) */
 		break;
 	default:
-		WARN(1, "Unknown clock rate");
+		ret = -EINVAL;
+		goto out;
+	}
+
+	writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG);
+
+out:
+	return ret;
+}
+
+#ifdef CONFIG_ARM64
+static int __init tegra_init_timer(struct device_node *np)
+{
+	int cpu, ret = 0;
+	struct timer_of *to;
+
+	to = this_cpu_ptr(&tegra_to);
+	ret = tegra_timer_common_init(np, to);
+	if (ret < 0)
+		goto out;
+
+	for_each_possible_cpu(cpu) {
+		struct timer_of *cpu_to;
+
+		cpu_to = per_cpu_ptr(&tegra_to, cpu);
+		cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu);
+		cpu_to->of_clk.rate = timer_of_rate(to);
+		cpu_to->clkevt.cpumask = cpumask_of(cpu);
+		cpu_to->clkevt.irq =
+			irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu));
+		if (!cpu_to->clkevt.irq) {
+			pr_err("%s: can't map IRQ for CPU%d\n",
+			       __func__, cpu);
+			ret = -EINVAL;
+			goto out;
+		}
+
+		irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
+		ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr,
+				  IRQF_TIMER | IRQF_NOBALANCING,
+				  cpu_to->clkevt.name, &cpu_to->clkevt);
+		if (ret) {
+			pr_err("%s: cannot setup irq %d for CPU%d\n",
+				__func__, cpu_to->clkevt.irq, cpu);
+			ret = -EINVAL;
+			goto out_irq;
+		}
+	}
+
+	cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
+			  "AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
+			  tegra_timer_stop);
+
+	return ret;
+out_irq:
+	for_each_possible_cpu(cpu) {
+		struct timer_of *cpu_to;
+
+		cpu_to = per_cpu_ptr(&tegra_to, cpu);
+		if (cpu_to->clkevt.irq) {
+			free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
+			irq_dispose_mapping(cpu_to->clkevt.irq);
+		}
 	}
+out:
+	timer_of_cleanup(to);
+	return ret;
+}
+#else /* CONFIG_ARM */
+static int __init tegra_init_timer(struct device_node *np)
+{
+	int ret = 0;
+
+	ret = tegra_timer_common_init(np, &tegra_to);
+	if (ret < 0)
+		goto out;
 
-	sched_clock_register(tegra_read_sched_clock, 32, 1000000);
+	tegra_to.of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(0);
+	tegra_to.of_clk.rate = 1000000; /* microsecond timer */
 
+	sched_clock_register(tegra_read_sched_clock, 32,
+			     timer_of_rate(&tegra_to));
 	ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
-				    "timer_us", 1000000, 300, 32,
-				    clocksource_mmio_readl_up);
+				    "timer_us", timer_of_rate(&tegra_to),
+				    300, 32, clocksource_mmio_readl_up);
 	if (ret) {
 		pr_err("Failed to register clocksource\n");
-		return ret;
+		goto out;
 	}
 
 	tegra_delay_timer.read_current_timer =
 			tegra_delay_timer_read_counter_long;
-	tegra_delay_timer.freq = 1000000;
+	tegra_delay_timer.freq = timer_of_rate(&tegra_to);
 	register_current_timer_delay(&tegra_delay_timer);
 
-	ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
-	if (ret) {
-		pr_err("Failed to register timer IRQ: %d\n", ret);
-		return ret;
-	}
+	clockevents_config_and_register(&tegra_to.clkevt,
+					timer_of_rate(&tegra_to),
+					0x1,
+					0x1fffffff);
 
-	tegra_clockevent.cpumask = cpu_possible_mask;
-	tegra_clockevent.irq = tegra_timer_irq.irq;
-	clockevents_config_and_register(&tegra_clockevent, 1000000,
-					0x1, 0x1fffffff);
+	return ret;
+out:
+	timer_of_cleanup(&tegra_to);
 
-	return 0;
+	return ret;
 }
-TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
 
 static int __init tegra20_init_rtc(struct device_node *np)
 {
@@ -261,3 +406,6 @@ static int __init tegra20_init_rtc(struct device_node *np)
 	return register_persistent_clock(tegra_read_persistent_clock64);
 }
 TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
+#endif
+TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra_init_timer);
+TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra_init_timer);
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index fd586d0301e7..e78281d07b70 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -121,6 +121,7 @@ enum cpuhp_state {
 	CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING,
 	CPUHP_AP_ARM_TWD_STARTING,
 	CPUHP_AP_QCOM_TIMER_STARTING,
+	CPUHP_AP_TEGRA_TIMER_STARTING,
 	CPUHP_AP_ARMADA_TIMER_STARTING,
 	CPUHP_AP_MARCO_TIMER_STARTING,
 	CPUHP_AP_MIPS_GIC_TIMER_STARTING,
-- 
2.20.1

[PATCH V7 2/8] clocksource: tegra: add Tegra210 timer support

[Joseph Lo]

Add support for the Tegra210 timer that runs at oscillator clock
(TMR10-TMR13). We need these timers to work as clock event device and to
replace the ARMv8 architected timer due to it can't survive across the
power cycle of the CPU core or CPUPORESET signal. So it can't be a wake-up
source when CPU suspends in power down state.

Also convert the original driver to use timer-of API.

Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
v7:
 * kconfig fix for 'depends on ARM || ARM64'
 * move suspend/resume to clkevt
 * refine the usage for the macro of TIMER_OF_DECLARE
v6:
 * refine the timer defines
 * add ack tag from Jon.
v5:
 * add ack tag from Thierry
v4:
 * merge timer-tegra210.c in previous version into timer-tegra20.c
v3:
 * use timer-of API
v2:
 * add error clean-up code
---
 drivers/clocksource/Kconfig         |   3 +-
 drivers/clocksource/timer-tegra20.c | 370 +++++++++++++++++++---------
 include/linux/cpuhotplug.h          |   1 +
 3 files changed, 262 insertions(+), 112 deletions(-)

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 8dfd3bc448d0..5d93e580e5dc 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -131,7 +131,8 @@ config SUN5I_HSTIMER
 config TEGRA_TIMER
 	bool "Tegra timer driver" if COMPILE_TEST
 	select CLKSRC_MMIO
-	depends on ARM
+	select TIMER_OF
+	depends on ARM || ARM64
 	help
 	  Enables support for the Tegra driver.
 
diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c
index 4293943f4e2b..fdb3d795a409 100644
--- a/drivers/clocksource/timer-tegra20.c
+++ b/drivers/clocksource/timer-tegra20.c
@@ -15,21 +15,24 @@
  *
  */
 
-#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/cpu.h>
+#include <linux/cpumask.h>
+#include <linux/delay.h>
 #include <linux/err.h>
-#include <linux/time.h>
 #include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/clockchips.h>
-#include <linux/clocksource.h>
-#include <linux/clk.h>
-#include <linux/io.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <linux/percpu.h>
 #include <linux/sched_clock.h>
-#include <linux/delay.h>
+#include <linux/time.h>
+
+#include "timer-of.h"
 
+#ifdef CONFIG_ARM
 #include <asm/mach/time.h>
+#endif
 
 #define RTC_SECONDS            0x08
 #define RTC_SHADOW_SECONDS     0x0c
@@ -39,74 +42,161 @@
 #define TIMERUS_USEC_CFG 0x14
 #define TIMERUS_CNTR_FREEZE 0x4c
 
-#define TIMER1_BASE 0x0
-#define TIMER2_BASE 0x8
-#define TIMER3_BASE 0x50
-#define TIMER4_BASE 0x58
-
-#define TIMER_PTV 0x0
-#define TIMER_PCR 0x4
-
+#define TIMER_PTV		0x0
+#define TIMER_PTV_EN		BIT(31)
+#define TIMER_PTV_PER		BIT(30)
+#define TIMER_PCR		0x4
+#define TIMER_PCR_INTR_CLR	BIT(30)
+
+#ifdef CONFIG_ARM
+#define TIMER_CPU0		0x50 /* TIMER3 */
+#else
+#define TIMER_CPU0		0x90 /* TIMER10 */
+#define TIMER10_IRQ_IDX		10
+#define IRQ_IDX_FOR_CPU(cpu)	(TIMER10_IRQ_IDX + cpu)
+#endif
+#define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8)
+
+static u32 usec_config;
 static void __iomem *timer_reg_base;
+#ifdef CONFIG_ARM
 static void __iomem *rtc_base;
-
 static struct timespec64 persistent_ts;
 static u64 persistent_ms, last_persistent_ms;
-
 static struct delay_timer tegra_delay_timer;
-
-#define timer_writel(value, reg) \
-	writel_relaxed(value, timer_reg_base + (reg))
-#define timer_readl(reg) \
-	readl_relaxed(timer_reg_base + (reg))
+#endif
 
 static int tegra_timer_set_next_event(unsigned long cycles,
 					 struct clock_event_device *evt)
 {
-	u32 reg;
+	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
 
-	reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
-	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
+	writel(TIMER_PTV_EN |
+	       ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
+	       reg_base + TIMER_PTV);
 
 	return 0;
 }
 
-static inline void timer_shutdown(struct clock_event_device *evt)
+static int tegra_timer_shutdown(struct clock_event_device *evt)
 {
-	timer_writel(0, TIMER3_BASE + TIMER_PTV);
+	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
+
+	writel(0, reg_base + TIMER_PTV);
+
+	return 0;
 }
 
-static int tegra_timer_shutdown(struct clock_event_device *evt)
+static int tegra_timer_set_periodic(struct clock_event_device *evt)
 {
-	timer_shutdown(evt);
+	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
+
+	writel(TIMER_PTV_EN | TIMER_PTV_PER |
+	       ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
+	       reg_base + TIMER_PTV);
+
 	return 0;
 }
 
-static int tegra_timer_set_periodic(struct clock_event_device *evt)
+static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
+	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
+
+	writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
+	evt->event_handler(evt);
+
+	return IRQ_HANDLED;
+}
+
+static void tegra_timer_suspend(struct clock_event_device *evt)
+{
+	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
+
+	writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
+}
+
+static void tegra_timer_resume(struct clock_event_device *evt)
+{
+	writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
+}
+
+#ifdef CONFIG_ARM64
+static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
+	.flags = TIMER_OF_CLOCK | TIMER_OF_BASE,
+
+	.clkevt = {
+		.name = "tegra_timer",
+		.rating = 460,
+		.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
+		.set_next_event = tegra_timer_set_next_event,
+		.set_state_shutdown = tegra_timer_shutdown,
+		.set_state_periodic = tegra_timer_set_periodic,
+		.set_state_oneshot = tegra_timer_shutdown,
+		.tick_resume = tegra_timer_shutdown,
+		.suspend = tegra_timer_suspend,
+		.resume = tegra_timer_resume,
+	},
+};
+
+static int tegra_timer_setup(unsigned int cpu)
 {
-	u32 reg = 0xC0000000 | ((1000000 / HZ) - 1);
+	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
+
+	irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
+	enable_irq(to->clkevt.irq);
+
+	clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
+					1, /* min */
+					0x1fffffff); /* 29 bits */
 
-	timer_shutdown(evt);
-	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
 	return 0;
 }
 
-static struct clock_event_device tegra_clockevent = {
-	.name			= "timer0",
-	.rating			= 300,
-	.features		= CLOCK_EVT_FEAT_ONESHOT |
-				  CLOCK_EVT_FEAT_PERIODIC |
-				  CLOCK_EVT_FEAT_DYNIRQ,
-	.set_next_event		= tegra_timer_set_next_event,
-	.set_state_shutdown	= tegra_timer_shutdown,
-	.set_state_periodic	= tegra_timer_set_periodic,
-	.set_state_oneshot	= tegra_timer_shutdown,
-	.tick_resume		= tegra_timer_shutdown,
+static int tegra_timer_stop(unsigned int cpu)
+{
+	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
+
+	to->clkevt.set_state_shutdown(&to->clkevt);
+	disable_irq_nosync(to->clkevt.irq);
+
+	return 0;
+}
+#else /* CONFIG_ARM */
+static struct timer_of tegra_to = {
+	.flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ,
+
+	.clkevt = {
+		.name = "tegra_timer",
+		.rating	= 300,
+		.features = CLOCK_EVT_FEAT_ONESHOT |
+			    CLOCK_EVT_FEAT_PERIODIC |
+			    CLOCK_EVT_FEAT_DYNIRQ,
+		.set_next_event	= tegra_timer_set_next_event,
+		.set_state_shutdown = tegra_timer_shutdown,
+		.set_state_periodic = tegra_timer_set_periodic,
+		.set_state_oneshot = tegra_timer_shutdown,
+		.tick_resume = tegra_timer_shutdown,
+		.suspend = tegra_timer_suspend,
+		.resume = tegra_timer_resume,
+		.cpumask = cpu_possible_mask,
+	},
+
+	.of_irq = {
+		.index = 2,
+		.flags = IRQF_TIMER | IRQF_TRIGGER_HIGH,
+		.handler = tegra_timer_isr,
+	},
 };
 
 static u64 notrace tegra_read_sched_clock(void)
 {
-	return timer_readl(TIMERUS_CNTR_1US);
+	return readl(timer_reg_base + TIMERUS_CNTR_1US);
+}
+
+static unsigned long tegra_delay_timer_read_counter_long(void)
+{
+	return readl(timer_reg_base + TIMERUS_CNTR_1US);
 }
 
 /*
@@ -143,100 +233,155 @@ static void tegra_read_persistent_clock64(struct timespec64 *ts)
 	timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC);
 	*ts = persistent_ts;
 }
+#endif
 
-static unsigned long tegra_delay_timer_read_counter_long(void)
-{
-	return readl(timer_reg_base + TIMERUS_CNTR_1US);
-}
-
-static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
-{
-	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
-	timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
-	evt->event_handler(evt);
-	return IRQ_HANDLED;
-}
-
-static struct irqaction tegra_timer_irq = {
-	.name		= "timer0",
-	.flags		= IRQF_TIMER | IRQF_TRIGGER_HIGH,
-	.handler	= tegra_timer_interrupt,
-	.dev_id		= &tegra_clockevent,
-};
-
-static int __init tegra20_init_timer(struct device_node *np)
+static int tegra_timer_common_init(struct device_node *np, struct timer_of *to)
 {
-	struct clk *clk;
-	unsigned long rate;
-	int ret;
-
-	timer_reg_base = of_iomap(np, 0);
-	if (!timer_reg_base) {
-		pr_err("Can't map timer registers\n");
-		return -ENXIO;
-	}
+	int ret = 0;
 
-	tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
-	if (tegra_timer_irq.irq <= 0) {
-		pr_err("Failed to map timer IRQ\n");
-		return -EINVAL;
-	}
+	ret = timer_of_init(np, to);
+	if (ret < 0)
+		goto out;
 
-	clk = of_clk_get(np, 0);
-	if (IS_ERR(clk)) {
-		pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
-		rate = 12000000;
-	} else {
-		clk_prepare_enable(clk);
-		rate = clk_get_rate(clk);
-	}
+	timer_reg_base = timer_of_base(to);
 
-	switch (rate) {
+	/*
+	 * Configure microsecond timers to have 1MHz clock
+	 * Config register is 0xqqww, where qq is "dividend", ww is "divisor"
+	 * Uses n+1 scheme
+	 */
+	switch (timer_of_rate(to)) {
 	case 12000000:
-		timer_writel(0x000b, TIMERUS_USEC_CFG);
+		usec_config = 0x000b; /* (11+1)/(0+1) */
+		break;
+	case 12800000:
+		usec_config = 0x043f; /* (63+1)/(4+1) */
 		break;
 	case 13000000:
-		timer_writel(0x000c, TIMERUS_USEC_CFG);
+		usec_config = 0x000c; /* (12+1)/(0+1) */
+		break;
+	case 16800000:
+		usec_config = 0x0453; /* (83+1)/(4+1) */
 		break;
 	case 19200000:
-		timer_writel(0x045f, TIMERUS_USEC_CFG);
+		usec_config = 0x045f; /* (95+1)/(4+1) */
 		break;
 	case 26000000:
-		timer_writel(0x0019, TIMERUS_USEC_CFG);
+		usec_config = 0x0019; /* (25+1)/(0+1) */
+		break;
+	case 38400000:
+		usec_config = 0x04bf; /* (191+1)/(4+1) */
+		break;
+	case 48000000:
+		usec_config = 0x002f; /* (47+1)/(0+1) */
 		break;
 	default:
-		WARN(1, "Unknown clock rate");
+		ret = -EINVAL;
+		goto out;
+	}
+
+	writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG);
+
+out:
+	return ret;
+}
+
+#ifdef CONFIG_ARM64
+static int __init tegra_init_timer(struct device_node *np)
+{
+	int cpu, ret = 0;
+	struct timer_of *to;
+
+	to = this_cpu_ptr(&tegra_to);
+	ret = tegra_timer_common_init(np, to);
+	if (ret < 0)
+		goto out;
+
+	for_each_possible_cpu(cpu) {
+		struct timer_of *cpu_to;
+
+		cpu_to = per_cpu_ptr(&tegra_to, cpu);
+		cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu);
+		cpu_to->of_clk.rate = timer_of_rate(to);
+		cpu_to->clkevt.cpumask = cpumask_of(cpu);
+		cpu_to->clkevt.irq =
+			irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu));
+		if (!cpu_to->clkevt.irq) {
+			pr_err("%s: can't map IRQ for CPU%d\n",
+			       __func__, cpu);
+			ret = -EINVAL;
+			goto out;
+		}
+
+		irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
+		ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr,
+				  IRQF_TIMER | IRQF_NOBALANCING,
+				  cpu_to->clkevt.name, &cpu_to->clkevt);
+		if (ret) {
+			pr_err("%s: cannot setup irq %d for CPU%d\n",
+				__func__, cpu_to->clkevt.irq, cpu);
+			ret = -EINVAL;
+			goto out_irq;
+		}
+	}
+
+	cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
+			  "AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
+			  tegra_timer_stop);
+
+	return ret;
+out_irq:
+	for_each_possible_cpu(cpu) {
+		struct timer_of *cpu_to;
+
+		cpu_to = per_cpu_ptr(&tegra_to, cpu);
+		if (cpu_to->clkevt.irq) {
+			free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
+			irq_dispose_mapping(cpu_to->clkevt.irq);
+		}
 	}
+out:
+	timer_of_cleanup(to);
+	return ret;
+}
+#else /* CONFIG_ARM */
+static int __init tegra_init_timer(struct device_node *np)
+{
+	int ret = 0;
+
+	ret = tegra_timer_common_init(np, &tegra_to);
+	if (ret < 0)
+		goto out;
 
-	sched_clock_register(tegra_read_sched_clock, 32, 1000000);
+	tegra_to.of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(0);
+	tegra_to.of_clk.rate = 1000000; /* microsecond timer */
 
+	sched_clock_register(tegra_read_sched_clock, 32,
+			     timer_of_rate(&tegra_to));
 	ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
-				    "timer_us", 1000000, 300, 32,
-				    clocksource_mmio_readl_up);
+				    "timer_us", timer_of_rate(&tegra_to),
+				    300, 32, clocksource_mmio_readl_up);
 	if (ret) {
 		pr_err("Failed to register clocksource\n");
-		return ret;
+		goto out;
 	}
 
 	tegra_delay_timer.read_current_timer =
 			tegra_delay_timer_read_counter_long;
-	tegra_delay_timer.freq = 1000000;
+	tegra_delay_timer.freq = timer_of_rate(&tegra_to);
 	register_current_timer_delay(&tegra_delay_timer);
 
-	ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
-	if (ret) {
-		pr_err("Failed to register timer IRQ: %d\n", ret);
-		return ret;
-	}
+	clockevents_config_and_register(&tegra_to.clkevt,
+					timer_of_rate(&tegra_to),
+					0x1,
+					0x1fffffff);
 
-	tegra_clockevent.cpumask = cpu_possible_mask;
-	tegra_clockevent.irq = tegra_timer_irq.irq;
-	clockevents_config_and_register(&tegra_clockevent, 1000000,
-					0x1, 0x1fffffff);
+	return ret;
+out:
+	timer_of_cleanup(&tegra_to);
 
-	return 0;
+	return ret;
 }
-TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
 
 static int __init tegra20_init_rtc(struct device_node *np)
 {
@@ -261,3 +406,6 @@ static int __init tegra20_init_rtc(struct device_node *np)
 	return register_persistent_clock(tegra_read_persistent_clock64);
 }
 TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
+#endif
+TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra_init_timer);
+TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra_init_timer);
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index fd586d0301e7..e78281d07b70 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -121,6 +121,7 @@ enum cpuhp_state {
 	CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING,
 	CPUHP_AP_ARM_TWD_STARTING,
 	CPUHP_AP_QCOM_TIMER_STARTING,
+	CPUHP_AP_TEGRA_TIMER_STARTING,
 	CPUHP_AP_ARMADA_TIMER_STARTING,
 	CPUHP_AP_MARCO_TIMER_STARTING,
 	CPUHP_AP_MIPS_GIC_TIMER_STARTING,
-- 
2.20.1

[PATCH V7 2/8] clocksource: tegra: add Tegra210 timer support

[Joseph Lo]

Add support for the Tegra210 timer that runs at oscillator clock
(TMR10-TMR13). We need these timers to work as clock event device and to
replace the ARMv8 architected timer due to it can't survive across the
power cycle of the CPU core or CPUPORESET signal. So it can't be a wake-up
source when CPU suspends in power down state.

Also convert the original driver to use timer-of API.

Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
v7:
 * kconfig fix for 'depends on ARM || ARM64'
 * move suspend/resume to clkevt
 * refine the usage for the macro of TIMER_OF_DECLARE
v6:
 * refine the timer defines
 * add ack tag from Jon.
v5:
 * add ack tag from Thierry
v4:
 * merge timer-tegra210.c in previous version into timer-tegra20.c
v3:
 * use timer-of API
v2:
 * add error clean-up code
---
 drivers/clocksource/Kconfig         |   3 +-
 drivers/clocksource/timer-tegra20.c | 370 +++++++++++++++++++---------
 include/linux/cpuhotplug.h          |   1 +
 3 files changed, 262 insertions(+), 112 deletions(-)

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 8dfd3bc448d0..5d93e580e5dc 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -131,7 +131,8 @@ config SUN5I_HSTIMER
 config TEGRA_TIMER
 	bool "Tegra timer driver" if COMPILE_TEST
 	select CLKSRC_MMIO
-	depends on ARM
+	select TIMER_OF
+	depends on ARM || ARM64
 	help
 	  Enables support for the Tegra driver.
 
diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c
index 4293943f4e2b..fdb3d795a409 100644
--- a/drivers/clocksource/timer-tegra20.c
+++ b/drivers/clocksource/timer-tegra20.c
@@ -15,21 +15,24 @@
  *
  */
 
-#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/cpu.h>
+#include <linux/cpumask.h>
+#include <linux/delay.h>
 #include <linux/err.h>
-#include <linux/time.h>
 #include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/clockchips.h>
-#include <linux/clocksource.h>
-#include <linux/clk.h>
-#include <linux/io.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <linux/percpu.h>
 #include <linux/sched_clock.h>
-#include <linux/delay.h>
+#include <linux/time.h>
+
+#include "timer-of.h"
 
+#ifdef CONFIG_ARM
 #include <asm/mach/time.h>
+#endif
 
 #define RTC_SECONDS            0x08
 #define RTC_SHADOW_SECONDS     0x0c
@@ -39,74 +42,161 @@
 #define TIMERUS_USEC_CFG 0x14
 #define TIMERUS_CNTR_FREEZE 0x4c
 
-#define TIMER1_BASE 0x0
-#define TIMER2_BASE 0x8
-#define TIMER3_BASE 0x50
-#define TIMER4_BASE 0x58
-
-#define TIMER_PTV 0x0
-#define TIMER_PCR 0x4
-
+#define TIMER_PTV		0x0
+#define TIMER_PTV_EN		BIT(31)
+#define TIMER_PTV_PER		BIT(30)
+#define TIMER_PCR		0x4
+#define TIMER_PCR_INTR_CLR	BIT(30)
+
+#ifdef CONFIG_ARM
+#define TIMER_CPU0		0x50 /* TIMER3 */
+#else
+#define TIMER_CPU0		0x90 /* TIMER10 */
+#define TIMER10_IRQ_IDX		10
+#define IRQ_IDX_FOR_CPU(cpu)	(TIMER10_IRQ_IDX + cpu)
+#endif
+#define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8)
+
+static u32 usec_config;
 static void __iomem *timer_reg_base;
+#ifdef CONFIG_ARM
 static void __iomem *rtc_base;
-
 static struct timespec64 persistent_ts;
 static u64 persistent_ms, last_persistent_ms;
-
 static struct delay_timer tegra_delay_timer;
-
-#define timer_writel(value, reg) \
-	writel_relaxed(value, timer_reg_base + (reg))
-#define timer_readl(reg) \
-	readl_relaxed(timer_reg_base + (reg))
+#endif
 
 static int tegra_timer_set_next_event(unsigned long cycles,
 					 struct clock_event_device *evt)
 {
-	u32 reg;
+	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
 
-	reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
-	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
+	writel(TIMER_PTV_EN |
+	       ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
+	       reg_base + TIMER_PTV);
 
 	return 0;
 }
 
-static inline void timer_shutdown(struct clock_event_device *evt)
+static int tegra_timer_shutdown(struct clock_event_device *evt)
 {
-	timer_writel(0, TIMER3_BASE + TIMER_PTV);
+	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
+
+	writel(0, reg_base + TIMER_PTV);
+
+	return 0;
 }
 
-static int tegra_timer_shutdown(struct clock_event_device *evt)
+static int tegra_timer_set_periodic(struct clock_event_device *evt)
 {
-	timer_shutdown(evt);
+	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
+
+	writel(TIMER_PTV_EN | TIMER_PTV_PER |
+	       ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
+	       reg_base + TIMER_PTV);
+
 	return 0;
 }
 
-static int tegra_timer_set_periodic(struct clock_event_device *evt)
+static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
+	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
+
+	writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
+	evt->event_handler(evt);
+
+	return IRQ_HANDLED;
+}
+
+static void tegra_timer_suspend(struct clock_event_device *evt)
+{
+	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
+
+	writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
+}
+
+static void tegra_timer_resume(struct clock_event_device *evt)
+{
+	writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
+}
+
+#ifdef CONFIG_ARM64
+static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
+	.flags = TIMER_OF_CLOCK | TIMER_OF_BASE,
+
+	.clkevt = {
+		.name = "tegra_timer",
+		.rating = 460,
+		.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
+		.set_next_event = tegra_timer_set_next_event,
+		.set_state_shutdown = tegra_timer_shutdown,
+		.set_state_periodic = tegra_timer_set_periodic,
+		.set_state_oneshot = tegra_timer_shutdown,
+		.tick_resume = tegra_timer_shutdown,
+		.suspend = tegra_timer_suspend,
+		.resume = tegra_timer_resume,
+	},
+};
+
+static int tegra_timer_setup(unsigned int cpu)
 {
-	u32 reg = 0xC0000000 | ((1000000 / HZ) - 1);
+	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
+
+	irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
+	enable_irq(to->clkevt.irq);
+
+	clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
+					1, /* min */
+					0x1fffffff); /* 29 bits */
 
-	timer_shutdown(evt);
-	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
 	return 0;
 }
 
-static struct clock_event_device tegra_clockevent = {
-	.name			= "timer0",
-	.rating			= 300,
-	.features		= CLOCK_EVT_FEAT_ONESHOT |
-				  CLOCK_EVT_FEAT_PERIODIC |
-				  CLOCK_EVT_FEAT_DYNIRQ,
-	.set_next_event		= tegra_timer_set_next_event,
-	.set_state_shutdown	= tegra_timer_shutdown,
-	.set_state_periodic	= tegra_timer_set_periodic,
-	.set_state_oneshot	= tegra_timer_shutdown,
-	.tick_resume		= tegra_timer_shutdown,
+static int tegra_timer_stop(unsigned int cpu)
+{
+	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
+
+	to->clkevt.set_state_shutdown(&to->clkevt);
+	disable_irq_nosync(to->clkevt.irq);
+
+	return 0;
+}
+#else /* CONFIG_ARM */
+static struct timer_of tegra_to = {
+	.flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ,
+
+	.clkevt = {
+		.name = "tegra_timer",
+		.rating	= 300,
+		.features = CLOCK_EVT_FEAT_ONESHOT |
+			    CLOCK_EVT_FEAT_PERIODIC |
+			    CLOCK_EVT_FEAT_DYNIRQ,
+		.set_next_event	= tegra_timer_set_next_event,
+		.set_state_shutdown = tegra_timer_shutdown,
+		.set_state_periodic = tegra_timer_set_periodic,
+		.set_state_oneshot = tegra_timer_shutdown,
+		.tick_resume = tegra_timer_shutdown,
+		.suspend = tegra_timer_suspend,
+		.resume = tegra_timer_resume,
+		.cpumask = cpu_possible_mask,
+	},
+
+	.of_irq = {
+		.index = 2,
+		.flags = IRQF_TIMER | IRQF_TRIGGER_HIGH,
+		.handler = tegra_timer_isr,
+	},
 };
 
 static u64 notrace tegra_read_sched_clock(void)
 {
-	return timer_readl(TIMERUS_CNTR_1US);
+	return readl(timer_reg_base + TIMERUS_CNTR_1US);
+}
+
+static unsigned long tegra_delay_timer_read_counter_long(void)
+{
+	return readl(timer_reg_base + TIMERUS_CNTR_1US);
 }
 
 /*
@@ -143,100 +233,155 @@ static void tegra_read_persistent_clock64(struct timespec64 *ts)
 	timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC);
 	*ts = persistent_ts;
 }
+#endif
 
-static unsigned long tegra_delay_timer_read_counter_long(void)
-{
-	return readl(timer_reg_base + TIMERUS_CNTR_1US);
-}
-
-static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
-{
-	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
-	timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
-	evt->event_handler(evt);
-	return IRQ_HANDLED;
-}
-
-static struct irqaction tegra_timer_irq = {
-	.name		= "timer0",
-	.flags		= IRQF_TIMER | IRQF_TRIGGER_HIGH,
-	.handler	= tegra_timer_interrupt,
-	.dev_id		= &tegra_clockevent,
-};
-
-static int __init tegra20_init_timer(struct device_node *np)
+static int tegra_timer_common_init(struct device_node *np, struct timer_of *to)
 {
-	struct clk *clk;
-	unsigned long rate;
-	int ret;
-
-	timer_reg_base = of_iomap(np, 0);
-	if (!timer_reg_base) {
-		pr_err("Can't map timer registers\n");
-		return -ENXIO;
-	}
+	int ret = 0;
 
-	tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
-	if (tegra_timer_irq.irq <= 0) {
-		pr_err("Failed to map timer IRQ\n");
-		return -EINVAL;
-	}
+	ret = timer_of_init(np, to);
+	if (ret < 0)
+		goto out;
 
-	clk = of_clk_get(np, 0);
-	if (IS_ERR(clk)) {
-		pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
-		rate = 12000000;
-	} else {
-		clk_prepare_enable(clk);
-		rate = clk_get_rate(clk);
-	}
+	timer_reg_base = timer_of_base(to);
 
-	switch (rate) {
+	/*
+	 * Configure microsecond timers to have 1MHz clock
+	 * Config register is 0xqqww, where qq is "dividend", ww is "divisor"
+	 * Uses n+1 scheme
+	 */
+	switch (timer_of_rate(to)) {
 	case 12000000:
-		timer_writel(0x000b, TIMERUS_USEC_CFG);
+		usec_config = 0x000b; /* (11+1)/(0+1) */
+		break;
+	case 12800000:
+		usec_config = 0x043f; /* (63+1)/(4+1) */
 		break;
 	case 13000000:
-		timer_writel(0x000c, TIMERUS_USEC_CFG);
+		usec_config = 0x000c; /* (12+1)/(0+1) */
+		break;
+	case 16800000:
+		usec_config = 0x0453; /* (83+1)/(4+1) */
 		break;
 	case 19200000:
-		timer_writel(0x045f, TIMERUS_USEC_CFG);
+		usec_config = 0x045f; /* (95+1)/(4+1) */
 		break;
 	case 26000000:
-		timer_writel(0x0019, TIMERUS_USEC_CFG);
+		usec_config = 0x0019; /* (25+1)/(0+1) */
+		break;
+	case 38400000:
+		usec_config = 0x04bf; /* (191+1)/(4+1) */
+		break;
+	case 48000000:
+		usec_config = 0x002f; /* (47+1)/(0+1) */
 		break;
 	default:
-		WARN(1, "Unknown clock rate");
+		ret = -EINVAL;
+		goto out;
+	}
+
+	writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG);
+
+out:
+	return ret;
+}
+
+#ifdef CONFIG_ARM64
+static int __init tegra_init_timer(struct device_node *np)
+{
+	int cpu, ret = 0;
+	struct timer_of *to;
+
+	to = this_cpu_ptr(&tegra_to);
+	ret = tegra_timer_common_init(np, to);
+	if (ret < 0)
+		goto out;
+
+	for_each_possible_cpu(cpu) {
+		struct timer_of *cpu_to;
+
+		cpu_to = per_cpu_ptr(&tegra_to, cpu);
+		cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu);
+		cpu_to->of_clk.rate = timer_of_rate(to);
+		cpu_to->clkevt.cpumask = cpumask_of(cpu);
+		cpu_to->clkevt.irq =
+			irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu));
+		if (!cpu_to->clkevt.irq) {
+			pr_err("%s: can't map IRQ for CPU%d\n",
+			       __func__, cpu);
+			ret = -EINVAL;
+			goto out;
+		}
+
+		irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
+		ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr,
+				  IRQF_TIMER | IRQF_NOBALANCING,
+				  cpu_to->clkevt.name, &cpu_to->clkevt);
+		if (ret) {
+			pr_err("%s: cannot setup irq %d for CPU%d\n",
+				__func__, cpu_to->clkevt.irq, cpu);
+			ret = -EINVAL;
+			goto out_irq;
+		}
+	}
+
+	cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
+			  "AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
+			  tegra_timer_stop);
+
+	return ret;
+out_irq:
+	for_each_possible_cpu(cpu) {
+		struct timer_of *cpu_to;
+
+		cpu_to = per_cpu_ptr(&tegra_to, cpu);
+		if (cpu_to->clkevt.irq) {
+			free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
+			irq_dispose_mapping(cpu_to->clkevt.irq);
+		}
 	}
+out:
+	timer_of_cleanup(to);
+	return ret;
+}
+#else /* CONFIG_ARM */
+static int __init tegra_init_timer(struct device_node *np)
+{
+	int ret = 0;
+
+	ret = tegra_timer_common_init(np, &tegra_to);
+	if (ret < 0)
+		goto out;
 
-	sched_clock_register(tegra_read_sched_clock, 32, 1000000);
+	tegra_to.of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(0);
+	tegra_to.of_clk.rate = 1000000; /* microsecond timer */
 
+	sched_clock_register(tegra_read_sched_clock, 32,
+			     timer_of_rate(&tegra_to));
 	ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
-				    "timer_us", 1000000, 300, 32,
-				    clocksource_mmio_readl_up);
+				    "timer_us", timer_of_rate(&tegra_to),
+				    300, 32, clocksource_mmio_readl_up);
 	if (ret) {
 		pr_err("Failed to register clocksource\n");
-		return ret;
+		goto out;
 	}
 
 	tegra_delay_timer.read_current_timer =
 			tegra_delay_timer_read_counter_long;
-	tegra_delay_timer.freq = 1000000;
+	tegra_delay_timer.freq = timer_of_rate(&tegra_to);
 	register_current_timer_delay(&tegra_delay_timer);
 
-	ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
-	if (ret) {
-		pr_err("Failed to register timer IRQ: %d\n", ret);
-		return ret;
-	}
+	clockevents_config_and_register(&tegra_to.clkevt,
+					timer_of_rate(&tegra_to),
+					0x1,
+					0x1fffffff);
 
-	tegra_clockevent.cpumask = cpu_possible_mask;
-	tegra_clockevent.irq = tegra_timer_irq.irq;
-	clockevents_config_and_register(&tegra_clockevent, 1000000,
-					0x1, 0x1fffffff);
+	return ret;
+out:
+	timer_of_cleanup(&tegra_to);
 
-	return 0;
+	return ret;
 }
-TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
 
 static int __init tegra20_init_rtc(struct device_node *np)
 {
@@ -261,3 +406,6 @@ static int __init tegra20_init_rtc(struct device_node *np)
 	return register_persistent_clock(tegra_read_persistent_clock64);
 }
 TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
+#endif
+TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra_init_timer);
+TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra_init_timer);
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index fd586d0301e7..e78281d07b70 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -121,6 +121,7 @@ enum cpuhp_state {
 	CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING,
 	CPUHP_AP_ARM_TWD_STARTING,
 	CPUHP_AP_QCOM_TIMER_STARTING,
+	CPUHP_AP_TEGRA_TIMER_STARTING,
 	CPUHP_AP_ARMADA_TIMER_STARTING,
 	CPUHP_AP_MARCO_TIMER_STARTING,
 	CPUHP_AP_MIPS_GIC_TIMER_STARTING,
-- 
2.20.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH V7 2/8] clocksource: tegra: add Tegra210 timer support

[Daniel Lezcano]

On 21/02/2019 08:21, Joseph Lo wrote:
> Add support for the Tegra210 timer that runs at oscillator clock
> (TMR10-TMR13). We need these timers to work as clock event device and to
> replace the ARMv8 architected timer due to it can't survive across the
> power cycle of the CPU core or CPUPORESET signal. So it can't be a wake-up
> source when CPU suspends in power down state.
> 
> Also convert the original driver to use timer-of API.
> 
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Joseph Lo <josephl@nvidia.com>
> Acked-by: Thierry Reding <treding@nvidia.com>
> Acked-by: Jon Hunter <jonathanh@nvidia.com>
> ---

Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>

Will you take care of dropping the persistent clocksource code in this
driver?

> v7:
>  * kconfig fix for 'depends on ARM || ARM64'
>  * move suspend/resume to clkevt
>  * refine the usage for the macro of TIMER_OF_DECLARE
> v6:
>  * refine the timer defines
>  * add ack tag from Jon.
> v5:
>  * add ack tag from Thierry
> v4:
>  * merge timer-tegra210.c in previous version into timer-tegra20.c
> v3:
>  * use timer-of API
> v2:
>  * add error clean-up code
> ---
>  drivers/clocksource/Kconfig         |   3 +-
>  drivers/clocksource/timer-tegra20.c | 370 +++++++++++++++++++---------
>  include/linux/cpuhotplug.h          |   1 +
>  3 files changed, 262 insertions(+), 112 deletions(-)
> 
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 8dfd3bc448d0..5d93e580e5dc 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -131,7 +131,8 @@ config SUN5I_HSTIMER
>  config TEGRA_TIMER
>  	bool "Tegra timer driver" if COMPILE_TEST
>  	select CLKSRC_MMIO
> -	depends on ARM
> +	select TIMER_OF
> +	depends on ARM || ARM64
>  	help
>  	  Enables support for the Tegra driver.
>  
> diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c
> index 4293943f4e2b..fdb3d795a409 100644
> --- a/drivers/clocksource/timer-tegra20.c
> +++ b/drivers/clocksource/timer-tegra20.c
> @@ -15,21 +15,24 @@
>   *
>   */
>  
> -#include <linux/init.h>
> +#include <linux/clk.h>
> +#include <linux/clockchips.h>
> +#include <linux/cpu.h>
> +#include <linux/cpumask.h>
> +#include <linux/delay.h>
>  #include <linux/err.h>
> -#include <linux/time.h>
>  #include <linux/interrupt.h>
> -#include <linux/irq.h>
> -#include <linux/clockchips.h>
> -#include <linux/clocksource.h>
> -#include <linux/clk.h>
> -#include <linux/io.h>
>  #include <linux/of_address.h>
>  #include <linux/of_irq.h>
> +#include <linux/percpu.h>
>  #include <linux/sched_clock.h>
> -#include <linux/delay.h>
> +#include <linux/time.h>
> +
> +#include "timer-of.h"
>  
> +#ifdef CONFIG_ARM
>  #include <asm/mach/time.h>
> +#endif
>  
>  #define RTC_SECONDS            0x08
>  #define RTC_SHADOW_SECONDS     0x0c
> @@ -39,74 +42,161 @@
>  #define TIMERUS_USEC_CFG 0x14
>  #define TIMERUS_CNTR_FREEZE 0x4c
>  
> -#define TIMER1_BASE 0x0
> -#define TIMER2_BASE 0x8
> -#define TIMER3_BASE 0x50
> -#define TIMER4_BASE 0x58
> -
> -#define TIMER_PTV 0x0
> -#define TIMER_PCR 0x4
> -
> +#define TIMER_PTV		0x0
> +#define TIMER_PTV_EN		BIT(31)
> +#define TIMER_PTV_PER		BIT(30)
> +#define TIMER_PCR		0x4
> +#define TIMER_PCR_INTR_CLR	BIT(30)
> +
> +#ifdef CONFIG_ARM
> +#define TIMER_CPU0		0x50 /* TIMER3 */
> +#else
> +#define TIMER_CPU0		0x90 /* TIMER10 */
> +#define TIMER10_IRQ_IDX		10
> +#define IRQ_IDX_FOR_CPU(cpu)	(TIMER10_IRQ_IDX + cpu)
> +#endif
> +#define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8)
> +
> +static u32 usec_config;
>  static void __iomem *timer_reg_base;
> +#ifdef CONFIG_ARM
>  static void __iomem *rtc_base;
> -
>  static struct timespec64 persistent_ts;
>  static u64 persistent_ms, last_persistent_ms;
> -
>  static struct delay_timer tegra_delay_timer;
> -
> -#define timer_writel(value, reg) \
> -	writel_relaxed(value, timer_reg_base + (reg))
> -#define timer_readl(reg) \
> -	readl_relaxed(timer_reg_base + (reg))
> +#endif
>  
>  static int tegra_timer_set_next_event(unsigned long cycles,
>  					 struct clock_event_device *evt)
>  {
> -	u32 reg;
> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>  
> -	reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
> -	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
> +	writel(TIMER_PTV_EN |
> +	       ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
> +	       reg_base + TIMER_PTV);
>  
>  	return 0;
>  }
>  
> -static inline void timer_shutdown(struct clock_event_device *evt)
> +static int tegra_timer_shutdown(struct clock_event_device *evt)
>  {
> -	timer_writel(0, TIMER3_BASE + TIMER_PTV);
> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
> +
> +	writel(0, reg_base + TIMER_PTV);
> +
> +	return 0;
>  }
>  
> -static int tegra_timer_shutdown(struct clock_event_device *evt)
> +static int tegra_timer_set_periodic(struct clock_event_device *evt)
>  {
> -	timer_shutdown(evt);
> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
> +
> +	writel(TIMER_PTV_EN | TIMER_PTV_PER |
> +	       ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
> +	       reg_base + TIMER_PTV);
> +
>  	return 0;
>  }
>  
> -static int tegra_timer_set_periodic(struct clock_event_device *evt)
> +static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
> +{
> +	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
> +
> +	writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
> +	evt->event_handler(evt);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static void tegra_timer_suspend(struct clock_event_device *evt)
> +{
> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
> +
> +	writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
> +}
> +
> +static void tegra_timer_resume(struct clock_event_device *evt)
> +{
> +	writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
> +}
> +
> +#ifdef CONFIG_ARM64
> +static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
> +	.flags = TIMER_OF_CLOCK | TIMER_OF_BASE,
> +
> +	.clkevt = {
> +		.name = "tegra_timer",
> +		.rating = 460,
> +		.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
> +		.set_next_event = tegra_timer_set_next_event,
> +		.set_state_shutdown = tegra_timer_shutdown,
> +		.set_state_periodic = tegra_timer_set_periodic,
> +		.set_state_oneshot = tegra_timer_shutdown,
> +		.tick_resume = tegra_timer_shutdown,
> +		.suspend = tegra_timer_suspend,
> +		.resume = tegra_timer_resume,
> +	},
> +};
> +
> +static int tegra_timer_setup(unsigned int cpu)
>  {
> -	u32 reg = 0xC0000000 | ((1000000 / HZ) - 1);
> +	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
> +
> +	irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
> +	enable_irq(to->clkevt.irq);
> +
> +	clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
> +					1, /* min */
> +					0x1fffffff); /* 29 bits */
>  
> -	timer_shutdown(evt);
> -	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
>  	return 0;
>  }
>  
> -static struct clock_event_device tegra_clockevent = {
> -	.name			= "timer0",
> -	.rating			= 300,
> -	.features		= CLOCK_EVT_FEAT_ONESHOT |
> -				  CLOCK_EVT_FEAT_PERIODIC |
> -				  CLOCK_EVT_FEAT_DYNIRQ,
> -	.set_next_event		= tegra_timer_set_next_event,
> -	.set_state_shutdown	= tegra_timer_shutdown,
> -	.set_state_periodic	= tegra_timer_set_periodic,
> -	.set_state_oneshot	= tegra_timer_shutdown,
> -	.tick_resume		= tegra_timer_shutdown,
> +static int tegra_timer_stop(unsigned int cpu)
> +{
> +	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
> +
> +	to->clkevt.set_state_shutdown(&to->clkevt);
> +	disable_irq_nosync(to->clkevt.irq);
> +
> +	return 0;
> +}
> +#else /* CONFIG_ARM */
> +static struct timer_of tegra_to = {
> +	.flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ,
> +
> +	.clkevt = {
> +		.name = "tegra_timer",
> +		.rating	= 300,
> +		.features = CLOCK_EVT_FEAT_ONESHOT |
> +			    CLOCK_EVT_FEAT_PERIODIC |
> +			    CLOCK_EVT_FEAT_DYNIRQ,
> +		.set_next_event	= tegra_timer_set_next_event,
> +		.set_state_shutdown = tegra_timer_shutdown,
> +		.set_state_periodic = tegra_timer_set_periodic,
> +		.set_state_oneshot = tegra_timer_shutdown,
> +		.tick_resume = tegra_timer_shutdown,
> +		.suspend = tegra_timer_suspend,
> +		.resume = tegra_timer_resume,
> +		.cpumask = cpu_possible_mask,
> +	},
> +
> +	.of_irq = {
> +		.index = 2,
> +		.flags = IRQF_TIMER | IRQF_TRIGGER_HIGH,
> +		.handler = tegra_timer_isr,
> +	},
>  };
>  
>  static u64 notrace tegra_read_sched_clock(void)
>  {
> -	return timer_readl(TIMERUS_CNTR_1US);
> +	return readl(timer_reg_base + TIMERUS_CNTR_1US);
> +}
> +
> +static unsigned long tegra_delay_timer_read_counter_long(void)
> +{
> +	return readl(timer_reg_base + TIMERUS_CNTR_1US);
>  }
>  
>  /*
> @@ -143,100 +233,155 @@ static void tegra_read_persistent_clock64(struct timespec64 *ts)
>  	timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC);
>  	*ts = persistent_ts;
>  }
> +#endif
>  
> -static unsigned long tegra_delay_timer_read_counter_long(void)
> -{
> -	return readl(timer_reg_base + TIMERUS_CNTR_1US);
> -}
> -
> -static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
> -{
> -	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
> -	timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
> -	evt->event_handler(evt);
> -	return IRQ_HANDLED;
> -}
> -
> -static struct irqaction tegra_timer_irq = {
> -	.name		= "timer0",
> -	.flags		= IRQF_TIMER | IRQF_TRIGGER_HIGH,
> -	.handler	= tegra_timer_interrupt,
> -	.dev_id		= &tegra_clockevent,
> -};
> -
> -static int __init tegra20_init_timer(struct device_node *np)
> +static int tegra_timer_common_init(struct device_node *np, struct timer_of *to)
>  {
> -	struct clk *clk;
> -	unsigned long rate;
> -	int ret;
> -
> -	timer_reg_base = of_iomap(np, 0);
> -	if (!timer_reg_base) {
> -		pr_err("Can't map timer registers\n");
> -		return -ENXIO;
> -	}
> +	int ret = 0;
>  
> -	tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
> -	if (tegra_timer_irq.irq <= 0) {
> -		pr_err("Failed to map timer IRQ\n");
> -		return -EINVAL;
> -	}
> +	ret = timer_of_init(np, to);
> +	if (ret < 0)
> +		goto out;
>  
> -	clk = of_clk_get(np, 0);
> -	if (IS_ERR(clk)) {
> -		pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
> -		rate = 12000000;
> -	} else {
> -		clk_prepare_enable(clk);
> -		rate = clk_get_rate(clk);
> -	}
> +	timer_reg_base = timer_of_base(to);
>  
> -	switch (rate) {
> +	/*
> +	 * Configure microsecond timers to have 1MHz clock
> +	 * Config register is 0xqqww, where qq is "dividend", ww is "divisor"
> +	 * Uses n+1 scheme
> +	 */
> +	switch (timer_of_rate(to)) {
>  	case 12000000:
> -		timer_writel(0x000b, TIMERUS_USEC_CFG);
> +		usec_config = 0x000b; /* (11+1)/(0+1) */
> +		break;
> +	case 12800000:
> +		usec_config = 0x043f; /* (63+1)/(4+1) */
>  		break;
>  	case 13000000:
> -		timer_writel(0x000c, TIMERUS_USEC_CFG);
> +		usec_config = 0x000c; /* (12+1)/(0+1) */
> +		break;
> +	case 16800000:
> +		usec_config = 0x0453; /* (83+1)/(4+1) */
>  		break;
>  	case 19200000:
> -		timer_writel(0x045f, TIMERUS_USEC_CFG);
> +		usec_config = 0x045f; /* (95+1)/(4+1) */
>  		break;
>  	case 26000000:
> -		timer_writel(0x0019, TIMERUS_USEC_CFG);
> +		usec_config = 0x0019; /* (25+1)/(0+1) */
> +		break;
> +	case 38400000:
> +		usec_config = 0x04bf; /* (191+1)/(4+1) */
> +		break;
> +	case 48000000:
> +		usec_config = 0x002f; /* (47+1)/(0+1) */
>  		break;
>  	default:
> -		WARN(1, "Unknown clock rate");
> +		ret = -EINVAL;
> +		goto out;
> +	}
> +
> +	writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG);
> +
> +out:
> +	return ret;
> +}
> +
> +#ifdef CONFIG_ARM64
> +static int __init tegra_init_timer(struct device_node *np)
> +{
> +	int cpu, ret = 0;
> +	struct timer_of *to;
> +
> +	to = this_cpu_ptr(&tegra_to);
> +	ret = tegra_timer_common_init(np, to);
> +	if (ret < 0)
> +		goto out;
> +
> +	for_each_possible_cpu(cpu) {
> +		struct timer_of *cpu_to;
> +
> +		cpu_to = per_cpu_ptr(&tegra_to, cpu);
> +		cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu);
> +		cpu_to->of_clk.rate = timer_of_rate(to);
> +		cpu_to->clkevt.cpumask = cpumask_of(cpu);
> +		cpu_to->clkevt.irq =
> +			irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu));
> +		if (!cpu_to->clkevt.irq) {
> +			pr_err("%s: can't map IRQ for CPU%d\n",
> +			       __func__, cpu);
> +			ret = -EINVAL;
> +			goto out;
> +		}
> +
> +		irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
> +		ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr,
> +				  IRQF_TIMER | IRQF_NOBALANCING,
> +				  cpu_to->clkevt.name, &cpu_to->clkevt);
> +		if (ret) {
> +			pr_err("%s: cannot setup irq %d for CPU%d\n",
> +				__func__, cpu_to->clkevt.irq, cpu);
> +			ret = -EINVAL;
> +			goto out_irq;
> +		}
> +	}
> +
> +	cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
> +			  "AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
> +			  tegra_timer_stop);
> +
> +	return ret;
> +out_irq:
> +	for_each_possible_cpu(cpu) {
> +		struct timer_of *cpu_to;
> +
> +		cpu_to = per_cpu_ptr(&tegra_to, cpu);
> +		if (cpu_to->clkevt.irq) {
> +			free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
> +			irq_dispose_mapping(cpu_to->clkevt.irq);
> +		}
>  	}
> +out:
> +	timer_of_cleanup(to);
> +	return ret;
> +}
> +#else /* CONFIG_ARM */
> +static int __init tegra_init_timer(struct device_node *np)
> +{
> +	int ret = 0;
> +
> +	ret = tegra_timer_common_init(np, &tegra_to);
> +	if (ret < 0)
> +		goto out;
>  
> -	sched_clock_register(tegra_read_sched_clock, 32, 1000000);
> +	tegra_to.of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(0);
> +	tegra_to.of_clk.rate = 1000000; /* microsecond timer */
>  
> +	sched_clock_register(tegra_read_sched_clock, 32,
> +			     timer_of_rate(&tegra_to));
>  	ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
> -				    "timer_us", 1000000, 300, 32,
> -				    clocksource_mmio_readl_up);
> +				    "timer_us", timer_of_rate(&tegra_to),
> +				    300, 32, clocksource_mmio_readl_up);
>  	if (ret) {
>  		pr_err("Failed to register clocksource\n");
> -		return ret;
> +		goto out;
>  	}
>  
>  	tegra_delay_timer.read_current_timer =
>  			tegra_delay_timer_read_counter_long;
> -	tegra_delay_timer.freq = 1000000;
> +	tegra_delay_timer.freq = timer_of_rate(&tegra_to);
>  	register_current_timer_delay(&tegra_delay_timer);
>  
> -	ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
> -	if (ret) {
> -		pr_err("Failed to register timer IRQ: %d\n", ret);
> -		return ret;
> -	}
> +	clockevents_config_and_register(&tegra_to.clkevt,
> +					timer_of_rate(&tegra_to),
> +					0x1,
> +					0x1fffffff);
>  
> -	tegra_clockevent.cpumask = cpu_possible_mask;
> -	tegra_clockevent.irq = tegra_timer_irq.irq;
> -	clockevents_config_and_register(&tegra_clockevent, 1000000,
> -					0x1, 0x1fffffff);
> +	return ret;
> +out:
> +	timer_of_cleanup(&tegra_to);
>  
> -	return 0;
> +	return ret;
>  }
> -TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
>  
>  static int __init tegra20_init_rtc(struct device_node *np)
>  {
> @@ -261,3 +406,6 @@ static int __init tegra20_init_rtc(struct device_node *np)
>  	return register_persistent_clock(tegra_read_persistent_clock64);
>  }
>  TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
> +#endif
> +TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra_init_timer);
> +TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra_init_timer);
> diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
> index fd586d0301e7..e78281d07b70 100644
> --- a/include/linux/cpuhotplug.h
> +++ b/include/linux/cpuhotplug.h
> @@ -121,6 +121,7 @@ enum cpuhp_state {
>  	CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING,
>  	CPUHP_AP_ARM_TWD_STARTING,
>  	CPUHP_AP_QCOM_TIMER_STARTING,
> +	CPUHP_AP_TEGRA_TIMER_STARTING,
>  	CPUHP_AP_ARMADA_TIMER_STARTING,
>  	CPUHP_AP_MARCO_TIMER_STARTING,
>  	CPUHP_AP_MIPS_GIC_TIMER_STARTING,
> 


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Re: [PATCH V7 2/8] clocksource: tegra: add Tegra210 timer support

[Daniel Lezcano]

On 21/02/2019 08:21, Joseph Lo wrote:
> Add support for the Tegra210 timer that runs at oscillator clock
> (TMR10-TMR13). We need these timers to work as clock event device and to
> replace the ARMv8 architected timer due to it can't survive across the
> power cycle of the CPU core or CPUPORESET signal. So it can't be a wake-up
> source when CPU suspends in power down state.
> 
> Also convert the original driver to use timer-of API.
> 
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Joseph Lo <josephl@nvidia.com>
> Acked-by: Thierry Reding <treding@nvidia.com>
> Acked-by: Jon Hunter <jonathanh@nvidia.com>
> ---

Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>

Will you take care of dropping the persistent clocksource code in this
driver?

> v7:
>  * kconfig fix for 'depends on ARM || ARM64'
>  * move suspend/resume to clkevt
>  * refine the usage for the macro of TIMER_OF_DECLARE
> v6:
>  * refine the timer defines
>  * add ack tag from Jon.
> v5:
>  * add ack tag from Thierry
> v4:
>  * merge timer-tegra210.c in previous version into timer-tegra20.c
> v3:
>  * use timer-of API
> v2:
>  * add error clean-up code
> ---
>  drivers/clocksource/Kconfig         |   3 +-
>  drivers/clocksource/timer-tegra20.c | 370 +++++++++++++++++++---------
>  include/linux/cpuhotplug.h          |   1 +
>  3 files changed, 262 insertions(+), 112 deletions(-)
> 
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 8dfd3bc448d0..5d93e580e5dc 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -131,7 +131,8 @@ config SUN5I_HSTIMER
>  config TEGRA_TIMER
>  	bool "Tegra timer driver" if COMPILE_TEST
>  	select CLKSRC_MMIO
> -	depends on ARM
> +	select TIMER_OF
> +	depends on ARM || ARM64
>  	help
>  	  Enables support for the Tegra driver.
>  
> diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c
> index 4293943f4e2b..fdb3d795a409 100644
> --- a/drivers/clocksource/timer-tegra20.c
> +++ b/drivers/clocksource/timer-tegra20.c
> @@ -15,21 +15,24 @@
>   *
>   */
>  
> -#include <linux/init.h>
> +#include <linux/clk.h>
> +#include <linux/clockchips.h>
> +#include <linux/cpu.h>
> +#include <linux/cpumask.h>
> +#include <linux/delay.h>
>  #include <linux/err.h>
> -#include <linux/time.h>
>  #include <linux/interrupt.h>
> -#include <linux/irq.h>
> -#include <linux/clockchips.h>
> -#include <linux/clocksource.h>
> -#include <linux/clk.h>
> -#include <linux/io.h>
>  #include <linux/of_address.h>
>  #include <linux/of_irq.h>
> +#include <linux/percpu.h>
>  #include <linux/sched_clock.h>
> -#include <linux/delay.h>
> +#include <linux/time.h>
> +
> +#include "timer-of.h"
>  
> +#ifdef CONFIG_ARM
>  #include <asm/mach/time.h>
> +#endif
>  
>  #define RTC_SECONDS            0x08
>  #define RTC_SHADOW_SECONDS     0x0c
> @@ -39,74 +42,161 @@
>  #define TIMERUS_USEC_CFG 0x14
>  #define TIMERUS_CNTR_FREEZE 0x4c
>  
> -#define TIMER1_BASE 0x0
> -#define TIMER2_BASE 0x8
> -#define TIMER3_BASE 0x50
> -#define TIMER4_BASE 0x58
> -
> -#define TIMER_PTV 0x0
> -#define TIMER_PCR 0x4
> -
> +#define TIMER_PTV		0x0
> +#define TIMER_PTV_EN		BIT(31)
> +#define TIMER_PTV_PER		BIT(30)
> +#define TIMER_PCR		0x4
> +#define TIMER_PCR_INTR_CLR	BIT(30)
> +
> +#ifdef CONFIG_ARM
> +#define TIMER_CPU0		0x50 /* TIMER3 */
> +#else
> +#define TIMER_CPU0		0x90 /* TIMER10 */
> +#define TIMER10_IRQ_IDX		10
> +#define IRQ_IDX_FOR_CPU(cpu)	(TIMER10_IRQ_IDX + cpu)
> +#endif
> +#define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8)
> +
> +static u32 usec_config;
>  static void __iomem *timer_reg_base;
> +#ifdef CONFIG_ARM
>  static void __iomem *rtc_base;
> -
>  static struct timespec64 persistent_ts;
>  static u64 persistent_ms, last_persistent_ms;
> -
>  static struct delay_timer tegra_delay_timer;
> -
> -#define timer_writel(value, reg) \
> -	writel_relaxed(value, timer_reg_base + (reg))
> -#define timer_readl(reg) \
> -	readl_relaxed(timer_reg_base + (reg))
> +#endif
>  
>  static int tegra_timer_set_next_event(unsigned long cycles,
>  					 struct clock_event_device *evt)
>  {
> -	u32 reg;
> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>  
> -	reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
> -	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
> +	writel(TIMER_PTV_EN |
> +	       ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
> +	       reg_base + TIMER_PTV);
>  
>  	return 0;
>  }
>  
> -static inline void timer_shutdown(struct clock_event_device *evt)
> +static int tegra_timer_shutdown(struct clock_event_device *evt)
>  {
> -	timer_writel(0, TIMER3_BASE + TIMER_PTV);
> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
> +
> +	writel(0, reg_base + TIMER_PTV);
> +
> +	return 0;
>  }
>  
> -static int tegra_timer_shutdown(struct clock_event_device *evt)
> +static int tegra_timer_set_periodic(struct clock_event_device *evt)
>  {
> -	timer_shutdown(evt);
> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
> +
> +	writel(TIMER_PTV_EN | TIMER_PTV_PER |
> +	       ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
> +	       reg_base + TIMER_PTV);
> +
>  	return 0;
>  }
>  
> -static int tegra_timer_set_periodic(struct clock_event_device *evt)
> +static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
> +{
> +	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
> +
> +	writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
> +	evt->event_handler(evt);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static void tegra_timer_suspend(struct clock_event_device *evt)
> +{
> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
> +
> +	writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
> +}
> +
> +static void tegra_timer_resume(struct clock_event_device *evt)
> +{
> +	writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
> +}
> +
> +#ifdef CONFIG_ARM64
> +static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
> +	.flags = TIMER_OF_CLOCK | TIMER_OF_BASE,
> +
> +	.clkevt = {
> +		.name = "tegra_timer",
> +		.rating = 460,
> +		.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
> +		.set_next_event = tegra_timer_set_next_event,
> +		.set_state_shutdown = tegra_timer_shutdown,
> +		.set_state_periodic = tegra_timer_set_periodic,
> +		.set_state_oneshot = tegra_timer_shutdown,
> +		.tick_resume = tegra_timer_shutdown,
> +		.suspend = tegra_timer_suspend,
> +		.resume = tegra_timer_resume,
> +	},
> +};
> +
> +static int tegra_timer_setup(unsigned int cpu)
>  {
> -	u32 reg = 0xC0000000 | ((1000000 / HZ) - 1);
> +	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
> +
> +	irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
> +	enable_irq(to->clkevt.irq);
> +
> +	clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
> +					1, /* min */
> +					0x1fffffff); /* 29 bits */
>  
> -	timer_shutdown(evt);
> -	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
>  	return 0;
>  }
>  
> -static struct clock_event_device tegra_clockevent = {
> -	.name			= "timer0",
> -	.rating			= 300,
> -	.features		= CLOCK_EVT_FEAT_ONESHOT |
> -				  CLOCK_EVT_FEAT_PERIODIC |
> -				  CLOCK_EVT_FEAT_DYNIRQ,
> -	.set_next_event		= tegra_timer_set_next_event,
> -	.set_state_shutdown	= tegra_timer_shutdown,
> -	.set_state_periodic	= tegra_timer_set_periodic,
> -	.set_state_oneshot	= tegra_timer_shutdown,
> -	.tick_resume		= tegra_timer_shutdown,
> +static int tegra_timer_stop(unsigned int cpu)
> +{
> +	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
> +
> +	to->clkevt.set_state_shutdown(&to->clkevt);
> +	disable_irq_nosync(to->clkevt.irq);
> +
> +	return 0;
> +}
> +#else /* CONFIG_ARM */
> +static struct timer_of tegra_to = {
> +	.flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ,
> +
> +	.clkevt = {
> +		.name = "tegra_timer",
> +		.rating	= 300,
> +		.features = CLOCK_EVT_FEAT_ONESHOT |
> +			    CLOCK_EVT_FEAT_PERIODIC |
> +			    CLOCK_EVT_FEAT_DYNIRQ,
> +		.set_next_event	= tegra_timer_set_next_event,
> +		.set_state_shutdown = tegra_timer_shutdown,
> +		.set_state_periodic = tegra_timer_set_periodic,
> +		.set_state_oneshot = tegra_timer_shutdown,
> +		.tick_resume = tegra_timer_shutdown,
> +		.suspend = tegra_timer_suspend,
> +		.resume = tegra_timer_resume,
> +		.cpumask = cpu_possible_mask,
> +	},
> +
> +	.of_irq = {
> +		.index = 2,
> +		.flags = IRQF_TIMER | IRQF_TRIGGER_HIGH,
> +		.handler = tegra_timer_isr,
> +	},
>  };
>  
>  static u64 notrace tegra_read_sched_clock(void)
>  {
> -	return timer_readl(TIMERUS_CNTR_1US);
> +	return readl(timer_reg_base + TIMERUS_CNTR_1US);
> +}
> +
> +static unsigned long tegra_delay_timer_read_counter_long(void)
> +{
> +	return readl(timer_reg_base + TIMERUS_CNTR_1US);
>  }
>  
>  /*
> @@ -143,100 +233,155 @@ static void tegra_read_persistent_clock64(struct timespec64 *ts)
>  	timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC);
>  	*ts = persistent_ts;
>  }
> +#endif
>  
> -static unsigned long tegra_delay_timer_read_counter_long(void)
> -{
> -	return readl(timer_reg_base + TIMERUS_CNTR_1US);
> -}
> -
> -static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
> -{
> -	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
> -	timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
> -	evt->event_handler(evt);
> -	return IRQ_HANDLED;
> -}
> -
> -static struct irqaction tegra_timer_irq = {
> -	.name		= "timer0",
> -	.flags		= IRQF_TIMER | IRQF_TRIGGER_HIGH,
> -	.handler	= tegra_timer_interrupt,
> -	.dev_id		= &tegra_clockevent,
> -};
> -
> -static int __init tegra20_init_timer(struct device_node *np)
> +static int tegra_timer_common_init(struct device_node *np, struct timer_of *to)
>  {
> -	struct clk *clk;
> -	unsigned long rate;
> -	int ret;
> -
> -	timer_reg_base = of_iomap(np, 0);
> -	if (!timer_reg_base) {
> -		pr_err("Can't map timer registers\n");
> -		return -ENXIO;
> -	}
> +	int ret = 0;
>  
> -	tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
> -	if (tegra_timer_irq.irq <= 0) {
> -		pr_err("Failed to map timer IRQ\n");
> -		return -EINVAL;
> -	}
> +	ret = timer_of_init(np, to);
> +	if (ret < 0)
> +		goto out;
>  
> -	clk = of_clk_get(np, 0);
> -	if (IS_ERR(clk)) {
> -		pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
> -		rate = 12000000;
> -	} else {
> -		clk_prepare_enable(clk);
> -		rate = clk_get_rate(clk);
> -	}
> +	timer_reg_base = timer_of_base(to);
>  
> -	switch (rate) {
> +	/*
> +	 * Configure microsecond timers to have 1MHz clock
> +	 * Config register is 0xqqww, where qq is "dividend", ww is "divisor"
> +	 * Uses n+1 scheme
> +	 */
> +	switch (timer_of_rate(to)) {
>  	case 12000000:
> -		timer_writel(0x000b, TIMERUS_USEC_CFG);
> +		usec_config = 0x000b; /* (11+1)/(0+1) */
> +		break;
> +	case 12800000:
> +		usec_config = 0x043f; /* (63+1)/(4+1) */
>  		break;
>  	case 13000000:
> -		timer_writel(0x000c, TIMERUS_USEC_CFG);
> +		usec_config = 0x000c; /* (12+1)/(0+1) */
> +		break;
> +	case 16800000:
> +		usec_config = 0x0453; /* (83+1)/(4+1) */
>  		break;
>  	case 19200000:
> -		timer_writel(0x045f, TIMERUS_USEC_CFG);
> +		usec_config = 0x045f; /* (95+1)/(4+1) */
>  		break;
>  	case 26000000:
> -		timer_writel(0x0019, TIMERUS_USEC_CFG);
> +		usec_config = 0x0019; /* (25+1)/(0+1) */
> +		break;
> +	case 38400000:
> +		usec_config = 0x04bf; /* (191+1)/(4+1) */
> +		break;
> +	case 48000000:
> +		usec_config = 0x002f; /* (47+1)/(0+1) */
>  		break;
>  	default:
> -		WARN(1, "Unknown clock rate");
> +		ret = -EINVAL;
> +		goto out;
> +	}
> +
> +	writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG);
> +
> +out:
> +	return ret;
> +}
> +
> +#ifdef CONFIG_ARM64
> +static int __init tegra_init_timer(struct device_node *np)
> +{
> +	int cpu, ret = 0;
> +	struct timer_of *to;
> +
> +	to = this_cpu_ptr(&tegra_to);
> +	ret = tegra_timer_common_init(np, to);
> +	if (ret < 0)
> +		goto out;
> +
> +	for_each_possible_cpu(cpu) {
> +		struct timer_of *cpu_to;
> +
> +		cpu_to = per_cpu_ptr(&tegra_to, cpu);
> +		cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu);
> +		cpu_to->of_clk.rate = timer_of_rate(to);
> +		cpu_to->clkevt.cpumask = cpumask_of(cpu);
> +		cpu_to->clkevt.irq =
> +			irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu));
> +		if (!cpu_to->clkevt.irq) {
> +			pr_err("%s: can't map IRQ for CPU%d\n",
> +			       __func__, cpu);
> +			ret = -EINVAL;
> +			goto out;
> +		}
> +
> +		irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
> +		ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr,
> +				  IRQF_TIMER | IRQF_NOBALANCING,
> +				  cpu_to->clkevt.name, &cpu_to->clkevt);
> +		if (ret) {
> +			pr_err("%s: cannot setup irq %d for CPU%d\n",
> +				__func__, cpu_to->clkevt.irq, cpu);
> +			ret = -EINVAL;
> +			goto out_irq;
> +		}
> +	}
> +
> +	cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
> +			  "AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
> +			  tegra_timer_stop);
> +
> +	return ret;
> +out_irq:
> +	for_each_possible_cpu(cpu) {
> +		struct timer_of *cpu_to;
> +
> +		cpu_to = per_cpu_ptr(&tegra_to, cpu);
> +		if (cpu_to->clkevt.irq) {
> +			free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
> +			irq_dispose_mapping(cpu_to->clkevt.irq);
> +		}
>  	}
> +out:
> +	timer_of_cleanup(to);
> +	return ret;
> +}
> +#else /* CONFIG_ARM */
> +static int __init tegra_init_timer(struct device_node *np)
> +{
> +	int ret = 0;
> +
> +	ret = tegra_timer_common_init(np, &tegra_to);
> +	if (ret < 0)
> +		goto out;
>  
> -	sched_clock_register(tegra_read_sched_clock, 32, 1000000);
> +	tegra_to.of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(0);
> +	tegra_to.of_clk.rate = 1000000; /* microsecond timer */
>  
> +	sched_clock_register(tegra_read_sched_clock, 32,
> +			     timer_of_rate(&tegra_to));
>  	ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
> -				    "timer_us", 1000000, 300, 32,
> -				    clocksource_mmio_readl_up);
> +				    "timer_us", timer_of_rate(&tegra_to),
> +				    300, 32, clocksource_mmio_readl_up);
>  	if (ret) {
>  		pr_err("Failed to register clocksource\n");
> -		return ret;
> +		goto out;
>  	}
>  
>  	tegra_delay_timer.read_current_timer =
>  			tegra_delay_timer_read_counter_long;
> -	tegra_delay_timer.freq = 1000000;
> +	tegra_delay_timer.freq = timer_of_rate(&tegra_to);
>  	register_current_timer_delay(&tegra_delay_timer);
>  
> -	ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
> -	if (ret) {
> -		pr_err("Failed to register timer IRQ: %d\n", ret);
> -		return ret;
> -	}
> +	clockevents_config_and_register(&tegra_to.clkevt,
> +					timer_of_rate(&tegra_to),
> +					0x1,
> +					0x1fffffff);
>  
> -	tegra_clockevent.cpumask = cpu_possible_mask;
> -	tegra_clockevent.irq = tegra_timer_irq.irq;
> -	clockevents_config_and_register(&tegra_clockevent, 1000000,
> -					0x1, 0x1fffffff);
> +	return ret;
> +out:
> +	timer_of_cleanup(&tegra_to);
>  
> -	return 0;
> +	return ret;
>  }
> -TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
>  
>  static int __init tegra20_init_rtc(struct device_node *np)
>  {
> @@ -261,3 +406,6 @@ static int __init tegra20_init_rtc(struct device_node *np)
>  	return register_persistent_clock(tegra_read_persistent_clock64);
>  }
>  TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
> +#endif
> +TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra_init_timer);
> +TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra_init_timer);
> diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
> index fd586d0301e7..e78281d07b70 100644
> --- a/include/linux/cpuhotplug.h
> +++ b/include/linux/cpuhotplug.h
> @@ -121,6 +121,7 @@ enum cpuhp_state {
>  	CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING,
>  	CPUHP_AP_ARM_TWD_STARTING,
>  	CPUHP_AP_QCOM_TIMER_STARTING,
> +	CPUHP_AP_TEGRA_TIMER_STARTING,
>  	CPUHP_AP_ARMADA_TIMER_STARTING,
>  	CPUHP_AP_MARCO_TIMER_STARTING,
>  	CPUHP_AP_MIPS_GIC_TIMER_STARTING,
> 


-- 
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Re: [PATCH V7 2/8] clocksource: tegra: add Tegra210 timer support

[Joseph Lo]

On 2/22/19 4:43 PM, Daniel Lezcano wrote:
> On 21/02/2019 08:21, Joseph Lo wrote:
>> Add support for the Tegra210 timer that runs at oscillator clock
>> (TMR10-TMR13). We need these timers to work as clock event device and to
>> replace the ARMv8 architected timer due to it can't survive across the
>> power cycle of the CPU core or CPUPORESET signal. So it can't be a wake-up
>> source when CPU suspends in power down state.
>>
>> Also convert the original driver to use timer-of API.
>>
>> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
>> Cc: Thomas Gleixner <tglx@linutronix.de>
>> Cc: linux-kernel@vger.kernel.org
>> Signed-off-by: Joseph Lo <josephl@nvidia.com>
>> Acked-by: Thierry Reding <treding@nvidia.com>
>> Acked-by: Jon Hunter <jonathanh@nvidia.com>
>> ---
> 
> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>

Hi Daniel,

Thanks for your review again. Regarding to Thierry's suggestion in [1], 
could you help to pick up patch 1~3 in this series in clocksource tree?

[1]: https://patchwork.ozlabs.org/patch/1034075/

If not, I'll let him know this series needs to go with Tegra tree.

> 
> Will you take care of dropping the persistent clocksource code in this
> driver?

Yes, will do.

Thanks,
Joseph

> 
>> v7:
>>   * kconfig fix for 'depends on ARM || ARM64'
>>   * move suspend/resume to clkevt
>>   * refine the usage for the macro of TIMER_OF_DECLARE
>> v6:
>>   * refine the timer defines
>>   * add ack tag from Jon.
>> v5:
>>   * add ack tag from Thierry
>> v4:
>>   * merge timer-tegra210.c in previous version into timer-tegra20.c
>> v3:
>>   * use timer-of API
>> v2:
>>   * add error clean-up code
>> ---
>>   drivers/clocksource/Kconfig         |   3 +-
>>   drivers/clocksource/timer-tegra20.c | 370 +++++++++++++++++++---------
>>   include/linux/cpuhotplug.h          |   1 +
>>   3 files changed, 262 insertions(+), 112 deletions(-)
>>
>> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
>> index 8dfd3bc448d0..5d93e580e5dc 100644
>> --- a/drivers/clocksource/Kconfig
>> +++ b/drivers/clocksource/Kconfig
>> @@ -131,7 +131,8 @@ config SUN5I_HSTIMER
>>   config TEGRA_TIMER
>>   	bool "Tegra timer driver" if COMPILE_TEST
>>   	select CLKSRC_MMIO
>> -	depends on ARM
>> +	select TIMER_OF
>> +	depends on ARM || ARM64
>>   	help
>>   	  Enables support for the Tegra driver.
>>   
>> diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c
>> index 4293943f4e2b..fdb3d795a409 100644
>> --- a/drivers/clocksource/timer-tegra20.c
>> +++ b/drivers/clocksource/timer-tegra20.c
>> @@ -15,21 +15,24 @@
>>    *
>>    */
>>   
>> -#include <linux/init.h>
>> +#include <linux/clk.h>
>> +#include <linux/clockchips.h>
>> +#include <linux/cpu.h>
>> +#include <linux/cpumask.h>
>> +#include <linux/delay.h>
>>   #include <linux/err.h>
>> -#include <linux/time.h>
>>   #include <linux/interrupt.h>
>> -#include <linux/irq.h>
>> -#include <linux/clockchips.h>
>> -#include <linux/clocksource.h>
>> -#include <linux/clk.h>
>> -#include <linux/io.h>
>>   #include <linux/of_address.h>
>>   #include <linux/of_irq.h>
>> +#include <linux/percpu.h>
>>   #include <linux/sched_clock.h>
>> -#include <linux/delay.h>
>> +#include <linux/time.h>
>> +
>> +#include "timer-of.h"
>>   
>> +#ifdef CONFIG_ARM
>>   #include <asm/mach/time.h>
>> +#endif
>>   
>>   #define RTC_SECONDS            0x08
>>   #define RTC_SHADOW_SECONDS     0x0c
>> @@ -39,74 +42,161 @@
>>   #define TIMERUS_USEC_CFG 0x14
>>   #define TIMERUS_CNTR_FREEZE 0x4c
>>   
>> -#define TIMER1_BASE 0x0
>> -#define TIMER2_BASE 0x8
>> -#define TIMER3_BASE 0x50
>> -#define TIMER4_BASE 0x58
>> -
>> -#define TIMER_PTV 0x0
>> -#define TIMER_PCR 0x4
>> -
>> +#define TIMER_PTV		0x0
>> +#define TIMER_PTV_EN		BIT(31)
>> +#define TIMER_PTV_PER		BIT(30)
>> +#define TIMER_PCR		0x4
>> +#define TIMER_PCR_INTR_CLR	BIT(30)
>> +
>> +#ifdef CONFIG_ARM
>> +#define TIMER_CPU0		0x50 /* TIMER3 */
>> +#else
>> +#define TIMER_CPU0		0x90 /* TIMER10 */
>> +#define TIMER10_IRQ_IDX		10
>> +#define IRQ_IDX_FOR_CPU(cpu)	(TIMER10_IRQ_IDX + cpu)
>> +#endif
>> +#define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8)
>> +
>> +static u32 usec_config;
>>   static void __iomem *timer_reg_base;
>> +#ifdef CONFIG_ARM
>>   static void __iomem *rtc_base;
>> -
>>   static struct timespec64 persistent_ts;
>>   static u64 persistent_ms, last_persistent_ms;
>> -
>>   static struct delay_timer tegra_delay_timer;
>> -
>> -#define timer_writel(value, reg) \
>> -	writel_relaxed(value, timer_reg_base + (reg))
>> -#define timer_readl(reg) \
>> -	readl_relaxed(timer_reg_base + (reg))
>> +#endif
>>   
>>   static int tegra_timer_set_next_event(unsigned long cycles,
>>   					 struct clock_event_device *evt)
>>   {
>> -	u32 reg;
>> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>>   
>> -	reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
>> -	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
>> +	writel(TIMER_PTV_EN |
>> +	       ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
>> +	       reg_base + TIMER_PTV);
>>   
>>   	return 0;
>>   }
>>   
>> -static inline void timer_shutdown(struct clock_event_device *evt)
>> +static int tegra_timer_shutdown(struct clock_event_device *evt)
>>   {
>> -	timer_writel(0, TIMER3_BASE + TIMER_PTV);
>> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>> +
>> +	writel(0, reg_base + TIMER_PTV);
>> +
>> +	return 0;
>>   }
>>   
>> -static int tegra_timer_shutdown(struct clock_event_device *evt)
>> +static int tegra_timer_set_periodic(struct clock_event_device *evt)
>>   {
>> -	timer_shutdown(evt);
>> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>> +
>> +	writel(TIMER_PTV_EN | TIMER_PTV_PER |
>> +	       ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
>> +	       reg_base + TIMER_PTV);
>> +
>>   	return 0;
>>   }
>>   
>> -static int tegra_timer_set_periodic(struct clock_event_device *evt)
>> +static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
>> +{
>> +	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
>> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>> +
>> +	writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
>> +	evt->event_handler(evt);
>> +
>> +	return IRQ_HANDLED;
>> +}
>> +
>> +static void tegra_timer_suspend(struct clock_event_device *evt)
>> +{
>> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>> +
>> +	writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
>> +}
>> +
>> +static void tegra_timer_resume(struct clock_event_device *evt)
>> +{
>> +	writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
>> +}
>> +
>> +#ifdef CONFIG_ARM64
>> +static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
>> +	.flags = TIMER_OF_CLOCK | TIMER_OF_BASE,
>> +
>> +	.clkevt = {
>> +		.name = "tegra_timer",
>> +		.rating = 460,
>> +		.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
>> +		.set_next_event = tegra_timer_set_next_event,
>> +		.set_state_shutdown = tegra_timer_shutdown,
>> +		.set_state_periodic = tegra_timer_set_periodic,
>> +		.set_state_oneshot = tegra_timer_shutdown,
>> +		.tick_resume = tegra_timer_shutdown,
>> +		.suspend = tegra_timer_suspend,
>> +		.resume = tegra_timer_resume,
>> +	},
>> +};
>> +
>> +static int tegra_timer_setup(unsigned int cpu)
>>   {
>> -	u32 reg = 0xC0000000 | ((1000000 / HZ) - 1);
>> +	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
>> +
>> +	irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
>> +	enable_irq(to->clkevt.irq);
>> +
>> +	clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
>> +					1, /* min */
>> +					0x1fffffff); /* 29 bits */
>>   
>> -	timer_shutdown(evt);
>> -	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
>>   	return 0;
>>   }
>>   
>> -static struct clock_event_device tegra_clockevent = {
>> -	.name			= "timer0",
>> -	.rating			= 300,
>> -	.features		= CLOCK_EVT_FEAT_ONESHOT |
>> -				  CLOCK_EVT_FEAT_PERIODIC |
>> -				  CLOCK_EVT_FEAT_DYNIRQ,
>> -	.set_next_event		= tegra_timer_set_next_event,
>> -	.set_state_shutdown	= tegra_timer_shutdown,
>> -	.set_state_periodic	= tegra_timer_set_periodic,
>> -	.set_state_oneshot	= tegra_timer_shutdown,
>> -	.tick_resume		= tegra_timer_shutdown,
>> +static int tegra_timer_stop(unsigned int cpu)
>> +{
>> +	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
>> +
>> +	to->clkevt.set_state_shutdown(&to->clkevt);
>> +	disable_irq_nosync(to->clkevt.irq);
>> +
>> +	return 0;
>> +}
>> +#else /* CONFIG_ARM */
>> +static struct timer_of tegra_to = {
>> +	.flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ,
>> +
>> +	.clkevt = {
>> +		.name = "tegra_timer",
>> +		.rating	= 300,
>> +		.features = CLOCK_EVT_FEAT_ONESHOT |
>> +			    CLOCK_EVT_FEAT_PERIODIC |
>> +			    CLOCK_EVT_FEAT_DYNIRQ,
>> +		.set_next_event	= tegra_timer_set_next_event,
>> +		.set_state_shutdown = tegra_timer_shutdown,
>> +		.set_state_periodic = tegra_timer_set_periodic,
>> +		.set_state_oneshot = tegra_timer_shutdown,
>> +		.tick_resume = tegra_timer_shutdown,
>> +		.suspend = tegra_timer_suspend,
>> +		.resume = tegra_timer_resume,
>> +		.cpumask = cpu_possible_mask,
>> +	},
>> +
>> +	.of_irq = {
>> +		.index = 2,
>> +		.flags = IRQF_TIMER | IRQF_TRIGGER_HIGH,
>> +		.handler = tegra_timer_isr,
>> +	},
>>   };
>>   
>>   static u64 notrace tegra_read_sched_clock(void)
>>   {
>> -	return timer_readl(TIMERUS_CNTR_1US);
>> +	return readl(timer_reg_base + TIMERUS_CNTR_1US);
>> +}
>> +
>> +static unsigned long tegra_delay_timer_read_counter_long(void)
>> +{
>> +	return readl(timer_reg_base + TIMERUS_CNTR_1US);
>>   }
>>   
>>   /*
>> @@ -143,100 +233,155 @@ static void tegra_read_persistent_clock64(struct timespec64 *ts)
>>   	timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC);
>>   	*ts = persistent_ts;
>>   }
>> +#endif
>>   
>> -static unsigned long tegra_delay_timer_read_counter_long(void)
>> -{
>> -	return readl(timer_reg_base + TIMERUS_CNTR_1US);
>> -}
>> -
>> -static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
>> -{
>> -	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
>> -	timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
>> -	evt->event_handler(evt);
>> -	return IRQ_HANDLED;
>> -}
>> -
>> -static struct irqaction tegra_timer_irq = {
>> -	.name		= "timer0",
>> -	.flags		= IRQF_TIMER | IRQF_TRIGGER_HIGH,
>> -	.handler	= tegra_timer_interrupt,
>> -	.dev_id		= &tegra_clockevent,
>> -};
>> -
>> -static int __init tegra20_init_timer(struct device_node *np)
>> +static int tegra_timer_common_init(struct device_node *np, struct timer_of *to)
>>   {
>> -	struct clk *clk;
>> -	unsigned long rate;
>> -	int ret;
>> -
>> -	timer_reg_base = of_iomap(np, 0);
>> -	if (!timer_reg_base) {
>> -		pr_err("Can't map timer registers\n");
>> -		return -ENXIO;
>> -	}
>> +	int ret = 0;
>>   
>> -	tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
>> -	if (tegra_timer_irq.irq <= 0) {
>> -		pr_err("Failed to map timer IRQ\n");
>> -		return -EINVAL;
>> -	}
>> +	ret = timer_of_init(np, to);
>> +	if (ret < 0)
>> +		goto out;
>>   
>> -	clk = of_clk_get(np, 0);
>> -	if (IS_ERR(clk)) {
>> -		pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
>> -		rate = 12000000;
>> -	} else {
>> -		clk_prepare_enable(clk);
>> -		rate = clk_get_rate(clk);
>> -	}
>> +	timer_reg_base = timer_of_base(to);
>>   
>> -	switch (rate) {
>> +	/*
>> +	 * Configure microsecond timers to have 1MHz clock
>> +	 * Config register is 0xqqww, where qq is "dividend", ww is "divisor"
>> +	 * Uses n+1 scheme
>> +	 */
>> +	switch (timer_of_rate(to)) {
>>   	case 12000000:
>> -		timer_writel(0x000b, TIMERUS_USEC_CFG);
>> +		usec_config = 0x000b; /* (11+1)/(0+1) */
>> +		break;
>> +	case 12800000:
>> +		usec_config = 0x043f; /* (63+1)/(4+1) */
>>   		break;
>>   	case 13000000:
>> -		timer_writel(0x000c, TIMERUS_USEC_CFG);
>> +		usec_config = 0x000c; /* (12+1)/(0+1) */
>> +		break;
>> +	case 16800000:
>> +		usec_config = 0x0453; /* (83+1)/(4+1) */
>>   		break;
>>   	case 19200000:
>> -		timer_writel(0x045f, TIMERUS_USEC_CFG);
>> +		usec_config = 0x045f; /* (95+1)/(4+1) */
>>   		break;
>>   	case 26000000:
>> -		timer_writel(0x0019, TIMERUS_USEC_CFG);
>> +		usec_config = 0x0019; /* (25+1)/(0+1) */
>> +		break;
>> +	case 38400000:
>> +		usec_config = 0x04bf; /* (191+1)/(4+1) */
>> +		break;
>> +	case 48000000:
>> +		usec_config = 0x002f; /* (47+1)/(0+1) */
>>   		break;
>>   	default:
>> -		WARN(1, "Unknown clock rate");
>> +		ret = -EINVAL;
>> +		goto out;
>> +	}
>> +
>> +	writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG);
>> +
>> +out:
>> +	return ret;
>> +}
>> +
>> +#ifdef CONFIG_ARM64
>> +static int __init tegra_init_timer(struct device_node *np)
>> +{
>> +	int cpu, ret = 0;
>> +	struct timer_of *to;
>> +
>> +	to = this_cpu_ptr(&tegra_to);
>> +	ret = tegra_timer_common_init(np, to);
>> +	if (ret < 0)
>> +		goto out;
>> +
>> +	for_each_possible_cpu(cpu) {
>> +		struct timer_of *cpu_to;
>> +
>> +		cpu_to = per_cpu_ptr(&tegra_to, cpu);
>> +		cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu);
>> +		cpu_to->of_clk.rate = timer_of_rate(to);
>> +		cpu_to->clkevt.cpumask = cpumask_of(cpu);
>> +		cpu_to->clkevt.irq =
>> +			irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu));
>> +		if (!cpu_to->clkevt.irq) {
>> +			pr_err("%s: can't map IRQ for CPU%d\n",
>> +			       __func__, cpu);
>> +			ret = -EINVAL;
>> +			goto out;
>> +		}
>> +
>> +		irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
>> +		ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr,
>> +				  IRQF_TIMER | IRQF_NOBALANCING,
>> +				  cpu_to->clkevt.name, &cpu_to->clkevt);
>> +		if (ret) {
>> +			pr_err("%s: cannot setup irq %d for CPU%d\n",
>> +				__func__, cpu_to->clkevt.irq, cpu);
>> +			ret = -EINVAL;
>> +			goto out_irq;
>> +		}
>> +	}
>> +
>> +	cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
>> +			  "AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
>> +			  tegra_timer_stop);
>> +
>> +	return ret;
>> +out_irq:
>> +	for_each_possible_cpu(cpu) {
>> +		struct timer_of *cpu_to;
>> +
>> +		cpu_to = per_cpu_ptr(&tegra_to, cpu);
>> +		if (cpu_to->clkevt.irq) {
>> +			free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
>> +			irq_dispose_mapping(cpu_to->clkevt.irq);
>> +		}
>>   	}
>> +out:
>> +	timer_of_cleanup(to);
>> +	return ret;
>> +}
>> +#else /* CONFIG_ARM */
>> +static int __init tegra_init_timer(struct device_node *np)
>> +{
>> +	int ret = 0;
>> +
>> +	ret = tegra_timer_common_init(np, &tegra_to);
>> +	if (ret < 0)
>> +		goto out;
>>   
>> -	sched_clock_register(tegra_read_sched_clock, 32, 1000000);
>> +	tegra_to.of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(0);
>> +	tegra_to.of_clk.rate = 1000000; /* microsecond timer */
>>   
>> +	sched_clock_register(tegra_read_sched_clock, 32,
>> +			     timer_of_rate(&tegra_to));
>>   	ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
>> -				    "timer_us", 1000000, 300, 32,
>> -				    clocksource_mmio_readl_up);
>> +				    "timer_us", timer_of_rate(&tegra_to),
>> +				    300, 32, clocksource_mmio_readl_up);
>>   	if (ret) {
>>   		pr_err("Failed to register clocksource\n");
>> -		return ret;
>> +		goto out;
>>   	}
>>   
>>   	tegra_delay_timer.read_current_timer =
>>   			tegra_delay_timer_read_counter_long;
>> -	tegra_delay_timer.freq = 1000000;
>> +	tegra_delay_timer.freq = timer_of_rate(&tegra_to);
>>   	register_current_timer_delay(&tegra_delay_timer);
>>   
>> -	ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
>> -	if (ret) {
>> -		pr_err("Failed to register timer IRQ: %d\n", ret);
>> -		return ret;
>> -	}
>> +	clockevents_config_and_register(&tegra_to.clkevt,
>> +					timer_of_rate(&tegra_to),
>> +					0x1,
>> +					0x1fffffff);
>>   
>> -	tegra_clockevent.cpumask = cpu_possible_mask;
>> -	tegra_clockevent.irq = tegra_timer_irq.irq;
>> -	clockevents_config_and_register(&tegra_clockevent, 1000000,
>> -					0x1, 0x1fffffff);
>> +	return ret;
>> +out:
>> +	timer_of_cleanup(&tegra_to);
>>   
>> -	return 0;
>> +	return ret;
>>   }
>> -TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
>>   
>>   static int __init tegra20_init_rtc(struct device_node *np)
>>   {
>> @@ -261,3 +406,6 @@ static int __init tegra20_init_rtc(struct device_node *np)
>>   	return register_persistent_clock(tegra_read_persistent_clock64);
>>   }
>>   TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
>> +#endif
>> +TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra_init_timer);
>> +TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra_init_timer);
>> diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
>> index fd586d0301e7..e78281d07b70 100644
>> --- a/include/linux/cpuhotplug.h
>> +++ b/include/linux/cpuhotplug.h
>> @@ -121,6 +121,7 @@ enum cpuhp_state {
>>   	CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING,
>>   	CPUHP_AP_ARM_TWD_STARTING,
>>   	CPUHP_AP_QCOM_TIMER_STARTING,
>> +	CPUHP_AP_TEGRA_TIMER_STARTING,
>>   	CPUHP_AP_ARMADA_TIMER_STARTING,
>>   	CPUHP_AP_MARCO_TIMER_STARTING,
>>   	CPUHP_AP_MIPS_GIC_TIMER_STARTING,
>>
> 
> 

Re: [PATCH V7 2/8] clocksource: tegra: add Tegra210 timer support

[Joseph Lo]

On 2/22/19 4:43 PM, Daniel Lezcano wrote:
> On 21/02/2019 08:21, Joseph Lo wrote:
>> Add support for the Tegra210 timer that runs at oscillator clock
>> (TMR10-TMR13). We need these timers to work as clock event device and to
>> replace the ARMv8 architected timer due to it can't survive across the
>> power cycle of the CPU core or CPUPORESET signal. So it can't be a wake-up
>> source when CPU suspends in power down state.
>>
>> Also convert the original driver to use timer-of API.
>>
>> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
>> Cc: Thomas Gleixner <tglx@linutronix.de>
>> Cc: linux-kernel@vger.kernel.org
>> Signed-off-by: Joseph Lo <josephl@nvidia.com>
>> Acked-by: Thierry Reding <treding@nvidia.com>
>> Acked-by: Jon Hunter <jonathanh@nvidia.com>
>> ---
> 
> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>

Hi Daniel,

Thanks for your review again. Regarding to Thierry's suggestion in [1], 
could you help to pick up patch 1~3 in this series in clocksource tree?

[1]: https://patchwork.ozlabs.org/patch/1034075/

If not, I'll let him know this series needs to go with Tegra tree.

> 
> Will you take care of dropping the persistent clocksource code in this
> driver?

Yes, will do.

Thanks,
Joseph

> 
>> v7:
>>   * kconfig fix for 'depends on ARM || ARM64'
>>   * move suspend/resume to clkevt
>>   * refine the usage for the macro of TIMER_OF_DECLARE
>> v6:
>>   * refine the timer defines
>>   * add ack tag from Jon.
>> v5:
>>   * add ack tag from Thierry
>> v4:
>>   * merge timer-tegra210.c in previous version into timer-tegra20.c
>> v3:
>>   * use timer-of API
>> v2:
>>   * add error clean-up code
>> ---
>>   drivers/clocksource/Kconfig         |   3 +-
>>   drivers/clocksource/timer-tegra20.c | 370 +++++++++++++++++++---------
>>   include/linux/cpuhotplug.h          |   1 +
>>   3 files changed, 262 insertions(+), 112 deletions(-)
>>
>> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
>> index 8dfd3bc448d0..5d93e580e5dc 100644
>> --- a/drivers/clocksource/Kconfig
>> +++ b/drivers/clocksource/Kconfig
>> @@ -131,7 +131,8 @@ config SUN5I_HSTIMER
>>   config TEGRA_TIMER
>>   	bool "Tegra timer driver" if COMPILE_TEST
>>   	select CLKSRC_MMIO
>> -	depends on ARM
>> +	select TIMER_OF
>> +	depends on ARM || ARM64
>>   	help
>>   	  Enables support for the Tegra driver.
>>   
>> diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c
>> index 4293943f4e2b..fdb3d795a409 100644
>> --- a/drivers/clocksource/timer-tegra20.c
>> +++ b/drivers/clocksource/timer-tegra20.c
>> @@ -15,21 +15,24 @@
>>    *
>>    */
>>   
>> -#include <linux/init.h>
>> +#include <linux/clk.h>
>> +#include <linux/clockchips.h>
>> +#include <linux/cpu.h>
>> +#include <linux/cpumask.h>
>> +#include <linux/delay.h>
>>   #include <linux/err.h>
>> -#include <linux/time.h>
>>   #include <linux/interrupt.h>
>> -#include <linux/irq.h>
>> -#include <linux/clockchips.h>
>> -#include <linux/clocksource.h>
>> -#include <linux/clk.h>
>> -#include <linux/io.h>
>>   #include <linux/of_address.h>
>>   #include <linux/of_irq.h>
>> +#include <linux/percpu.h>
>>   #include <linux/sched_clock.h>
>> -#include <linux/delay.h>
>> +#include <linux/time.h>
>> +
>> +#include "timer-of.h"
>>   
>> +#ifdef CONFIG_ARM
>>   #include <asm/mach/time.h>
>> +#endif
>>   
>>   #define RTC_SECONDS            0x08
>>   #define RTC_SHADOW_SECONDS     0x0c
>> @@ -39,74 +42,161 @@
>>   #define TIMERUS_USEC_CFG 0x14
>>   #define TIMERUS_CNTR_FREEZE 0x4c
>>   
>> -#define TIMER1_BASE 0x0
>> -#define TIMER2_BASE 0x8
>> -#define TIMER3_BASE 0x50
>> -#define TIMER4_BASE 0x58
>> -
>> -#define TIMER_PTV 0x0
>> -#define TIMER_PCR 0x4
>> -
>> +#define TIMER_PTV		0x0
>> +#define TIMER_PTV_EN		BIT(31)
>> +#define TIMER_PTV_PER		BIT(30)
>> +#define TIMER_PCR		0x4
>> +#define TIMER_PCR_INTR_CLR	BIT(30)
>> +
>> +#ifdef CONFIG_ARM
>> +#define TIMER_CPU0		0x50 /* TIMER3 */
>> +#else
>> +#define TIMER_CPU0		0x90 /* TIMER10 */
>> +#define TIMER10_IRQ_IDX		10
>> +#define IRQ_IDX_FOR_CPU(cpu)	(TIMER10_IRQ_IDX + cpu)
>> +#endif
>> +#define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8)
>> +
>> +static u32 usec_config;
>>   static void __iomem *timer_reg_base;
>> +#ifdef CONFIG_ARM
>>   static void __iomem *rtc_base;
>> -
>>   static struct timespec64 persistent_ts;
>>   static u64 persistent_ms, last_persistent_ms;
>> -
>>   static struct delay_timer tegra_delay_timer;
>> -
>> -#define timer_writel(value, reg) \
>> -	writel_relaxed(value, timer_reg_base + (reg))
>> -#define timer_readl(reg) \
>> -	readl_relaxed(timer_reg_base + (reg))
>> +#endif
>>   
>>   static int tegra_timer_set_next_event(unsigned long cycles,
>>   					 struct clock_event_device *evt)
>>   {
>> -	u32 reg;
>> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>>   
>> -	reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
>> -	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
>> +	writel(TIMER_PTV_EN |
>> +	       ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
>> +	       reg_base + TIMER_PTV);
>>   
>>   	return 0;
>>   }
>>   
>> -static inline void timer_shutdown(struct clock_event_device *evt)
>> +static int tegra_timer_shutdown(struct clock_event_device *evt)
>>   {
>> -	timer_writel(0, TIMER3_BASE + TIMER_PTV);
>> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>> +
>> +	writel(0, reg_base + TIMER_PTV);
>> +
>> +	return 0;
>>   }
>>   
>> -static int tegra_timer_shutdown(struct clock_event_device *evt)
>> +static int tegra_timer_set_periodic(struct clock_event_device *evt)
>>   {
>> -	timer_shutdown(evt);
>> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>> +
>> +	writel(TIMER_PTV_EN | TIMER_PTV_PER |
>> +	       ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
>> +	       reg_base + TIMER_PTV);
>> +
>>   	return 0;
>>   }
>>   
>> -static int tegra_timer_set_periodic(struct clock_event_device *evt)
>> +static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
>> +{
>> +	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
>> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>> +
>> +	writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
>> +	evt->event_handler(evt);
>> +
>> +	return IRQ_HANDLED;
>> +}
>> +
>> +static void tegra_timer_suspend(struct clock_event_device *evt)
>> +{
>> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>> +
>> +	writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
>> +}
>> +
>> +static void tegra_timer_resume(struct clock_event_device *evt)
>> +{
>> +	writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
>> +}
>> +
>> +#ifdef CONFIG_ARM64
>> +static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
>> +	.flags = TIMER_OF_CLOCK | TIMER_OF_BASE,
>> +
>> +	.clkevt = {
>> +		.name = "tegra_timer",
>> +		.rating = 460,
>> +		.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
>> +		.set_next_event = tegra_timer_set_next_event,
>> +		.set_state_shutdown = tegra_timer_shutdown,
>> +		.set_state_periodic = tegra_timer_set_periodic,
>> +		.set_state_oneshot = tegra_timer_shutdown,
>> +		.tick_resume = tegra_timer_shutdown,
>> +		.suspend = tegra_timer_suspend,
>> +		.resume = tegra_timer_resume,
>> +	},
>> +};
>> +
>> +static int tegra_timer_setup(unsigned int cpu)
>>   {
>> -	u32 reg = 0xC0000000 | ((1000000 / HZ) - 1);
>> +	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
>> +
>> +	irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
>> +	enable_irq(to->clkevt.irq);
>> +
>> +	clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
>> +					1, /* min */
>> +					0x1fffffff); /* 29 bits */
>>   
>> -	timer_shutdown(evt);
>> -	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
>>   	return 0;
>>   }
>>   
>> -static struct clock_event_device tegra_clockevent = {
>> -	.name			= "timer0",
>> -	.rating			= 300,
>> -	.features		= CLOCK_EVT_FEAT_ONESHOT |
>> -				  CLOCK_EVT_FEAT_PERIODIC |
>> -				  CLOCK_EVT_FEAT_DYNIRQ,
>> -	.set_next_event		= tegra_timer_set_next_event,
>> -	.set_state_shutdown	= tegra_timer_shutdown,
>> -	.set_state_periodic	= tegra_timer_set_periodic,
>> -	.set_state_oneshot	= tegra_timer_shutdown,
>> -	.tick_resume		= tegra_timer_shutdown,
>> +static int tegra_timer_stop(unsigned int cpu)
>> +{
>> +	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
>> +
>> +	to->clkevt.set_state_shutdown(&to->clkevt);
>> +	disable_irq_nosync(to->clkevt.irq);
>> +
>> +	return 0;
>> +}
>> +#else /* CONFIG_ARM */
>> +static struct timer_of tegra_to = {
>> +	.flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ,
>> +
>> +	.clkevt = {
>> +		.name = "tegra_timer",
>> +		.rating	= 300,
>> +		.features = CLOCK_EVT_FEAT_ONESHOT |
>> +			    CLOCK_EVT_FEAT_PERIODIC |
>> +			    CLOCK_EVT_FEAT_DYNIRQ,
>> +		.set_next_event	= tegra_timer_set_next_event,
>> +		.set_state_shutdown = tegra_timer_shutdown,
>> +		.set_state_periodic = tegra_timer_set_periodic,
>> +		.set_state_oneshot = tegra_timer_shutdown,
>> +		.tick_resume = tegra_timer_shutdown,
>> +		.suspend = tegra_timer_suspend,
>> +		.resume = tegra_timer_resume,
>> +		.cpumask = cpu_possible_mask,
>> +	},
>> +
>> +	.of_irq = {
>> +		.index = 2,
>> +		.flags = IRQF_TIMER | IRQF_TRIGGER_HIGH,
>> +		.handler = tegra_timer_isr,
>> +	},
>>   };
>>   
>>   static u64 notrace tegra_read_sched_clock(void)
>>   {
>> -	return timer_readl(TIMERUS_CNTR_1US);
>> +	return readl(timer_reg_base + TIMERUS_CNTR_1US);
>> +}
>> +
>> +static unsigned long tegra_delay_timer_read_counter_long(void)
>> +{
>> +	return readl(timer_reg_base + TIMERUS_CNTR_1US);
>>   }
>>   
>>   /*
>> @@ -143,100 +233,155 @@ static void tegra_read_persistent_clock64(struct timespec64 *ts)
>>   	timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC);
>>   	*ts = persistent_ts;
>>   }
>> +#endif
>>   
>> -static unsigned long tegra_delay_timer_read_counter_long(void)
>> -{
>> -	return readl(timer_reg_base + TIMERUS_CNTR_1US);
>> -}
>> -
>> -static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
>> -{
>> -	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
>> -	timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
>> -	evt->event_handler(evt);
>> -	return IRQ_HANDLED;
>> -}
>> -
>> -static struct irqaction tegra_timer_irq = {
>> -	.name		= "timer0",
>> -	.flags		= IRQF_TIMER | IRQF_TRIGGER_HIGH,
>> -	.handler	= tegra_timer_interrupt,
>> -	.dev_id		= &tegra_clockevent,
>> -};
>> -
>> -static int __init tegra20_init_timer(struct device_node *np)
>> +static int tegra_timer_common_init(struct device_node *np, struct timer_of *to)
>>   {
>> -	struct clk *clk;
>> -	unsigned long rate;
>> -	int ret;
>> -
>> -	timer_reg_base = of_iomap(np, 0);
>> -	if (!timer_reg_base) {
>> -		pr_err("Can't map timer registers\n");
>> -		return -ENXIO;
>> -	}
>> +	int ret = 0;
>>   
>> -	tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
>> -	if (tegra_timer_irq.irq <= 0) {
>> -		pr_err("Failed to map timer IRQ\n");
>> -		return -EINVAL;
>> -	}
>> +	ret = timer_of_init(np, to);
>> +	if (ret < 0)
>> +		goto out;
>>   
>> -	clk = of_clk_get(np, 0);
>> -	if (IS_ERR(clk)) {
>> -		pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
>> -		rate = 12000000;
>> -	} else {
>> -		clk_prepare_enable(clk);
>> -		rate = clk_get_rate(clk);
>> -	}
>> +	timer_reg_base = timer_of_base(to);
>>   
>> -	switch (rate) {
>> +	/*
>> +	 * Configure microsecond timers to have 1MHz clock
>> +	 * Config register is 0xqqww, where qq is "dividend", ww is "divisor"
>> +	 * Uses n+1 scheme
>> +	 */
>> +	switch (timer_of_rate(to)) {
>>   	case 12000000:
>> -		timer_writel(0x000b, TIMERUS_USEC_CFG);
>> +		usec_config = 0x000b; /* (11+1)/(0+1) */
>> +		break;
>> +	case 12800000:
>> +		usec_config = 0x043f; /* (63+1)/(4+1) */
>>   		break;
>>   	case 13000000:
>> -		timer_writel(0x000c, TIMERUS_USEC_CFG);
>> +		usec_config = 0x000c; /* (12+1)/(0+1) */
>> +		break;
>> +	case 16800000:
>> +		usec_config = 0x0453; /* (83+1)/(4+1) */
>>   		break;
>>   	case 19200000:
>> -		timer_writel(0x045f, TIMERUS_USEC_CFG);
>> +		usec_config = 0x045f; /* (95+1)/(4+1) */
>>   		break;
>>   	case 26000000:
>> -		timer_writel(0x0019, TIMERUS_USEC_CFG);
>> +		usec_config = 0x0019; /* (25+1)/(0+1) */
>> +		break;
>> +	case 38400000:
>> +		usec_config = 0x04bf; /* (191+1)/(4+1) */
>> +		break;
>> +	case 48000000:
>> +		usec_config = 0x002f; /* (47+1)/(0+1) */
>>   		break;
>>   	default:
>> -		WARN(1, "Unknown clock rate");
>> +		ret = -EINVAL;
>> +		goto out;
>> +	}
>> +
>> +	writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG);
>> +
>> +out:
>> +	return ret;
>> +}
>> +
>> +#ifdef CONFIG_ARM64
>> +static int __init tegra_init_timer(struct device_node *np)
>> +{
>> +	int cpu, ret = 0;
>> +	struct timer_of *to;
>> +
>> +	to = this_cpu_ptr(&tegra_to);
>> +	ret = tegra_timer_common_init(np, to);
>> +	if (ret < 0)
>> +		goto out;
>> +
>> +	for_each_possible_cpu(cpu) {
>> +		struct timer_of *cpu_to;
>> +
>> +		cpu_to = per_cpu_ptr(&tegra_to, cpu);
>> +		cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu);
>> +		cpu_to->of_clk.rate = timer_of_rate(to);
>> +		cpu_to->clkevt.cpumask = cpumask_of(cpu);
>> +		cpu_to->clkevt.irq =
>> +			irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu));
>> +		if (!cpu_to->clkevt.irq) {
>> +			pr_err("%s: can't map IRQ for CPU%d\n",
>> +			       __func__, cpu);
>> +			ret = -EINVAL;
>> +			goto out;
>> +		}
>> +
>> +		irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
>> +		ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr,
>> +				  IRQF_TIMER | IRQF_NOBALANCING,
>> +				  cpu_to->clkevt.name, &cpu_to->clkevt);
>> +		if (ret) {
>> +			pr_err("%s: cannot setup irq %d for CPU%d\n",
>> +				__func__, cpu_to->clkevt.irq, cpu);
>> +			ret = -EINVAL;
>> +			goto out_irq;
>> +		}
>> +	}
>> +
>> +	cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
>> +			  "AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
>> +			  tegra_timer_stop);
>> +
>> +	return ret;
>> +out_irq:
>> +	for_each_possible_cpu(cpu) {
>> +		struct timer_of *cpu_to;
>> +
>> +		cpu_to = per_cpu_ptr(&tegra_to, cpu);
>> +		if (cpu_to->clkevt.irq) {
>> +			free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
>> +			irq_dispose_mapping(cpu_to->clkevt.irq);
>> +		}
>>   	}
>> +out:
>> +	timer_of_cleanup(to);
>> +	return ret;
>> +}
>> +#else /* CONFIG_ARM */
>> +static int __init tegra_init_timer(struct device_node *np)
>> +{
>> +	int ret = 0;
>> +
>> +	ret = tegra_timer_common_init(np, &tegra_to);
>> +	if (ret < 0)
>> +		goto out;
>>   
>> -	sched_clock_register(tegra_read_sched_clock, 32, 1000000);
>> +	tegra_to.of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(0);
>> +	tegra_to.of_clk.rate = 1000000; /* microsecond timer */
>>   
>> +	sched_clock_register(tegra_read_sched_clock, 32,
>> +			     timer_of_rate(&tegra_to));
>>   	ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
>> -				    "timer_us", 1000000, 300, 32,
>> -				    clocksource_mmio_readl_up);
>> +				    "timer_us", timer_of_rate(&tegra_to),
>> +				    300, 32, clocksource_mmio_readl_up);
>>   	if (ret) {
>>   		pr_err("Failed to register clocksource\n");
>> -		return ret;
>> +		goto out;
>>   	}
>>   
>>   	tegra_delay_timer.read_current_timer =
>>   			tegra_delay_timer_read_counter_long;
>> -	tegra_delay_timer.freq = 1000000;
>> +	tegra_delay_timer.freq = timer_of_rate(&tegra_to);
>>   	register_current_timer_delay(&tegra_delay_timer);
>>   
>> -	ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
>> -	if (ret) {
>> -		pr_err("Failed to register timer IRQ: %d\n", ret);
>> -		return ret;
>> -	}
>> +	clockevents_config_and_register(&tegra_to.clkevt,
>> +					timer_of_rate(&tegra_to),
>> +					0x1,
>> +					0x1fffffff);
>>   
>> -	tegra_clockevent.cpumask = cpu_possible_mask;
>> -	tegra_clockevent.irq = tegra_timer_irq.irq;
>> -	clockevents_config_and_register(&tegra_clockevent, 1000000,
>> -					0x1, 0x1fffffff);
>> +	return ret;
>> +out:
>> +	timer_of_cleanup(&tegra_to);
>>   
>> -	return 0;
>> +	return ret;
>>   }
>> -TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
>>   
>>   static int __init tegra20_init_rtc(struct device_node *np)
>>   {
>> @@ -261,3 +406,6 @@ static int __init tegra20_init_rtc(struct device_node *np)
>>   	return register_persistent_clock(tegra_read_persistent_clock64);
>>   }
>>   TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
>> +#endif
>> +TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra_init_timer);
>> +TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra_init_timer);
>> diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
>> index fd586d0301e7..e78281d07b70 100644
>> --- a/include/linux/cpuhotplug.h
>> +++ b/include/linux/cpuhotplug.h
>> @@ -121,6 +121,7 @@ enum cpuhp_state {
>>   	CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING,
>>   	CPUHP_AP_ARM_TWD_STARTING,
>>   	CPUHP_AP_QCOM_TIMER_STARTING,
>> +	CPUHP_AP_TEGRA_TIMER_STARTING,
>>   	CPUHP_AP_ARMADA_TIMER_STARTING,
>>   	CPUHP_AP_MARCO_TIMER_STARTING,
>>   	CPUHP_AP_MIPS_GIC_TIMER_STARTING,
>>
> 
> 

Re: [PATCH V7 2/8] clocksource: tegra: add Tegra210 timer support

[Joseph Lo]

On 2/22/19 4:43 PM, Daniel Lezcano wrote:
> On 21/02/2019 08:21, Joseph Lo wrote:
>> Add support for the Tegra210 timer that runs at oscillator clock
>> (TMR10-TMR13). We need these timers to work as clock event device and to
>> replace the ARMv8 architected timer due to it can't survive across the
>> power cycle of the CPU core or CPUPORESET signal. So it can't be a wake-up
>> source when CPU suspends in power down state.
>>
>> Also convert the original driver to use timer-of API.
>>
>> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
>> Cc: Thomas Gleixner <tglx@linutronix.de>
>> Cc: linux-kernel@vger.kernel.org
>> Signed-off-by: Joseph Lo <josephl@nvidia.com>
>> Acked-by: Thierry Reding <treding@nvidia.com>
>> Acked-by: Jon Hunter <jonathanh@nvidia.com>
>> ---
> 
> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>

Hi Daniel,

Thanks for your review again. Regarding to Thierry's suggestion in [1], 
could you help to pick up patch 1~3 in this series in clocksource tree?

[1]: https://patchwork.ozlabs.org/patch/1034075/

If not, I'll let him know this series needs to go with Tegra tree.

> 
> Will you take care of dropping the persistent clocksource code in this
> driver?

Yes, will do.

Thanks,
Joseph

> 
>> v7:
>>   * kconfig fix for 'depends on ARM || ARM64'
>>   * move suspend/resume to clkevt
>>   * refine the usage for the macro of TIMER_OF_DECLARE
>> v6:
>>   * refine the timer defines
>>   * add ack tag from Jon.
>> v5:
>>   * add ack tag from Thierry
>> v4:
>>   * merge timer-tegra210.c in previous version into timer-tegra20.c
>> v3:
>>   * use timer-of API
>> v2:
>>   * add error clean-up code
>> ---
>>   drivers/clocksource/Kconfig         |   3 +-
>>   drivers/clocksource/timer-tegra20.c | 370 +++++++++++++++++++---------
>>   include/linux/cpuhotplug.h          |   1 +
>>   3 files changed, 262 insertions(+), 112 deletions(-)
>>
>> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
>> index 8dfd3bc448d0..5d93e580e5dc 100644
>> --- a/drivers/clocksource/Kconfig
>> +++ b/drivers/clocksource/Kconfig
>> @@ -131,7 +131,8 @@ config SUN5I_HSTIMER
>>   config TEGRA_TIMER
>>   	bool "Tegra timer driver" if COMPILE_TEST
>>   	select CLKSRC_MMIO
>> -	depends on ARM
>> +	select TIMER_OF
>> +	depends on ARM || ARM64
>>   	help
>>   	  Enables support for the Tegra driver.
>>   
>> diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c
>> index 4293943f4e2b..fdb3d795a409 100644
>> --- a/drivers/clocksource/timer-tegra20.c
>> +++ b/drivers/clocksource/timer-tegra20.c
>> @@ -15,21 +15,24 @@
>>    *
>>    */
>>   
>> -#include <linux/init.h>
>> +#include <linux/clk.h>
>> +#include <linux/clockchips.h>
>> +#include <linux/cpu.h>
>> +#include <linux/cpumask.h>
>> +#include <linux/delay.h>
>>   #include <linux/err.h>
>> -#include <linux/time.h>
>>   #include <linux/interrupt.h>
>> -#include <linux/irq.h>
>> -#include <linux/clockchips.h>
>> -#include <linux/clocksource.h>
>> -#include <linux/clk.h>
>> -#include <linux/io.h>
>>   #include <linux/of_address.h>
>>   #include <linux/of_irq.h>
>> +#include <linux/percpu.h>
>>   #include <linux/sched_clock.h>
>> -#include <linux/delay.h>
>> +#include <linux/time.h>
>> +
>> +#include "timer-of.h"
>>   
>> +#ifdef CONFIG_ARM
>>   #include <asm/mach/time.h>
>> +#endif
>>   
>>   #define RTC_SECONDS            0x08
>>   #define RTC_SHADOW_SECONDS     0x0c
>> @@ -39,74 +42,161 @@
>>   #define TIMERUS_USEC_CFG 0x14
>>   #define TIMERUS_CNTR_FREEZE 0x4c
>>   
>> -#define TIMER1_BASE 0x0
>> -#define TIMER2_BASE 0x8
>> -#define TIMER3_BASE 0x50
>> -#define TIMER4_BASE 0x58
>> -
>> -#define TIMER_PTV 0x0
>> -#define TIMER_PCR 0x4
>> -
>> +#define TIMER_PTV		0x0
>> +#define TIMER_PTV_EN		BIT(31)
>> +#define TIMER_PTV_PER		BIT(30)
>> +#define TIMER_PCR		0x4
>> +#define TIMER_PCR_INTR_CLR	BIT(30)
>> +
>> +#ifdef CONFIG_ARM
>> +#define TIMER_CPU0		0x50 /* TIMER3 */
>> +#else
>> +#define TIMER_CPU0		0x90 /* TIMER10 */
>> +#define TIMER10_IRQ_IDX		10
>> +#define IRQ_IDX_FOR_CPU(cpu)	(TIMER10_IRQ_IDX + cpu)
>> +#endif
>> +#define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8)
>> +
>> +static u32 usec_config;
>>   static void __iomem *timer_reg_base;
>> +#ifdef CONFIG_ARM
>>   static void __iomem *rtc_base;
>> -
>>   static struct timespec64 persistent_ts;
>>   static u64 persistent_ms, last_persistent_ms;
>> -
>>   static struct delay_timer tegra_delay_timer;
>> -
>> -#define timer_writel(value, reg) \
>> -	writel_relaxed(value, timer_reg_base + (reg))
>> -#define timer_readl(reg) \
>> -	readl_relaxed(timer_reg_base + (reg))
>> +#endif
>>   
>>   static int tegra_timer_set_next_event(unsigned long cycles,
>>   					 struct clock_event_device *evt)
>>   {
>> -	u32 reg;
>> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>>   
>> -	reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
>> -	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
>> +	writel(TIMER_PTV_EN |
>> +	       ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
>> +	       reg_base + TIMER_PTV);
>>   
>>   	return 0;
>>   }
>>   
>> -static inline void timer_shutdown(struct clock_event_device *evt)
>> +static int tegra_timer_shutdown(struct clock_event_device *evt)
>>   {
>> -	timer_writel(0, TIMER3_BASE + TIMER_PTV);
>> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>> +
>> +	writel(0, reg_base + TIMER_PTV);
>> +
>> +	return 0;
>>   }
>>   
>> -static int tegra_timer_shutdown(struct clock_event_device *evt)
>> +static int tegra_timer_set_periodic(struct clock_event_device *evt)
>>   {
>> -	timer_shutdown(evt);
>> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>> +
>> +	writel(TIMER_PTV_EN | TIMER_PTV_PER |
>> +	       ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
>> +	       reg_base + TIMER_PTV);
>> +
>>   	return 0;
>>   }
>>   
>> -static int tegra_timer_set_periodic(struct clock_event_device *evt)
>> +static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
>> +{
>> +	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
>> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>> +
>> +	writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
>> +	evt->event_handler(evt);
>> +
>> +	return IRQ_HANDLED;
>> +}
>> +
>> +static void tegra_timer_suspend(struct clock_event_device *evt)
>> +{
>> +	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>> +
>> +	writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
>> +}
>> +
>> +static void tegra_timer_resume(struct clock_event_device *evt)
>> +{
>> +	writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
>> +}
>> +
>> +#ifdef CONFIG_ARM64
>> +static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
>> +	.flags = TIMER_OF_CLOCK | TIMER_OF_BASE,
>> +
>> +	.clkevt = {
>> +		.name = "tegra_timer",
>> +		.rating = 460,
>> +		.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
>> +		.set_next_event = tegra_timer_set_next_event,
>> +		.set_state_shutdown = tegra_timer_shutdown,
>> +		.set_state_periodic = tegra_timer_set_periodic,
>> +		.set_state_oneshot = tegra_timer_shutdown,
>> +		.tick_resume = tegra_timer_shutdown,
>> +		.suspend = tegra_timer_suspend,
>> +		.resume = tegra_timer_resume,
>> +	},
>> +};
>> +
>> +static int tegra_timer_setup(unsigned int cpu)
>>   {
>> -	u32 reg = 0xC0000000 | ((1000000 / HZ) - 1);
>> +	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
>> +
>> +	irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
>> +	enable_irq(to->clkevt.irq);
>> +
>> +	clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
>> +					1, /* min */
>> +					0x1fffffff); /* 29 bits */
>>   
>> -	timer_shutdown(evt);
>> -	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
>>   	return 0;
>>   }
>>   
>> -static struct clock_event_device tegra_clockevent = {
>> -	.name			= "timer0",
>> -	.rating			= 300,
>> -	.features		= CLOCK_EVT_FEAT_ONESHOT |
>> -				  CLOCK_EVT_FEAT_PERIODIC |
>> -				  CLOCK_EVT_FEAT_DYNIRQ,
>> -	.set_next_event		= tegra_timer_set_next_event,
>> -	.set_state_shutdown	= tegra_timer_shutdown,
>> -	.set_state_periodic	= tegra_timer_set_periodic,
>> -	.set_state_oneshot	= tegra_timer_shutdown,
>> -	.tick_resume		= tegra_timer_shutdown,
>> +static int tegra_timer_stop(unsigned int cpu)
>> +{
>> +	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
>> +
>> +	to->clkevt.set_state_shutdown(&to->clkevt);
>> +	disable_irq_nosync(to->clkevt.irq);
>> +
>> +	return 0;
>> +}
>> +#else /* CONFIG_ARM */
>> +static struct timer_of tegra_to = {
>> +	.flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ,
>> +
>> +	.clkevt = {
>> +		.name = "tegra_timer",
>> +		.rating	= 300,
>> +		.features = CLOCK_EVT_FEAT_ONESHOT |
>> +			    CLOCK_EVT_FEAT_PERIODIC |
>> +			    CLOCK_EVT_FEAT_DYNIRQ,
>> +		.set_next_event	= tegra_timer_set_next_event,
>> +		.set_state_shutdown = tegra_timer_shutdown,
>> +		.set_state_periodic = tegra_timer_set_periodic,
>> +		.set_state_oneshot = tegra_timer_shutdown,
>> +		.tick_resume = tegra_timer_shutdown,
>> +		.suspend = tegra_timer_suspend,
>> +		.resume = tegra_timer_resume,
>> +		.cpumask = cpu_possible_mask,
>> +	},
>> +
>> +	.of_irq = {
>> +		.index = 2,
>> +		.flags = IRQF_TIMER | IRQF_TRIGGER_HIGH,
>> +		.handler = tegra_timer_isr,
>> +	},
>>   };
>>   
>>   static u64 notrace tegra_read_sched_clock(void)
>>   {
>> -	return timer_readl(TIMERUS_CNTR_1US);
>> +	return readl(timer_reg_base + TIMERUS_CNTR_1US);
>> +}
>> +
>> +static unsigned long tegra_delay_timer_read_counter_long(void)
>> +{
>> +	return readl(timer_reg_base + TIMERUS_CNTR_1US);
>>   }
>>   
>>   /*
>> @@ -143,100 +233,155 @@ static void tegra_read_persistent_clock64(struct timespec64 *ts)
>>   	timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC);
>>   	*ts = persistent_ts;
>>   }
>> +#endif
>>   
>> -static unsigned long tegra_delay_timer_read_counter_long(void)
>> -{
>> -	return readl(timer_reg_base + TIMERUS_CNTR_1US);
>> -}
>> -
>> -static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
>> -{
>> -	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
>> -	timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
>> -	evt->event_handler(evt);
>> -	return IRQ_HANDLED;
>> -}
>> -
>> -static struct irqaction tegra_timer_irq = {
>> -	.name		= "timer0",
>> -	.flags		= IRQF_TIMER | IRQF_TRIGGER_HIGH,
>> -	.handler	= tegra_timer_interrupt,
>> -	.dev_id		= &tegra_clockevent,
>> -};
>> -
>> -static int __init tegra20_init_timer(struct device_node *np)
>> +static int tegra_timer_common_init(struct device_node *np, struct timer_of *to)
>>   {
>> -	struct clk *clk;
>> -	unsigned long rate;
>> -	int ret;
>> -
>> -	timer_reg_base = of_iomap(np, 0);
>> -	if (!timer_reg_base) {
>> -		pr_err("Can't map timer registers\n");
>> -		return -ENXIO;
>> -	}
>> +	int ret = 0;
>>   
>> -	tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
>> -	if (tegra_timer_irq.irq <= 0) {
>> -		pr_err("Failed to map timer IRQ\n");
>> -		return -EINVAL;
>> -	}
>> +	ret = timer_of_init(np, to);
>> +	if (ret < 0)
>> +		goto out;
>>   
>> -	clk = of_clk_get(np, 0);
>> -	if (IS_ERR(clk)) {
>> -		pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
>> -		rate = 12000000;
>> -	} else {
>> -		clk_prepare_enable(clk);
>> -		rate = clk_get_rate(clk);
>> -	}
>> +	timer_reg_base = timer_of_base(to);
>>   
>> -	switch (rate) {
>> +	/*
>> +	 * Configure microsecond timers to have 1MHz clock
>> +	 * Config register is 0xqqww, where qq is "dividend", ww is "divisor"
>> +	 * Uses n+1 scheme
>> +	 */
>> +	switch (timer_of_rate(to)) {
>>   	case 12000000:
>> -		timer_writel(0x000b, TIMERUS_USEC_CFG);
>> +		usec_config = 0x000b; /* (11+1)/(0+1) */
>> +		break;
>> +	case 12800000:
>> +		usec_config = 0x043f; /* (63+1)/(4+1) */
>>   		break;
>>   	case 13000000:
>> -		timer_writel(0x000c, TIMERUS_USEC_CFG);
>> +		usec_config = 0x000c; /* (12+1)/(0+1) */
>> +		break;
>> +	case 16800000:
>> +		usec_config = 0x0453; /* (83+1)/(4+1) */
>>   		break;
>>   	case 19200000:
>> -		timer_writel(0x045f, TIMERUS_USEC_CFG);
>> +		usec_config = 0x045f; /* (95+1)/(4+1) */
>>   		break;
>>   	case 26000000:
>> -		timer_writel(0x0019, TIMERUS_USEC_CFG);
>> +		usec_config = 0x0019; /* (25+1)/(0+1) */
>> +		break;
>> +	case 38400000:
>> +		usec_config = 0x04bf; /* (191+1)/(4+1) */
>> +		break;
>> +	case 48000000:
>> +		usec_config = 0x002f; /* (47+1)/(0+1) */
>>   		break;
>>   	default:
>> -		WARN(1, "Unknown clock rate");
>> +		ret = -EINVAL;
>> +		goto out;
>> +	}
>> +
>> +	writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG);
>> +
>> +out:
>> +	return ret;
>> +}
>> +
>> +#ifdef CONFIG_ARM64
>> +static int __init tegra_init_timer(struct device_node *np)
>> +{
>> +	int cpu, ret = 0;
>> +	struct timer_of *to;
>> +
>> +	to = this_cpu_ptr(&tegra_to);
>> +	ret = tegra_timer_common_init(np, to);
>> +	if (ret < 0)
>> +		goto out;
>> +
>> +	for_each_possible_cpu(cpu) {
>> +		struct timer_of *cpu_to;
>> +
>> +		cpu_to = per_cpu_ptr(&tegra_to, cpu);
>> +		cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu);
>> +		cpu_to->of_clk.rate = timer_of_rate(to);
>> +		cpu_to->clkevt.cpumask = cpumask_of(cpu);
>> +		cpu_to->clkevt.irq =
>> +			irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu));
>> +		if (!cpu_to->clkevt.irq) {
>> +			pr_err("%s: can't map IRQ for CPU%d\n",
>> +			       __func__, cpu);
>> +			ret = -EINVAL;
>> +			goto out;
>> +		}
>> +
>> +		irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
>> +		ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr,
>> +				  IRQF_TIMER | IRQF_NOBALANCING,
>> +				  cpu_to->clkevt.name, &cpu_to->clkevt);
>> +		if (ret) {
>> +			pr_err("%s: cannot setup irq %d for CPU%d\n",
>> +				__func__, cpu_to->clkevt.irq, cpu);
>> +			ret = -EINVAL;
>> +			goto out_irq;
>> +		}
>> +	}
>> +
>> +	cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
>> +			  "AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
>> +			  tegra_timer_stop);
>> +
>> +	return ret;
>> +out_irq:
>> +	for_each_possible_cpu(cpu) {
>> +		struct timer_of *cpu_to;
>> +
>> +		cpu_to = per_cpu_ptr(&tegra_to, cpu);
>> +		if (cpu_to->clkevt.irq) {
>> +			free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
>> +			irq_dispose_mapping(cpu_to->clkevt.irq);
>> +		}
>>   	}
>> +out:
>> +	timer_of_cleanup(to);
>> +	return ret;
>> +}
>> +#else /* CONFIG_ARM */
>> +static int __init tegra_init_timer(struct device_node *np)
>> +{
>> +	int ret = 0;
>> +
>> +	ret = tegra_timer_common_init(np, &tegra_to);
>> +	if (ret < 0)
>> +		goto out;
>>   
>> -	sched_clock_register(tegra_read_sched_clock, 32, 1000000);
>> +	tegra_to.of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(0);
>> +	tegra_to.of_clk.rate = 1000000; /* microsecond timer */
>>   
>> +	sched_clock_register(tegra_read_sched_clock, 32,
>> +			     timer_of_rate(&tegra_to));
>>   	ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
>> -				    "timer_us", 1000000, 300, 32,
>> -				    clocksource_mmio_readl_up);
>> +				    "timer_us", timer_of_rate(&tegra_to),
>> +				    300, 32, clocksource_mmio_readl_up);
>>   	if (ret) {
>>   		pr_err("Failed to register clocksource\n");
>> -		return ret;
>> +		goto out;
>>   	}
>>   
>>   	tegra_delay_timer.read_current_timer =
>>   			tegra_delay_timer_read_counter_long;
>> -	tegra_delay_timer.freq = 1000000;
>> +	tegra_delay_timer.freq = timer_of_rate(&tegra_to);
>>   	register_current_timer_delay(&tegra_delay_timer);
>>   
>> -	ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
>> -	if (ret) {
>> -		pr_err("Failed to register timer IRQ: %d\n", ret);
>> -		return ret;
>> -	}
>> +	clockevents_config_and_register(&tegra_to.clkevt,
>> +					timer_of_rate(&tegra_to),
>> +					0x1,
>> +					0x1fffffff);
>>   
>> -	tegra_clockevent.cpumask = cpu_possible_mask;
>> -	tegra_clockevent.irq = tegra_timer_irq.irq;
>> -	clockevents_config_and_register(&tegra_clockevent, 1000000,
>> -					0x1, 0x1fffffff);
>> +	return ret;
>> +out:
>> +	timer_of_cleanup(&tegra_to);
>>   
>> -	return 0;
>> +	return ret;
>>   }
>> -TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
>>   
>>   static int __init tegra20_init_rtc(struct device_node *np)
>>   {
>> @@ -261,3 +406,6 @@ static int __init tegra20_init_rtc(struct device_node *np)
>>   	return register_persistent_clock(tegra_read_persistent_clock64);
>>   }
>>   TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
>> +#endif
>> +TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra_init_timer);
>> +TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra_init_timer);
>> diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
>> index fd586d0301e7..e78281d07b70 100644
>> --- a/include/linux/cpuhotplug.h
>> +++ b/include/linux/cpuhotplug.h
>> @@ -121,6 +121,7 @@ enum cpuhp_state {
>>   	CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING,
>>   	CPUHP_AP_ARM_TWD_STARTING,
>>   	CPUHP_AP_QCOM_TIMER_STARTING,
>> +	CPUHP_AP_TEGRA_TIMER_STARTING,
>>   	CPUHP_AP_ARMADA_TIMER_STARTING,
>>   	CPUHP_AP_MARCO_TIMER_STARTING,
>>   	CPUHP_AP_MIPS_GIC_TIMER_STARTING,
>>
> 
> 

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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH V7 2/8] clocksource: tegra: add Tegra210 timer support

[Daniel Lezcano]

On 22/02/2019 10:06, Joseph Lo wrote:
> 
> 
> On 2/22/19 4:43 PM, Daniel Lezcano wrote:
>> On 21/02/2019 08:21, Joseph Lo wrote:
>>> Add support for the Tegra210 timer that runs at oscillator clock
>>> (TMR10-TMR13). We need these timers to work as clock event device and to
>>> replace the ARMv8 architected timer due to it can't survive across the
>>> power cycle of the CPU core or CPUPORESET signal. So it can't be a
>>> wake-up
>>> source when CPU suspends in power down state.
>>>
>>> Also convert the original driver to use timer-of API.
>>>
>>> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
>>> Cc: Thomas Gleixner <tglx@linutronix.de>
>>> Cc: linux-kernel@vger.kernel.org
>>> Signed-off-by: Joseph Lo <josephl@nvidia.com>
>>> Acked-by: Thierry Reding <treding@nvidia.com>
>>> Acked-by: Jon Hunter <jonathanh@nvidia.com>
>>> ---
>>
>> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> 
> Hi Daniel,
> 
> Thanks for your review again. Regarding to Thierry's suggestion in [1],
> could you help to pick up patch 1~3 in this series in clocksource tree?

Ok, as they have the maintainer acked-by tag, I've picked them up for 5.1

Thanks

  -- Daniel


> [1]: https://patchwork.ozlabs.org/patch/1034075/
> 
> If not, I'll let him know this series needs to go with Tegra tree.
> 
>>
>> Will you take care of dropping the persistent clocksource code in this
>> driver?
> 
> Yes, will do.
> 
> Thanks,
> Joseph
> 
>>
>>> v7:
>>>   * kconfig fix for 'depends on ARM || ARM64'
>>>   * move suspend/resume to clkevt
>>>   * refine the usage for the macro of TIMER_OF_DECLARE
>>> v6:
>>>   * refine the timer defines
>>>   * add ack tag from Jon.
>>> v5:
>>>   * add ack tag from Thierry
>>> v4:
>>>   * merge timer-tegra210.c in previous version into timer-tegra20.c
>>> v3:
>>>   * use timer-of API
>>> v2:
>>>   * add error clean-up code
>>> ---
>>>   drivers/clocksource/Kconfig         |   3 +-
>>>   drivers/clocksource/timer-tegra20.c | 370 +++++++++++++++++++---------
>>>   include/linux/cpuhotplug.h          |   1 +
>>>   3 files changed, 262 insertions(+), 112 deletions(-)
>>>
>>> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
>>> index 8dfd3bc448d0..5d93e580e5dc 100644
>>> --- a/drivers/clocksource/Kconfig
>>> +++ b/drivers/clocksource/Kconfig
>>> @@ -131,7 +131,8 @@ config SUN5I_HSTIMER
>>>   config TEGRA_TIMER
>>>       bool "Tegra timer driver" if COMPILE_TEST
>>>       select CLKSRC_MMIO
>>> -    depends on ARM
>>> +    select TIMER_OF
>>> +    depends on ARM || ARM64
>>>       help
>>>         Enables support for the Tegra driver.
>>>   diff --git a/drivers/clocksource/timer-tegra20.c
>>> b/drivers/clocksource/timer-tegra20.c
>>> index 4293943f4e2b..fdb3d795a409 100644
>>> --- a/drivers/clocksource/timer-tegra20.c
>>> +++ b/drivers/clocksource/timer-tegra20.c
>>> @@ -15,21 +15,24 @@
>>>    *
>>>    */
>>>   -#include <linux/init.h>
>>> +#include <linux/clk.h>
>>> +#include <linux/clockchips.h>
>>> +#include <linux/cpu.h>
>>> +#include <linux/cpumask.h>
>>> +#include <linux/delay.h>
>>>   #include <linux/err.h>
>>> -#include <linux/time.h>
>>>   #include <linux/interrupt.h>
>>> -#include <linux/irq.h>
>>> -#include <linux/clockchips.h>
>>> -#include <linux/clocksource.h>
>>> -#include <linux/clk.h>
>>> -#include <linux/io.h>
>>>   #include <linux/of_address.h>
>>>   #include <linux/of_irq.h>
>>> +#include <linux/percpu.h>
>>>   #include <linux/sched_clock.h>
>>> -#include <linux/delay.h>
>>> +#include <linux/time.h>
>>> +
>>> +#include "timer-of.h"
>>>   +#ifdef CONFIG_ARM
>>>   #include <asm/mach/time.h>
>>> +#endif
>>>     #define RTC_SECONDS            0x08
>>>   #define RTC_SHADOW_SECONDS     0x0c
>>> @@ -39,74 +42,161 @@
>>>   #define TIMERUS_USEC_CFG 0x14
>>>   #define TIMERUS_CNTR_FREEZE 0x4c
>>>   -#define TIMER1_BASE 0x0
>>> -#define TIMER2_BASE 0x8
>>> -#define TIMER3_BASE 0x50
>>> -#define TIMER4_BASE 0x58
>>> -
>>> -#define TIMER_PTV 0x0
>>> -#define TIMER_PCR 0x4
>>> -
>>> +#define TIMER_PTV        0x0
>>> +#define TIMER_PTV_EN        BIT(31)
>>> +#define TIMER_PTV_PER        BIT(30)
>>> +#define TIMER_PCR        0x4
>>> +#define TIMER_PCR_INTR_CLR    BIT(30)
>>> +
>>> +#ifdef CONFIG_ARM
>>> +#define TIMER_CPU0        0x50 /* TIMER3 */
>>> +#else
>>> +#define TIMER_CPU0        0x90 /* TIMER10 */
>>> +#define TIMER10_IRQ_IDX        10
>>> +#define IRQ_IDX_FOR_CPU(cpu)    (TIMER10_IRQ_IDX + cpu)
>>> +#endif
>>> +#define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8)
>>> +
>>> +static u32 usec_config;
>>>   static void __iomem *timer_reg_base;
>>> +#ifdef CONFIG_ARM
>>>   static void __iomem *rtc_base;
>>> -
>>>   static struct timespec64 persistent_ts;
>>>   static u64 persistent_ms, last_persistent_ms;
>>> -
>>>   static struct delay_timer tegra_delay_timer;
>>> -
>>> -#define timer_writel(value, reg) \
>>> -    writel_relaxed(value, timer_reg_base + (reg))
>>> -#define timer_readl(reg) \
>>> -    readl_relaxed(timer_reg_base + (reg))
>>> +#endif
>>>     static int tegra_timer_set_next_event(unsigned long cycles,
>>>                        struct clock_event_device *evt)
>>>   {
>>> -    u32 reg;
>>> +    void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>>>   -    reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
>>> -    timer_writel(reg, TIMER3_BASE + TIMER_PTV);
>>> +    writel(TIMER_PTV_EN |
>>> +           ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
>>> +           reg_base + TIMER_PTV);
>>>         return 0;
>>>   }
>>>   -static inline void timer_shutdown(struct clock_event_device *evt)
>>> +static int tegra_timer_shutdown(struct clock_event_device *evt)
>>>   {
>>> -    timer_writel(0, TIMER3_BASE + TIMER_PTV);
>>> +    void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>>> +
>>> +    writel(0, reg_base + TIMER_PTV);
>>> +
>>> +    return 0;
>>>   }
>>>   -static int tegra_timer_shutdown(struct clock_event_device *evt)
>>> +static int tegra_timer_set_periodic(struct clock_event_device *evt)
>>>   {
>>> -    timer_shutdown(evt);
>>> +    void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>>> +
>>> +    writel(TIMER_PTV_EN | TIMER_PTV_PER |
>>> +           ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
>>> +           reg_base + TIMER_PTV);
>>> +
>>>       return 0;
>>>   }
>>>   -static int tegra_timer_set_periodic(struct clock_event_device *evt)
>>> +static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
>>> +{
>>> +    struct clock_event_device *evt = (struct clock_event_device
>>> *)dev_id;
>>> +    void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>>> +
>>> +    writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
>>> +    evt->event_handler(evt);
>>> +
>>> +    return IRQ_HANDLED;
>>> +}
>>> +
>>> +static void tegra_timer_suspend(struct clock_event_device *evt)
>>> +{
>>> +    void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>>> +
>>> +    writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
>>> +}
>>> +
>>> +static void tegra_timer_resume(struct clock_event_device *evt)
>>> +{
>>> +    writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
>>> +}
>>> +
>>> +#ifdef CONFIG_ARM64
>>> +static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
>>> +    .flags = TIMER_OF_CLOCK | TIMER_OF_BASE,
>>> +
>>> +    .clkevt = {
>>> +        .name = "tegra_timer",
>>> +        .rating = 460,
>>> +        .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
>>> +        .set_next_event = tegra_timer_set_next_event,
>>> +        .set_state_shutdown = tegra_timer_shutdown,
>>> +        .set_state_periodic = tegra_timer_set_periodic,
>>> +        .set_state_oneshot = tegra_timer_shutdown,
>>> +        .tick_resume = tegra_timer_shutdown,
>>> +        .suspend = tegra_timer_suspend,
>>> +        .resume = tegra_timer_resume,
>>> +    },
>>> +};
>>> +
>>> +static int tegra_timer_setup(unsigned int cpu)
>>>   {
>>> -    u32 reg = 0xC0000000 | ((1000000 / HZ) - 1);
>>> +    struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
>>> +
>>> +    irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
>>> +    enable_irq(to->clkevt.irq);
>>> +
>>> +    clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
>>> +                    1, /* min */
>>> +                    0x1fffffff); /* 29 bits */
>>>   -    timer_shutdown(evt);
>>> -    timer_writel(reg, TIMER3_BASE + TIMER_PTV);
>>>       return 0;
>>>   }
>>>   -static struct clock_event_device tegra_clockevent = {
>>> -    .name            = "timer0",
>>> -    .rating            = 300,
>>> -    .features        = CLOCK_EVT_FEAT_ONESHOT |
>>> -                  CLOCK_EVT_FEAT_PERIODIC |
>>> -                  CLOCK_EVT_FEAT_DYNIRQ,
>>> -    .set_next_event        = tegra_timer_set_next_event,
>>> -    .set_state_shutdown    = tegra_timer_shutdown,
>>> -    .set_state_periodic    = tegra_timer_set_periodic,
>>> -    .set_state_oneshot    = tegra_timer_shutdown,
>>> -    .tick_resume        = tegra_timer_shutdown,
>>> +static int tegra_timer_stop(unsigned int cpu)
>>> +{
>>> +    struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
>>> +
>>> +    to->clkevt.set_state_shutdown(&to->clkevt);
>>> +    disable_irq_nosync(to->clkevt.irq);
>>> +
>>> +    return 0;
>>> +}
>>> +#else /* CONFIG_ARM */
>>> +static struct timer_of tegra_to = {
>>> +    .flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ,
>>> +
>>> +    .clkevt = {
>>> +        .name = "tegra_timer",
>>> +        .rating    = 300,
>>> +        .features = CLOCK_EVT_FEAT_ONESHOT |
>>> +                CLOCK_EVT_FEAT_PERIODIC |
>>> +                CLOCK_EVT_FEAT_DYNIRQ,
>>> +        .set_next_event    = tegra_timer_set_next_event,
>>> +        .set_state_shutdown = tegra_timer_shutdown,
>>> +        .set_state_periodic = tegra_timer_set_periodic,
>>> +        .set_state_oneshot = tegra_timer_shutdown,
>>> +        .tick_resume = tegra_timer_shutdown,
>>> +        .suspend = tegra_timer_suspend,
>>> +        .resume = tegra_timer_resume,
>>> +        .cpumask = cpu_possible_mask,
>>> +    },
>>> +
>>> +    .of_irq = {
>>> +        .index = 2,
>>> +        .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH,
>>> +        .handler = tegra_timer_isr,
>>> +    },
>>>   };
>>>     static u64 notrace tegra_read_sched_clock(void)
>>>   {
>>> -    return timer_readl(TIMERUS_CNTR_1US);
>>> +    return readl(timer_reg_base + TIMERUS_CNTR_1US);
>>> +}
>>> +
>>> +static unsigned long tegra_delay_timer_read_counter_long(void)
>>> +{
>>> +    return readl(timer_reg_base + TIMERUS_CNTR_1US);
>>>   }
>>>     /*
>>> @@ -143,100 +233,155 @@ static void
>>> tegra_read_persistent_clock64(struct timespec64 *ts)
>>>       timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC);
>>>       *ts = persistent_ts;
>>>   }
>>> +#endif
>>>   -static unsigned long tegra_delay_timer_read_counter_long(void)
>>> -{
>>> -    return readl(timer_reg_base + TIMERUS_CNTR_1US);
>>> -}
>>> -
>>> -static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
>>> -{
>>> -    struct clock_event_device *evt = (struct clock_event_device
>>> *)dev_id;
>>> -    timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
>>> -    evt->event_handler(evt);
>>> -    return IRQ_HANDLED;
>>> -}
>>> -
>>> -static struct irqaction tegra_timer_irq = {
>>> -    .name        = "timer0",
>>> -    .flags        = IRQF_TIMER | IRQF_TRIGGER_HIGH,
>>> -    .handler    = tegra_timer_interrupt,
>>> -    .dev_id        = &tegra_clockevent,
>>> -};
>>> -
>>> -static int __init tegra20_init_timer(struct device_node *np)
>>> +static int tegra_timer_common_init(struct device_node *np, struct
>>> timer_of *to)
>>>   {
>>> -    struct clk *clk;
>>> -    unsigned long rate;
>>> -    int ret;
>>> -
>>> -    timer_reg_base = of_iomap(np, 0);
>>> -    if (!timer_reg_base) {
>>> -        pr_err("Can't map timer registers\n");
>>> -        return -ENXIO;
>>> -    }
>>> +    int ret = 0;
>>>   -    tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
>>> -    if (tegra_timer_irq.irq <= 0) {
>>> -        pr_err("Failed to map timer IRQ\n");
>>> -        return -EINVAL;
>>> -    }
>>> +    ret = timer_of_init(np, to);
>>> +    if (ret < 0)
>>> +        goto out;
>>>   -    clk = of_clk_get(np, 0);
>>> -    if (IS_ERR(clk)) {
>>> -        pr_warn("Unable to get timer clock. Assuming 12Mhz input
>>> clock.\n");
>>> -        rate = 12000000;
>>> -    } else {
>>> -        clk_prepare_enable(clk);
>>> -        rate = clk_get_rate(clk);
>>> -    }
>>> +    timer_reg_base = timer_of_base(to);
>>>   -    switch (rate) {
>>> +    /*
>>> +     * Configure microsecond timers to have 1MHz clock
>>> +     * Config register is 0xqqww, where qq is "dividend", ww is
>>> "divisor"
>>> +     * Uses n+1 scheme
>>> +     */
>>> +    switch (timer_of_rate(to)) {
>>>       case 12000000:
>>> -        timer_writel(0x000b, TIMERUS_USEC_CFG);
>>> +        usec_config = 0x000b; /* (11+1)/(0+1) */
>>> +        break;
>>> +    case 12800000:
>>> +        usec_config = 0x043f; /* (63+1)/(4+1) */
>>>           break;
>>>       case 13000000:
>>> -        timer_writel(0x000c, TIMERUS_USEC_CFG);
>>> +        usec_config = 0x000c; /* (12+1)/(0+1) */
>>> +        break;
>>> +    case 16800000:
>>> +        usec_config = 0x0453; /* (83+1)/(4+1) */
>>>           break;
>>>       case 19200000:
>>> -        timer_writel(0x045f, TIMERUS_USEC_CFG);
>>> +        usec_config = 0x045f; /* (95+1)/(4+1) */
>>>           break;
>>>       case 26000000:
>>> -        timer_writel(0x0019, TIMERUS_USEC_CFG);
>>> +        usec_config = 0x0019; /* (25+1)/(0+1) */
>>> +        break;
>>> +    case 38400000:
>>> +        usec_config = 0x04bf; /* (191+1)/(4+1) */
>>> +        break;
>>> +    case 48000000:
>>> +        usec_config = 0x002f; /* (47+1)/(0+1) */
>>>           break;
>>>       default:
>>> -        WARN(1, "Unknown clock rate");
>>> +        ret = -EINVAL;
>>> +        goto out;
>>> +    }
>>> +
>>> +    writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG);
>>> +
>>> +out:
>>> +    return ret;
>>> +}
>>> +
>>> +#ifdef CONFIG_ARM64
>>> +static int __init tegra_init_timer(struct device_node *np)
>>> +{
>>> +    int cpu, ret = 0;
>>> +    struct timer_of *to;
>>> +
>>> +    to = this_cpu_ptr(&tegra_to);
>>> +    ret = tegra_timer_common_init(np, to);
>>> +    if (ret < 0)
>>> +        goto out;
>>> +
>>> +    for_each_possible_cpu(cpu) {
>>> +        struct timer_of *cpu_to;
>>> +
>>> +        cpu_to = per_cpu_ptr(&tegra_to, cpu);
>>> +        cpu_to->of_base.base = timer_reg_base +
>>> TIMER_BASE_FOR_CPU(cpu);
>>> +        cpu_to->of_clk.rate = timer_of_rate(to);
>>> +        cpu_to->clkevt.cpumask = cpumask_of(cpu);
>>> +        cpu_to->clkevt.irq =
>>> +            irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu));
>>> +        if (!cpu_to->clkevt.irq) {
>>> +            pr_err("%s: can't map IRQ for CPU%d\n",
>>> +                   __func__, cpu);
>>> +            ret = -EINVAL;
>>> +            goto out;
>>> +        }
>>> +
>>> +        irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
>>> +        ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr,
>>> +                  IRQF_TIMER | IRQF_NOBALANCING,
>>> +                  cpu_to->clkevt.name, &cpu_to->clkevt);
>>> +        if (ret) {
>>> +            pr_err("%s: cannot setup irq %d for CPU%d\n",
>>> +                __func__, cpu_to->clkevt.irq, cpu);
>>> +            ret = -EINVAL;
>>> +            goto out_irq;
>>> +        }
>>> +    }
>>> +
>>> +    cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
>>> +              "AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
>>> +              tegra_timer_stop);
>>> +
>>> +    return ret;
>>> +out_irq:
>>> +    for_each_possible_cpu(cpu) {
>>> +        struct timer_of *cpu_to;
>>> +
>>> +        cpu_to = per_cpu_ptr(&tegra_to, cpu);
>>> +        if (cpu_to->clkevt.irq) {
>>> +            free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
>>> +            irq_dispose_mapping(cpu_to->clkevt.irq);
>>> +        }
>>>       }
>>> +out:
>>> +    timer_of_cleanup(to);
>>> +    return ret;
>>> +}
>>> +#else /* CONFIG_ARM */
>>> +static int __init tegra_init_timer(struct device_node *np)
>>> +{
>>> +    int ret = 0;
>>> +
>>> +    ret = tegra_timer_common_init(np, &tegra_to);
>>> +    if (ret < 0)
>>> +        goto out;
>>>   -    sched_clock_register(tegra_read_sched_clock, 32, 1000000);
>>> +    tegra_to.of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(0);
>>> +    tegra_to.of_clk.rate = 1000000; /* microsecond timer */
>>>   +    sched_clock_register(tegra_read_sched_clock, 32,
>>> +                 timer_of_rate(&tegra_to));
>>>       ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
>>> -                    "timer_us", 1000000, 300, 32,
>>> -                    clocksource_mmio_readl_up);
>>> +                    "timer_us", timer_of_rate(&tegra_to),
>>> +                    300, 32, clocksource_mmio_readl_up);
>>>       if (ret) {
>>>           pr_err("Failed to register clocksource\n");
>>> -        return ret;
>>> +        goto out;
>>>       }
>>>         tegra_delay_timer.read_current_timer =
>>>               tegra_delay_timer_read_counter_long;
>>> -    tegra_delay_timer.freq = 1000000;
>>> +    tegra_delay_timer.freq = timer_of_rate(&tegra_to);
>>>       register_current_timer_delay(&tegra_delay_timer);
>>>   -    ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
>>> -    if (ret) {
>>> -        pr_err("Failed to register timer IRQ: %d\n", ret);
>>> -        return ret;
>>> -    }
>>> +    clockevents_config_and_register(&tegra_to.clkevt,
>>> +                    timer_of_rate(&tegra_to),
>>> +                    0x1,
>>> +                    0x1fffffff);
>>>   -    tegra_clockevent.cpumask = cpu_possible_mask;
>>> -    tegra_clockevent.irq = tegra_timer_irq.irq;
>>> -    clockevents_config_and_register(&tegra_clockevent, 1000000,
>>> -                    0x1, 0x1fffffff);
>>> +    return ret;
>>> +out:
>>> +    timer_of_cleanup(&tegra_to);
>>>   -    return 0;
>>> +    return ret;
>>>   }
>>> -TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer",
>>> tegra20_init_timer);
>>>     static int __init tegra20_init_rtc(struct device_node *np)
>>>   {
>>> @@ -261,3 +406,6 @@ static int __init tegra20_init_rtc(struct
>>> device_node *np)
>>>       return register_persistent_clock(tegra_read_persistent_clock64);
>>>   }
>>>   TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
>>> +#endif
>>> +TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer",
>>> tegra_init_timer);
>>> +TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer",
>>> tegra_init_timer);
>>> diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
>>> index fd586d0301e7..e78281d07b70 100644
>>> --- a/include/linux/cpuhotplug.h
>>> +++ b/include/linux/cpuhotplug.h
>>> @@ -121,6 +121,7 @@ enum cpuhp_state {
>>>       CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING,
>>>       CPUHP_AP_ARM_TWD_STARTING,
>>>       CPUHP_AP_QCOM_TIMER_STARTING,
>>> +    CPUHP_AP_TEGRA_TIMER_STARTING,
>>>       CPUHP_AP_ARMADA_TIMER_STARTING,
>>>       CPUHP_AP_MARCO_TIMER_STARTING,
>>>       CPUHP_AP_MIPS_GIC_TIMER_STARTING,
>>>
>>
>>


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Re: [PATCH V7 2/8] clocksource: tegra: add Tegra210 timer support

[Daniel Lezcano]

On 22/02/2019 10:06, Joseph Lo wrote:
> 
> 
> On 2/22/19 4:43 PM, Daniel Lezcano wrote:
>> On 21/02/2019 08:21, Joseph Lo wrote:
>>> Add support for the Tegra210 timer that runs at oscillator clock
>>> (TMR10-TMR13). We need these timers to work as clock event device and to
>>> replace the ARMv8 architected timer due to it can't survive across the
>>> power cycle of the CPU core or CPUPORESET signal. So it can't be a
>>> wake-up
>>> source when CPU suspends in power down state.
>>>
>>> Also convert the original driver to use timer-of API.
>>>
>>> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
>>> Cc: Thomas Gleixner <tglx@linutronix.de>
>>> Cc: linux-kernel@vger.kernel.org
>>> Signed-off-by: Joseph Lo <josephl@nvidia.com>
>>> Acked-by: Thierry Reding <treding@nvidia.com>
>>> Acked-by: Jon Hunter <jonathanh@nvidia.com>
>>> ---
>>
>> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> 
> Hi Daniel,
> 
> Thanks for your review again. Regarding to Thierry's suggestion in [1],
> could you help to pick up patch 1~3 in this series in clocksource tree?

Ok, as they have the maintainer acked-by tag, I've picked them up for 5.1

Thanks

  -- Daniel


> [1]: https://patchwork.ozlabs.org/patch/1034075/
> 
> If not, I'll let him know this series needs to go with Tegra tree.
> 
>>
>> Will you take care of dropping the persistent clocksource code in this
>> driver?
> 
> Yes, will do.
> 
> Thanks,
> Joseph
> 
>>
>>> v7:
>>>   * kconfig fix for 'depends on ARM || ARM64'
>>>   * move suspend/resume to clkevt
>>>   * refine the usage for the macro of TIMER_OF_DECLARE
>>> v6:
>>>   * refine the timer defines
>>>   * add ack tag from Jon.
>>> v5:
>>>   * add ack tag from Thierry
>>> v4:
>>>   * merge timer-tegra210.c in previous version into timer-tegra20.c
>>> v3:
>>>   * use timer-of API
>>> v2:
>>>   * add error clean-up code
>>> ---
>>>   drivers/clocksource/Kconfig         |   3 +-
>>>   drivers/clocksource/timer-tegra20.c | 370 +++++++++++++++++++---------
>>>   include/linux/cpuhotplug.h          |   1 +
>>>   3 files changed, 262 insertions(+), 112 deletions(-)
>>>
>>> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
>>> index 8dfd3bc448d0..5d93e580e5dc 100644
>>> --- a/drivers/clocksource/Kconfig
>>> +++ b/drivers/clocksource/Kconfig
>>> @@ -131,7 +131,8 @@ config SUN5I_HSTIMER
>>>   config TEGRA_TIMER
>>>       bool "Tegra timer driver" if COMPILE_TEST
>>>       select CLKSRC_MMIO
>>> -    depends on ARM
>>> +    select TIMER_OF
>>> +    depends on ARM || ARM64
>>>       help
>>>         Enables support for the Tegra driver.
>>>   diff --git a/drivers/clocksource/timer-tegra20.c
>>> b/drivers/clocksource/timer-tegra20.c
>>> index 4293943f4e2b..fdb3d795a409 100644
>>> --- a/drivers/clocksource/timer-tegra20.c
>>> +++ b/drivers/clocksource/timer-tegra20.c
>>> @@ -15,21 +15,24 @@
>>>    *
>>>    */
>>>   -#include <linux/init.h>
>>> +#include <linux/clk.h>
>>> +#include <linux/clockchips.h>
>>> +#include <linux/cpu.h>
>>> +#include <linux/cpumask.h>
>>> +#include <linux/delay.h>
>>>   #include <linux/err.h>
>>> -#include <linux/time.h>
>>>   #include <linux/interrupt.h>
>>> -#include <linux/irq.h>
>>> -#include <linux/clockchips.h>
>>> -#include <linux/clocksource.h>
>>> -#include <linux/clk.h>
>>> -#include <linux/io.h>
>>>   #include <linux/of_address.h>
>>>   #include <linux/of_irq.h>
>>> +#include <linux/percpu.h>
>>>   #include <linux/sched_clock.h>
>>> -#include <linux/delay.h>
>>> +#include <linux/time.h>
>>> +
>>> +#include "timer-of.h"
>>>   +#ifdef CONFIG_ARM
>>>   #include <asm/mach/time.h>
>>> +#endif
>>>     #define RTC_SECONDS            0x08
>>>   #define RTC_SHADOW_SECONDS     0x0c
>>> @@ -39,74 +42,161 @@
>>>   #define TIMERUS_USEC_CFG 0x14
>>>   #define TIMERUS_CNTR_FREEZE 0x4c
>>>   -#define TIMER1_BASE 0x0
>>> -#define TIMER2_BASE 0x8
>>> -#define TIMER3_BASE 0x50
>>> -#define TIMER4_BASE 0x58
>>> -
>>> -#define TIMER_PTV 0x0
>>> -#define TIMER_PCR 0x4
>>> -
>>> +#define TIMER_PTV        0x0
>>> +#define TIMER_PTV_EN        BIT(31)
>>> +#define TIMER_PTV_PER        BIT(30)
>>> +#define TIMER_PCR        0x4
>>> +#define TIMER_PCR_INTR_CLR    BIT(30)
>>> +
>>> +#ifdef CONFIG_ARM
>>> +#define TIMER_CPU0        0x50 /* TIMER3 */
>>> +#else
>>> +#define TIMER_CPU0        0x90 /* TIMER10 */
>>> +#define TIMER10_IRQ_IDX        10
>>> +#define IRQ_IDX_FOR_CPU(cpu)    (TIMER10_IRQ_IDX + cpu)
>>> +#endif
>>> +#define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8)
>>> +
>>> +static u32 usec_config;
>>>   static void __iomem *timer_reg_base;
>>> +#ifdef CONFIG_ARM
>>>   static void __iomem *rtc_base;
>>> -
>>>   static struct timespec64 persistent_ts;
>>>   static u64 persistent_ms, last_persistent_ms;
>>> -
>>>   static struct delay_timer tegra_delay_timer;
>>> -
>>> -#define timer_writel(value, reg) \
>>> -    writel_relaxed(value, timer_reg_base + (reg))
>>> -#define timer_readl(reg) \
>>> -    readl_relaxed(timer_reg_base + (reg))
>>> +#endif
>>>     static int tegra_timer_set_next_event(unsigned long cycles,
>>>                        struct clock_event_device *evt)
>>>   {
>>> -    u32 reg;
>>> +    void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>>>   -    reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
>>> -    timer_writel(reg, TIMER3_BASE + TIMER_PTV);
>>> +    writel(TIMER_PTV_EN |
>>> +           ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
>>> +           reg_base + TIMER_PTV);
>>>         return 0;
>>>   }
>>>   -static inline void timer_shutdown(struct clock_event_device *evt)
>>> +static int tegra_timer_shutdown(struct clock_event_device *evt)
>>>   {
>>> -    timer_writel(0, TIMER3_BASE + TIMER_PTV);
>>> +    void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>>> +
>>> +    writel(0, reg_base + TIMER_PTV);
>>> +
>>> +    return 0;
>>>   }
>>>   -static int tegra_timer_shutdown(struct clock_event_device *evt)
>>> +static int tegra_timer_set_periodic(struct clock_event_device *evt)
>>>   {
>>> -    timer_shutdown(evt);
>>> +    void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>>> +
>>> +    writel(TIMER_PTV_EN | TIMER_PTV_PER |
>>> +           ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
>>> +           reg_base + TIMER_PTV);
>>> +
>>>       return 0;
>>>   }
>>>   -static int tegra_timer_set_periodic(struct clock_event_device *evt)
>>> +static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
>>> +{
>>> +    struct clock_event_device *evt = (struct clock_event_device
>>> *)dev_id;
>>> +    void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>>> +
>>> +    writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
>>> +    evt->event_handler(evt);
>>> +
>>> +    return IRQ_HANDLED;
>>> +}
>>> +
>>> +static void tegra_timer_suspend(struct clock_event_device *evt)
>>> +{
>>> +    void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>>> +
>>> +    writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
>>> +}
>>> +
>>> +static void tegra_timer_resume(struct clock_event_device *evt)
>>> +{
>>> +    writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
>>> +}
>>> +
>>> +#ifdef CONFIG_ARM64
>>> +static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
>>> +    .flags = TIMER_OF_CLOCK | TIMER_OF_BASE,
>>> +
>>> +    .clkevt = {
>>> +        .name = "tegra_timer",
>>> +        .rating = 460,
>>> +        .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
>>> +        .set_next_event = tegra_timer_set_next_event,
>>> +        .set_state_shutdown = tegra_timer_shutdown,
>>> +        .set_state_periodic = tegra_timer_set_periodic,
>>> +        .set_state_oneshot = tegra_timer_shutdown,
>>> +        .tick_resume = tegra_timer_shutdown,
>>> +        .suspend = tegra_timer_suspend,
>>> +        .resume = tegra_timer_resume,
>>> +    },
>>> +};
>>> +
>>> +static int tegra_timer_setup(unsigned int cpu)
>>>   {
>>> -    u32 reg = 0xC0000000 | ((1000000 / HZ) - 1);
>>> +    struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
>>> +
>>> +    irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
>>> +    enable_irq(to->clkevt.irq);
>>> +
>>> +    clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
>>> +                    1, /* min */
>>> +                    0x1fffffff); /* 29 bits */
>>>   -    timer_shutdown(evt);
>>> -    timer_writel(reg, TIMER3_BASE + TIMER_PTV);
>>>       return 0;
>>>   }
>>>   -static struct clock_event_device tegra_clockevent = {
>>> -    .name            = "timer0",
>>> -    .rating            = 300,
>>> -    .features        = CLOCK_EVT_FEAT_ONESHOT |
>>> -                  CLOCK_EVT_FEAT_PERIODIC |
>>> -                  CLOCK_EVT_FEAT_DYNIRQ,
>>> -    .set_next_event        = tegra_timer_set_next_event,
>>> -    .set_state_shutdown    = tegra_timer_shutdown,
>>> -    .set_state_periodic    = tegra_timer_set_periodic,
>>> -    .set_state_oneshot    = tegra_timer_shutdown,
>>> -    .tick_resume        = tegra_timer_shutdown,
>>> +static int tegra_timer_stop(unsigned int cpu)
>>> +{
>>> +    struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
>>> +
>>> +    to->clkevt.set_state_shutdown(&to->clkevt);
>>> +    disable_irq_nosync(to->clkevt.irq);
>>> +
>>> +    return 0;
>>> +}
>>> +#else /* CONFIG_ARM */
>>> +static struct timer_of tegra_to = {
>>> +    .flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ,
>>> +
>>> +    .clkevt = {
>>> +        .name = "tegra_timer",
>>> +        .rating    = 300,
>>> +        .features = CLOCK_EVT_FEAT_ONESHOT |
>>> +                CLOCK_EVT_FEAT_PERIODIC |
>>> +                CLOCK_EVT_FEAT_DYNIRQ,
>>> +        .set_next_event    = tegra_timer_set_next_event,
>>> +        .set_state_shutdown = tegra_timer_shutdown,
>>> +        .set_state_periodic = tegra_timer_set_periodic,
>>> +        .set_state_oneshot = tegra_timer_shutdown,
>>> +        .tick_resume = tegra_timer_shutdown,
>>> +        .suspend = tegra_timer_suspend,
>>> +        .resume = tegra_timer_resume,
>>> +        .cpumask = cpu_possible_mask,
>>> +    },
>>> +
>>> +    .of_irq = {
>>> +        .index = 2,
>>> +        .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH,
>>> +        .handler = tegra_timer_isr,
>>> +    },
>>>   };
>>>     static u64 notrace tegra_read_sched_clock(void)
>>>   {
>>> -    return timer_readl(TIMERUS_CNTR_1US);
>>> +    return readl(timer_reg_base + TIMERUS_CNTR_1US);
>>> +}
>>> +
>>> +static unsigned long tegra_delay_timer_read_counter_long(void)
>>> +{
>>> +    return readl(timer_reg_base + TIMERUS_CNTR_1US);
>>>   }
>>>     /*
>>> @@ -143,100 +233,155 @@ static void
>>> tegra_read_persistent_clock64(struct timespec64 *ts)
>>>       timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC);
>>>       *ts = persistent_ts;
>>>   }
>>> +#endif
>>>   -static unsigned long tegra_delay_timer_read_counter_long(void)
>>> -{
>>> -    return readl(timer_reg_base + TIMERUS_CNTR_1US);
>>> -}
>>> -
>>> -static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
>>> -{
>>> -    struct clock_event_device *evt = (struct clock_event_device
>>> *)dev_id;
>>> -    timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
>>> -    evt->event_handler(evt);
>>> -    return IRQ_HANDLED;
>>> -}
>>> -
>>> -static struct irqaction tegra_timer_irq = {
>>> -    .name        = "timer0",
>>> -    .flags        = IRQF_TIMER | IRQF_TRIGGER_HIGH,
>>> -    .handler    = tegra_timer_interrupt,
>>> -    .dev_id        = &tegra_clockevent,
>>> -};
>>> -
>>> -static int __init tegra20_init_timer(struct device_node *np)
>>> +static int tegra_timer_common_init(struct device_node *np, struct
>>> timer_of *to)
>>>   {
>>> -    struct clk *clk;
>>> -    unsigned long rate;
>>> -    int ret;
>>> -
>>> -    timer_reg_base = of_iomap(np, 0);
>>> -    if (!timer_reg_base) {
>>> -        pr_err("Can't map timer registers\n");
>>> -        return -ENXIO;
>>> -    }
>>> +    int ret = 0;
>>>   -    tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
>>> -    if (tegra_timer_irq.irq <= 0) {
>>> -        pr_err("Failed to map timer IRQ\n");
>>> -        return -EINVAL;
>>> -    }
>>> +    ret = timer_of_init(np, to);
>>> +    if (ret < 0)
>>> +        goto out;
>>>   -    clk = of_clk_get(np, 0);
>>> -    if (IS_ERR(clk)) {
>>> -        pr_warn("Unable to get timer clock. Assuming 12Mhz input
>>> clock.\n");
>>> -        rate = 12000000;
>>> -    } else {
>>> -        clk_prepare_enable(clk);
>>> -        rate = clk_get_rate(clk);
>>> -    }
>>> +    timer_reg_base = timer_of_base(to);
>>>   -    switch (rate) {
>>> +    /*
>>> +     * Configure microsecond timers to have 1MHz clock
>>> +     * Config register is 0xqqww, where qq is "dividend", ww is
>>> "divisor"
>>> +     * Uses n+1 scheme
>>> +     */
>>> +    switch (timer_of_rate(to)) {
>>>       case 12000000:
>>> -        timer_writel(0x000b, TIMERUS_USEC_CFG);
>>> +        usec_config = 0x000b; /* (11+1)/(0+1) */
>>> +        break;
>>> +    case 12800000:
>>> +        usec_config = 0x043f; /* (63+1)/(4+1) */
>>>           break;
>>>       case 13000000:
>>> -        timer_writel(0x000c, TIMERUS_USEC_CFG);
>>> +        usec_config = 0x000c; /* (12+1)/(0+1) */
>>> +        break;
>>> +    case 16800000:
>>> +        usec_config = 0x0453; /* (83+1)/(4+1) */
>>>           break;
>>>       case 19200000:
>>> -        timer_writel(0x045f, TIMERUS_USEC_CFG);
>>> +        usec_config = 0x045f; /* (95+1)/(4+1) */
>>>           break;
>>>       case 26000000:
>>> -        timer_writel(0x0019, TIMERUS_USEC_CFG);
>>> +        usec_config = 0x0019; /* (25+1)/(0+1) */
>>> +        break;
>>> +    case 38400000:
>>> +        usec_config = 0x04bf; /* (191+1)/(4+1) */
>>> +        break;
>>> +    case 48000000:
>>> +        usec_config = 0x002f; /* (47+1)/(0+1) */
>>>           break;
>>>       default:
>>> -        WARN(1, "Unknown clock rate");
>>> +        ret = -EINVAL;
>>> +        goto out;
>>> +    }
>>> +
>>> +    writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG);
>>> +
>>> +out:
>>> +    return ret;
>>> +}
>>> +
>>> +#ifdef CONFIG_ARM64
>>> +static int __init tegra_init_timer(struct device_node *np)
>>> +{
>>> +    int cpu, ret = 0;
>>> +    struct timer_of *to;
>>> +
>>> +    to = this_cpu_ptr(&tegra_to);
>>> +    ret = tegra_timer_common_init(np, to);
>>> +    if (ret < 0)
>>> +        goto out;
>>> +
>>> +    for_each_possible_cpu(cpu) {
>>> +        struct timer_of *cpu_to;
>>> +
>>> +        cpu_to = per_cpu_ptr(&tegra_to, cpu);
>>> +        cpu_to->of_base.base = timer_reg_base +
>>> TIMER_BASE_FOR_CPU(cpu);
>>> +        cpu_to->of_clk.rate = timer_of_rate(to);
>>> +        cpu_to->clkevt.cpumask = cpumask_of(cpu);
>>> +        cpu_to->clkevt.irq =
>>> +            irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu));
>>> +        if (!cpu_to->clkevt.irq) {
>>> +            pr_err("%s: can't map IRQ for CPU%d\n",
>>> +                   __func__, cpu);
>>> +            ret = -EINVAL;
>>> +            goto out;
>>> +        }
>>> +
>>> +        irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
>>> +        ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr,
>>> +                  IRQF_TIMER | IRQF_NOBALANCING,
>>> +                  cpu_to->clkevt.name, &cpu_to->clkevt);
>>> +        if (ret) {
>>> +            pr_err("%s: cannot setup irq %d for CPU%d\n",
>>> +                __func__, cpu_to->clkevt.irq, cpu);
>>> +            ret = -EINVAL;
>>> +            goto out_irq;
>>> +        }
>>> +    }
>>> +
>>> +    cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
>>> +              "AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
>>> +              tegra_timer_stop);
>>> +
>>> +    return ret;
>>> +out_irq:
>>> +    for_each_possible_cpu(cpu) {
>>> +        struct timer_of *cpu_to;
>>> +
>>> +        cpu_to = per_cpu_ptr(&tegra_to, cpu);
>>> +        if (cpu_to->clkevt.irq) {
>>> +            free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
>>> +            irq_dispose_mapping(cpu_to->clkevt.irq);
>>> +        }
>>>       }
>>> +out:
>>> +    timer_of_cleanup(to);
>>> +    return ret;
>>> +}
>>> +#else /* CONFIG_ARM */
>>> +static int __init tegra_init_timer(struct device_node *np)
>>> +{
>>> +    int ret = 0;
>>> +
>>> +    ret = tegra_timer_common_init(np, &tegra_to);
>>> +    if (ret < 0)
>>> +        goto out;
>>>   -    sched_clock_register(tegra_read_sched_clock, 32, 1000000);
>>> +    tegra_to.of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(0);
>>> +    tegra_to.of_clk.rate = 1000000; /* microsecond timer */
>>>   +    sched_clock_register(tegra_read_sched_clock, 32,
>>> +                 timer_of_rate(&tegra_to));
>>>       ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
>>> -                    "timer_us", 1000000, 300, 32,
>>> -                    clocksource_mmio_readl_up);
>>> +                    "timer_us", timer_of_rate(&tegra_to),
>>> +                    300, 32, clocksource_mmio_readl_up);
>>>       if (ret) {
>>>           pr_err("Failed to register clocksource\n");
>>> -        return ret;
>>> +        goto out;
>>>       }
>>>         tegra_delay_timer.read_current_timer =
>>>               tegra_delay_timer_read_counter_long;
>>> -    tegra_delay_timer.freq = 1000000;
>>> +    tegra_delay_timer.freq = timer_of_rate(&tegra_to);
>>>       register_current_timer_delay(&tegra_delay_timer);
>>>   -    ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
>>> -    if (ret) {
>>> -        pr_err("Failed to register timer IRQ: %d\n", ret);
>>> -        return ret;
>>> -    }
>>> +    clockevents_config_and_register(&tegra_to.clkevt,
>>> +                    timer_of_rate(&tegra_to),
>>> +                    0x1,
>>> +                    0x1fffffff);
>>>   -    tegra_clockevent.cpumask = cpu_possible_mask;
>>> -    tegra_clockevent.irq = tegra_timer_irq.irq;
>>> -    clockevents_config_and_register(&tegra_clockevent, 1000000,
>>> -                    0x1, 0x1fffffff);
>>> +    return ret;
>>> +out:
>>> +    timer_of_cleanup(&tegra_to);
>>>   -    return 0;
>>> +    return ret;
>>>   }
>>> -TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer",
>>> tegra20_init_timer);
>>>     static int __init tegra20_init_rtc(struct device_node *np)
>>>   {
>>> @@ -261,3 +406,6 @@ static int __init tegra20_init_rtc(struct
>>> device_node *np)
>>>       return register_persistent_clock(tegra_read_persistent_clock64);
>>>   }
>>>   TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
>>> +#endif
>>> +TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer",
>>> tegra_init_timer);
>>> +TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer",
>>> tegra_init_timer);
>>> diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
>>> index fd586d0301e7..e78281d07b70 100644
>>> --- a/include/linux/cpuhotplug.h
>>> +++ b/include/linux/cpuhotplug.h
>>> @@ -121,6 +121,7 @@ enum cpuhp_state {
>>>       CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING,
>>>       CPUHP_AP_ARM_TWD_STARTING,
>>>       CPUHP_AP_QCOM_TIMER_STARTING,
>>> +    CPUHP_AP_TEGRA_TIMER_STARTING,
>>>       CPUHP_AP_ARMADA_TIMER_STARTING,
>>>       CPUHP_AP_MARCO_TIMER_STARTING,
>>>       CPUHP_AP_MIPS_GIC_TIMER_STARTING,
>>>
>>
>>


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[PATCH V7 3/8] soc/tegra: default select TEGRA_TIMER for Tegra210

[Joseph Lo]

The tegra timer is necessary for Tegra210 to support CPU idle power-down
state. So select it by default.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
v7:
 * no change
v6:
 * add ack tag from Jon.
v5:
 * add ack tag from Thierry.
v4:
 * new added in this version
---
 drivers/soc/tegra/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig
index fe4481676da6..a0b03443d8c1 100644
--- a/drivers/soc/tegra/Kconfig
+++ b/drivers/soc/tegra/Kconfig
@@ -76,6 +76,7 @@ config ARCH_TEGRA_210_SOC
 	select PINCTRL_TEGRA210
 	select SOC_TEGRA_FLOWCTRL
 	select SOC_TEGRA_PMC
+	select TEGRA_TIMER
 	help
 	  Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1,
 	  the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
-- 
2.20.1

[PATCH V7 3/8] soc/tegra: default select TEGRA_TIMER for Tegra210

[Joseph Lo]

The tegra timer is necessary for Tegra210 to support CPU idle power-down
state. So select it by default.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
v7:
 * no change
v6:
 * add ack tag from Jon.
v5:
 * add ack tag from Thierry.
v4:
 * new added in this version
---
 drivers/soc/tegra/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig
index fe4481676da6..a0b03443d8c1 100644
--- a/drivers/soc/tegra/Kconfig
+++ b/drivers/soc/tegra/Kconfig
@@ -76,6 +76,7 @@ config ARCH_TEGRA_210_SOC
 	select PINCTRL_TEGRA210
 	select SOC_TEGRA_FLOWCTRL
 	select SOC_TEGRA_PMC
+	select TEGRA_TIMER
 	help
 	  Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1,
 	  the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
-- 
2.20.1


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[PATCH V7 4/8] arm64: tegra: fix timer node for Tegra210

[Joseph Lo]

Fix timer node to make it work with Tegra210 timer driver.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
v7:
 * no change
v6:
 * add ack tag from Jon.
v5:
 * no change
v4:
 * no change
v3:
 * no change
v2:
 * list all the IRQs per each timer channels 0 through 13
 * remove compatible string of "nvidia,tegra30-timer"
---
 arch/arm64/boot/dts/nvidia/tegra210.dtsi | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 6574396d2257..abbb686bd8ba 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -384,14 +384,22 @@
 	};
 
 	timer@60005000 {
-		compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer";
+		compatible = "nvidia,tegra210-timer";
 		reg = <0x0 0x60005000 0x0 0x400>;
-		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+			     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA210_CLK_TIMER>;
 		clock-names = "timer";
 	};
-- 
2.20.1

[PATCH V7 4/8] arm64: tegra: fix timer node for Tegra210

[Joseph Lo]

Fix timer node to make it work with Tegra210 timer driver.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
v7:
 * no change
v6:
 * add ack tag from Jon.
v5:
 * no change
v4:
 * no change
v3:
 * no change
v2:
 * list all the IRQs per each timer channels 0 through 13
 * remove compatible string of "nvidia,tegra30-timer"
---
 arch/arm64/boot/dts/nvidia/tegra210.dtsi | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 6574396d2257..abbb686bd8ba 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -384,14 +384,22 @@
 	};
 
 	timer@60005000 {
-		compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer";
+		compatible = "nvidia,tegra210-timer";
 		reg = <0x0 0x60005000 0x0 0x400>;
-		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+			     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA210_CLK_TIMER>;
 		clock-names = "timer";
 	};
-- 
2.20.1


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[PATCH V7 5/8] arm64: tegra: add CPU idle states properties for Tegra210

[Joseph Lo]

Add idle states properties for generic ARM CPU idle driver. This
includes a cpu-sleep state which is the power down state of CPU cores.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
v7:
 * s/C7/CPU_SLEEP/ & s/c7/cpu-sleep/
 * update the timing of 'entry/exit-latency-us'
v6:
 * add ack tag from Jon.
v5:
 * no change
v4:
 * no change
v3:
 * no change
v2:
 * add entry-latency-us and exit-latency-us properties
---
 arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index abbb686bd8ba..79cedd36ffad 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1371,24 +1371,43 @@
 				 <&dfll>;
 			clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
 			clock-latency = <300000>;
+			cpu-idle-states = <&CPU_SLEEP>;
 		};
 
 		cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a57";
 			reg = <1>;
+			cpu-idle-states = <&CPU_SLEEP>;
 		};
 
 		cpu@2 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a57";
 			reg = <2>;
+			cpu-idle-states = <&CPU_SLEEP>;
 		};
 
 		cpu@3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a57";
 			reg = <3>;
+			cpu-idle-states = <&CPU_SLEEP>;
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			CPU_SLEEP: cpu-sleep {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x40000007>;
+				entry-latency-us = <100>;
+				exit-latency-us = <30>;
+				min-residency-us = <1000>;
+				wakeup-latency-us = <130>;
+				idle-state-name = "cpu-sleep";
+				status = "disabled";
+			};
 		};
 	};
 
-- 
2.20.1

[PATCH V7 5/8] arm64: tegra: add CPU idle states properties for Tegra210

[Joseph Lo]

Add idle states properties for generic ARM CPU idle driver. This
includes a cpu-sleep state which is the power down state of CPU cores.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
v7:
 * s/C7/CPU_SLEEP/ & s/c7/cpu-sleep/
 * update the timing of 'entry/exit-latency-us'
v6:
 * add ack tag from Jon.
v5:
 * no change
v4:
 * no change
v3:
 * no change
v2:
 * add entry-latency-us and exit-latency-us properties
---
 arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index abbb686bd8ba..79cedd36ffad 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1371,24 +1371,43 @@
 				 <&dfll>;
 			clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
 			clock-latency = <300000>;
+			cpu-idle-states = <&CPU_SLEEP>;
 		};
 
 		cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a57";
 			reg = <1>;
+			cpu-idle-states = <&CPU_SLEEP>;
 		};
 
 		cpu@2 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a57";
 			reg = <2>;
+			cpu-idle-states = <&CPU_SLEEP>;
 		};
 
 		cpu@3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a57";
 			reg = <3>;
+			cpu-idle-states = <&CPU_SLEEP>;
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			CPU_SLEEP: cpu-sleep {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x40000007>;
+				entry-latency-us = <100>;
+				exit-latency-us = <30>;
+				min-residency-us = <1000>;
+				wakeup-latency-us = <130>;
+				idle-state-name = "cpu-sleep";
+				status = "disabled";
+			};
 		};
 	};
 
-- 
2.20.1


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Re: [PATCH V7 5/8] arm64: tegra: add CPU idle states properties for Tegra210

[Daniel Lezcano]

On 21/02/2019 08:21, Joseph Lo wrote:
> Add idle states properties for generic ARM CPU idle driver. This
> includes a cpu-sleep state which is the power down state of CPU cores.
> 
> Signed-off-by: Joseph Lo <josephl@nvidia.com>
> Acked-by: Jon Hunter <jonathanh@nvidia.com>

Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>


> ---
> v7:
>  * s/C7/CPU_SLEEP/ & s/c7/cpu-sleep/
>  * update the timing of 'entry/exit-latency-us'
> v6:
>  * add ack tag from Jon.
> v5:
>  * no change
> v4:
>  * no change
> v3:
>  * no change
> v2:
>  * add entry-latency-us and exit-latency-us properties
> ---
>  arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> index abbb686bd8ba..79cedd36ffad 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> @@ -1371,24 +1371,43 @@
>  				 <&dfll>;
>  			clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
>  			clock-latency = <300000>;
> +			cpu-idle-states = <&CPU_SLEEP>;
>  		};
>  
>  		cpu@1 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a57";
>  			reg = <1>;
> +			cpu-idle-states = <&CPU_SLEEP>;
>  		};
>  
>  		cpu@2 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a57";
>  			reg = <2>;
> +			cpu-idle-states = <&CPU_SLEEP>;
>  		};
>  
>  		cpu@3 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a57";
>  			reg = <3>;
> +			cpu-idle-states = <&CPU_SLEEP>;
> +		};
> +
> +		idle-states {
> +			entry-method = "psci";
> +
> +			CPU_SLEEP: cpu-sleep {
> +				compatible = "arm,idle-state";
> +				arm,psci-suspend-param = <0x40000007>;
> +				entry-latency-us = <100>;
> +				exit-latency-us = <30>;
> +				min-residency-us = <1000>;
> +				wakeup-latency-us = <130>;
> +				idle-state-name = "cpu-sleep";
> +				status = "disabled";
> +			};
>  		};
>  	};
>  
> 


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[PATCH V7 6/8] arm64: tegra: Enable CPU idle support for Jetson TX1

[Joseph Lo]

Enable CPU idle support for Jetson TX1 platform.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
v7:
 * s/c7/cpu-sleep/
v6:
 * add ack tag from Jon.
v5:
 * no change
v4:
 * no change
v3:
 * no change
v2:
 * no change
---
 arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
index 053458a5db55..4dcd0d36189a 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
@@ -305,6 +305,12 @@
 		cpu@3 {
 			enable-method = "psci";
 		};
+
+		idle-states {
+			cpu-sleep {
+				status = "okay";
+			};
+		};
 	};
 
 	psci {
-- 
2.20.1

[PATCH V7 6/8] arm64: tegra: Enable CPU idle support for Jetson TX1

[Joseph Lo]

Enable CPU idle support for Jetson TX1 platform.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
v7:
 * s/c7/cpu-sleep/
v6:
 * add ack tag from Jon.
v5:
 * no change
v4:
 * no change
v3:
 * no change
v2:
 * no change
---
 arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
index 053458a5db55..4dcd0d36189a 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
@@ -305,6 +305,12 @@
 		cpu@3 {
 			enable-method = "psci";
 		};
+
+		idle-states {
+			cpu-sleep {
+				status = "okay";
+			};
+		};
 	};
 
 	psci {
-- 
2.20.1


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[PATCH V7 7/8] arm64: tegra: Enable CPU idle support for Smaug

[Joseph Lo]

Enable CPU idle support for Smaug platform.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
v7:
 * s/c7/cpu-sleep/
v6:
 * add ack tag from Jon.
v5:
 * no change
v4:
 * no change
v3:
 * no change
v2:
 * no change
---
 arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
index a4b8f668a6d4..25fd65b5397a 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
@@ -1751,6 +1751,13 @@
 		cpu@3 {
 			enable-method = "psci";
 		};
+
+		idle-states {
+			cpu-sleep {
+				arm,psci-suspend-param = <0x00010007>;
+				status = "okay";
+			};
+		};
 	};
 
 	gpio-keys {
-- 
2.20.1

[PATCH V7 7/8] arm64: tegra: Enable CPU idle support for Smaug

[Joseph Lo]

Enable CPU idle support for Smaug platform.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
v7:
 * s/c7/cpu-sleep/
v6:
 * add ack tag from Jon.
v5:
 * no change
v4:
 * no change
v3:
 * no change
v2:
 * no change
---
 arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
index a4b8f668a6d4..25fd65b5397a 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
@@ -1751,6 +1751,13 @@
 		cpu@3 {
 			enable-method = "psci";
 		};
+
+		idle-states {
+			cpu-sleep {
+				arm,psci-suspend-param = <0x00010007>;
+				status = "okay";
+			};
+		};
 	};
 
 	gpio-keys {
-- 
2.20.1


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[PATCH V7 8/8] arm64: tegra: Enable CPU idle support for Shield

[Joseph Lo]

Enable CPU idle support for Shield platform.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
v7:
 * new added in v7
---
 arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi
index 3ddf173ccc18..88a4b9333d84 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi
@@ -1629,6 +1629,12 @@
 		cpu@3 {
 			enable-method = "psci";
 		};
+
+		idle-states {
+			cpu-sleep {
+				status = "okay";
+			};
+		};
 	};
 
 	psci {
-- 
2.20.1

[PATCH V7 8/8] arm64: tegra: Enable CPU idle support for Shield

[Joseph Lo]

Enable CPU idle support for Shield platform.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
v7:
 * new added in v7
---
 arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi
index 3ddf173ccc18..88a4b9333d84 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi
@@ -1629,6 +1629,12 @@
 		cpu@3 {
 			enable-method = "psci";
 		};
+
+		idle-states {
+			cpu-sleep {
+				status = "okay";
+			};
+		};
 	};
 
 	psci {
-- 
2.20.1


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Re: [PATCH V7 0/8] Add CPUidle support for Tegra210

[Thierry Reding]

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On Thu, Feb 21, 2019 at 03:21:42PM +0800, Joseph Lo wrote:
> This patch series adds CPUidle support for Tegra210, which supports
> cpu-sleep state for CPU cores. And due to arch timer cannot work
> across CPU core power-down and power on reset signal event. We introduce
> Tegra210 timer driver to work as clock event device. So it can be the
> wake-up source of CPU cores when they idled in the power-down state.
> 
> Fix in V7:
>  * kconfig fix for 'depends on ARM || ARM64'
>  * move suspend/resume to clkevt
>  * refine the usage of the macro of TIMER_OF_DECLARE
>  * update the 'entry/exit-latency-us' properties in the idle-states node
>  * add one patch for Shield platform support
> 
> Fix in V6:
>  * refine the timer defines in the timer driver (PATCH 2)
>  * add ack tags from Jon Hunter.
> 
> Fixed in V5:
>  * Just resend this whole series again with timer and Tegra maintainers
>    included
> 
> Fixed in V4:
>  * merge timer-tegra210.c into timer-tegra20.c
>  * add a new patch to select TEGRA_TIMER by default for Tegra210
> 
> Fixed in V3:
>  * use timer-of API for Tegra210 timer driver
> 
> Fixed in V2:
>  * list all the timer IRQs in the binding doc and dts file
>  * add error clean-up code in timer driver
>  * add entry-latency-us and exit-latency-us properties for idle-states
>    DT node
> 
> Joseph Lo (7):
>   dt-bindings: timer: add Tegra210 timer
>   clocksource: tegra: add Tegra210 timer support
>   soc/tegra: default select TEGRA_TIMER for Tegra210
>   arm64: tegra: fix timer node for Tegra210
>   arm64: tegra: add CPU idle states properties for Tegra210
>   arm64: tegra: Enable CPU idle support for Jetson TX1
>   arm64: tegra: Enable CPU idle support for Smaug
>   arm64: tegra: Enable CPU idle support for Shield
> 
>  .../bindings/timer/nvidia,tegra210-timer.txt  |  36 ++
>  .../arm64/boot/dts/nvidia/tegra210-p2180.dtsi |   6 +
>  .../arm64/boot/dts/nvidia/tegra210-p2894.dtsi |   6 +
>  arch/arm64/boot/dts/nvidia/tegra210-smaug.dts |   7 +
>  arch/arm64/boot/dts/nvidia/tegra210.dtsi      |  33 +-
>  drivers/clocksource/Kconfig                   |   3 +-
>  drivers/clocksource/timer-tegra20.c           | 370 ++++++++++++------
>  drivers/soc/tegra/Kconfig                     |   1 +
>  include/linux/cpuhotplug.h                    |   1 +
>  9 files changed, 348 insertions(+), 115 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt

Patches 4-8 applied to for-5.2/arm64/dt, thanks.

Thierry

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