* [PATCH v3 01/15] LICENSES: add BSD-1-Clause license
2019-04-01 10:18 [PATCH v3 00/15] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
@ 2019-04-01 10:18 ` Ahmad Fatoum
2019-04-01 12:20 ` Roland Hieber
2019-04-01 10:18 ` [PATCH v3 02/15] ARM: at91: import at91bootstrap's at91_ddrsdrc.h Ahmad Fatoum
` (14 subsequent siblings)
15 siblings, 1 reply; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-01 10:18 UTC (permalink / raw)
To: barebox; +Cc: sam
Incoming sama5d3 bootstrap code has been ported from the at91bootstrap
project and is licensed under a 1-clause BSD license. To remove
boilerplate legal text there, place the license at a fixed location
and only note SPDX-License-Identifier and Copyright in the source files.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
LICENSES/preferred/BSD-1-Clause | 15 +++++++++++++++
1 file changed, 15 insertions(+)
create mode 100644 LICENSES/preferred/BSD-1-Clause
diff --git a/LICENSES/preferred/BSD-1-Clause b/LICENSES/preferred/BSD-1-Clause
new file mode 100644
index 000000000000..f80acdf3b15f
--- /dev/null
+++ b/LICENSES/preferred/BSD-1-Clause
@@ -0,0 +1,15 @@
+Valid-License-Identifier: BSD-1-Clause
+SPDX-URL: https://spdx.org/licenses/BSD-1-Clause.html
+Usage-Guide:
+ To use the BSD 1-clause License put the following SPDX tag/value pair
+ into a comment according to the placement guidelines in the licensing
+ rules documentation:
+ SPDX-License-Identifier: BSD-1-Clause
+License-Text:
+
+Copyright (c) <year> <owner> All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
+THIS SOFTWARE IS PROVIDED BY Berkeley Software Design, Inc. "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Berkeley Software Design, Inc. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
2.20.1
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^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH v3 01/15] LICENSES: add BSD-1-Clause license
2019-04-01 10:18 ` [PATCH v3 01/15] LICENSES: add BSD-1-Clause license Ahmad Fatoum
@ 2019-04-01 12:20 ` Roland Hieber
2019-04-21 9:03 ` Ahmad Fatoum
0 siblings, 1 reply; 43+ messages in thread
From: Roland Hieber @ 2019-04-01 12:20 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox, sam
On Mon, Apr 01, 2019 at 12:18:09PM +0200, Ahmad Fatoum wrote:
> Incoming sama5d3 bootstrap code has been ported from the at91bootstrap
> project and is licensed under a 1-clause BSD license. To remove
> boilerplate legal text there, place the license at a fixed location
> and only note SPDX-License-Identifier and Copyright in the source files.
>
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> LICENSES/preferred/BSD-1-Clause | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
> create mode 100644 LICENSES/preferred/BSD-1-Clause
>
> diff --git a/LICENSES/preferred/BSD-1-Clause b/LICENSES/preferred/BSD-1-Clause
> new file mode 100644
> index 000000000000..f80acdf3b15f
> --- /dev/null
> +++ b/LICENSES/preferred/BSD-1-Clause
> @@ -0,0 +1,15 @@
> +Valid-License-Identifier: BSD-1-Clause
> +SPDX-URL: https://spdx.org/licenses/BSD-1-Clause.html
> +Usage-Guide:
> + To use the BSD 1-clause License put the following SPDX tag/value pair
> + into a comment according to the placement guidelines in the licensing
> + rules documentation:
> + SPDX-License-Identifier: BSD-1-Clause
> +License-Text:
> +
> +Copyright (c) <year> <owner> All rights reserved.
> +
> +Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
> +
> +1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
> +THIS SOFTWARE IS PROVIDED BY Berkeley Software Design, Inc. "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Berkeley Software Design, Inc. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
I would replace "Berkeley Software Design, Inc." with "the copyright
holder" here. In the link given in the SPDX-URL field these parts are
marked as placeholders in red text, which does not transfer well over to
plain text. :)
I would also hard-line-wrap the text to 80 characters to make it better
readable, but I guess that is a matter of personal preference.
- Roland
--
Roland Hieber | r.hieber@pengutronix.de |
Pengutronix e.K. | https://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim | Phone: +49-5121-206917-5086 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 01/15] LICENSES: add BSD-1-Clause license
2019-04-01 12:20 ` Roland Hieber
@ 2019-04-21 9:03 ` Ahmad Fatoum
0 siblings, 0 replies; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-21 9:03 UTC (permalink / raw)
To: Roland Hieber; +Cc: barebox
On 1/4/19 14:20, Roland Hieber wrote:
> On Mon, Apr 01, 2019 at 12:18:09PM +0200, Ahmad Fatoum wrote:
>> Incoming sama5d3 bootstrap code has been ported from the at91bootstrap
>> project and is licensed under a 1-clause BSD license. To remove
>> boilerplate legal text there, place the license at a fixed location
>> and only note SPDX-License-Identifier and Copyright in the source files.
>>
>> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
>> ---
>> LICENSES/preferred/BSD-1-Clause | 15 +++++++++++++++
>> 1 file changed, 15 insertions(+)
>> create mode 100644 LICENSES/preferred/BSD-1-Clause
>>
>> diff --git a/LICENSES/preferred/BSD-1-Clause b/LICENSES/preferred/BSD-1-Clause
>> new file mode 100644
>> index 000000000000..f80acdf3b15f
>> --- /dev/null
>> +++ b/LICENSES/preferred/BSD-1-Clause
>> @@ -0,0 +1,15 @@
>> +Valid-License-Identifier: BSD-1-Clause
>> +SPDX-URL: https://spdx.org/licenses/BSD-1-Clause.html
>> +Usage-Guide:
>> + To use the BSD 1-clause License put the following SPDX tag/value pair
>> + into a comment according to the placement guidelines in the licensing
>> + rules documentation:
>> + SPDX-License-Identifier: BSD-1-Clause
>> +License-Text:
>> +
>> +Copyright (c) <year> <owner> All rights reserved.
>> +
>> +Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
>> +
>> +1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
>> +THIS SOFTWARE IS PROVIDED BY Berkeley Software Design, Inc. "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Berkeley Software Design, Inc. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>
> I would replace "Berkeley Software Design, Inc." with "the copyright
> holder" here. In the link given in the SPDX-URL field these parts are
> marked as placeholders in red text, which does not transfer well over to
> plain text. :)
Oh forgot to change that. Thanks, will do.
>
> I would also hard-line-wrap the text to 80 characters to make it better
> readable, but I guess that is a matter of personal preference.
>
> - Roland
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 02/15] ARM: at91: import at91bootstrap's at91_ddrsdrc.h
2019-04-01 10:18 [PATCH v3 00/15] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
2019-04-01 10:18 ` [PATCH v3 01/15] LICENSES: add BSD-1-Clause license Ahmad Fatoum
@ 2019-04-01 10:18 ` Ahmad Fatoum
2019-04-01 12:32 ` Roland Hieber
2019-04-01 10:18 ` [PATCH v3 03/15] ARM: at91: migrate at91sam9_ddrsdr.h to use " Ahmad Fatoum
` (13 subsequent siblings)
15 siblings, 1 reply; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-01 10:18 UTC (permalink / raw)
To: barebox; +Cc: sam
Instead of adding missing definitions to the existing at91sam9_ddrsdr.h
and adapting the incoming DDRAM initialization code from at91bootstrap,
just replace the lightly used existing header with:
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/include/arch/at91_ddrsdrc.h
For easier comprehension, the replacement is done in three steps:
Here the header is imported.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
.../arm/mach-at91/include/mach/at91_ddrsdrc.h | 288 ++++++++++++++++++
1 file changed, 288 insertions(+)
create mode 100644 arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
new file mode 100644
index 000000000000..57d0d8f489c4
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: BSD-1-Clause
+/*
+ * Copyright (c) 2006, Atmel Corporation
+ */
+#ifndef __AT91_DDRSDRC_H__
+#define __AT91_DDRSDRC_H__
+
+/**** Register offset in AT91S_HDDRSDRC2 structure ***/
+#define AT91C_HDDRSDRC2_MR 0x00 /* Mode Register */
+#define AT91C_HDDRSDRC2_RTR 0x04 /* Refresh Timer Register */
+#define AT91C_HDDRSDRC2_CR 0x08 /* Configuration Register */
+#define AT91C_HDDRSDRC2_T0PR 0x0C /* Timing Parameter 0 Register */
+#define AT91C_HDDRSDRC2_T1PR 0x10 /* Timing Parameter 1 Register */
+#define AT91C_HDDRSDRC2_T2PR 0x14 /* Timing Parameter 2 Register */
+#define AT91C_HDDRSDRC2_T3PR 0x18 /* Timing Parameter 3 Register */
+#define AT91C_HDDRSDRC2_LPR 0x1C /* Low-power Register */
+#define AT91C_HDDRSDRC2_MDR 0x20 /* Memory Device Register */
+#define AT91C_HDDRSDRC2_DLL 0x24 /* DLL Information Register */
+#define AT91C_HDDRSDRC2_HS 0x2C /* High Speed Register */
+
+/* below items defined for sama5d3x */
+#define AT91C_MPDDRC_LPDDR2_HS 0x24 /* MPDDRC LPDDR2 High Speed Register */
+#define AT91C_MPDDRC_LPDDR2_LPR 0x28 /* MPDDRC LPDDR2 Low-power Register */
+#define AT91C_MPDDRC_LPDDR2_CAL_MR4 0x2C /* MPDDRC LPDDR2 Calibration and MR4 Register */
+#define AT91C_MPDDRC_LPDDR2_TIM_CAL 0x30 /* MPDDRC LPDDR2 Timing Calibration Register */
+#define AT91C_MPDDRC_IO_CALIBR 0x34 /* MPDDRC IO Calibration */
+#define AT91C_MPDDRC_OCMS 0x38 /* MPDDRC OCMS Register */
+#define AT91C_MPDDRC_OCMS_KEY1 0x3C /* MPDDRC OCMS KEY1 Register */
+#define AT91C_MPDDRC_OCMS_KEY2 0x40 /* MPDDRC OCMS KEY2 Register */
+/* 0x54 ~ 0x70 Reserved */
+#define AT91C_MPDDRC_DLL_MOR 0x74 /* MPDDRC DLL Master Offset Register */
+#define AT91C_MPDDRC_DLL_SOR 0x78 /* MPDDRC DLL Slave Offset Register */
+#define AT91C_MPDDRC_DLL_MSR 0x7C /* MPDDRC DLL Master Status Register */
+#define AT91C_MPDDRC_DLL_S0SR 0x80 /* MPDDRC DLL Slave 0 Status Register */
+#define AT91C_MPDDRC_DLL_S1SR 0x84 /* MPDDRC DLL Slave 1 Status Register */
+
+#define AT91C_MPDDRC_RD_DATA_PATH 0x5C /* MPDDRC Read Data Path */
+
+/* 0x94 ~ 0xE0 Reserved */
+#define AT91C_HDDRSDRC2_WPCR 0xE4 /* Write Protect Mode Register */
+#define AT91C_HDDRSDRC2_WPSR 0xE8 /* Write Protect Status Register */
+
+/* -------- HDDRSDRC2_MR : (HDDRSDRC2 Offset: 0x0) Mode Register --------*/
+#define AT91C_DDRC2_MODE (0x7UL << 0)
+#define AT91C_DDRC2_MODE_NORMAL_CMD (0x0UL)
+#define AT91C_DDRC2_MODE_NOP_CMD (0x1UL)
+#define AT91C_DDRC2_MODE_PRCGALL_CMD (0x2UL)
+#define AT91C_DDRC2_MODE_LMR_CMD (0x3UL)
+#define AT91C_DDRC2_MODE_RFSH_CMD (0x4UL)
+#define AT91C_DDRC2_MODE_EXT_LMR_CMD (0x5UL)
+#define AT91C_DDRC2_MODE_DEEP_CMD (0x6UL)
+#define AT91C_DDRC2_MODE_LPDDR2_CMD (0x7UL)
+#define AT91C_DDRC2_MRS(value) (value << 8)
+
+/* -------- HDDRSDRC2_RTR : (HDDRSDRC2 Offset: 0x4) Refresh Timer Register -------- */
+#define AT91C_DDRC2_COUNT (0xFFFUL << 0)
+
+/* -------- HDDRSDRC2_CR : (HDDRSDRC2 Offset: 0x8) Configuration Register --------*/
+#define AT91C_DDRC2_NC (0x3UL << 0)
+#define AT91C_DDRC2_NC_DDR9_SDR8 (0x0UL)
+#define AT91C_DDRC2_NC_DDR10_SDR9 (0x1UL)
+#define AT91C_DDRC2_NC_DDR11_SDR10 (0x2UL)
+#define AT91C_DDRC2_NC_DDR12_SDR11 (0x3UL)
+#define AT91C_DDRC2_NR (0x3UL << 2)
+#define AT91C_DDRC2_NR_11 (0x0UL << 2)
+#define AT91C_DDRC2_NR_12 (0x1UL << 2)
+#define AT91C_DDRC2_NR_13 (0x2UL << 2)
+#define AT91C_DDRC2_NR_14 (0x3UL << 2)
+#define AT91C_DDRC2_CAS (0x7UL << 4)
+#define AT91C_DDRC2_CAS_2 (0x2UL << 4)
+#define AT91C_DDRC2_CAS_3 (0x3UL << 4)
+#define AT91C_DDRC2_CAS_4 (0x4UL << 4)
+#define AT91C_DDRC2_CAS_5 (0x5UL << 4)
+#define AT91C_DDRC2_CAS_6 (0x6UL << 4)
+#define AT91C_DDRC2_RESET_DLL (0x1UL << 7)
+#define AT91C_DDRC2_DISABLE_RESET_DLL (0x0UL << 7)
+#define AT91C_DDRC2_ENABLE_RESET_DLL (0x1UL << 7)
+#define AT91C_DDRC2_DIC_DS (0x1UL << 8)
+#define AT91C_DDRC2_NORMAL_STRENGTH_RZQ6 (0x0UL << 8)
+#define AT91C_DDRC2_WEAK_STRENGTH_RZQ7 (0x1UL << 8)
+#define AT91C_DDRC2_DLL (0x1UL << 9)
+#define AT91C_DDRC2_ENABLE_DLL (0x0UL << 9)
+#define AT91C_DDRC2_DISABLE_DLL (0x1UL << 9)
+#define AT91C_DDRC2_ZQ (0x03 << 10)
+#define AT91C_DDRC2_ZQ_INIT (0x0 << 10)
+#define AT91C_DDRC2_ZQ_LONG (0x1 << 10)
+#define AT91C_DDRC2_ZQ_SHORT (0x2 << 10)
+#define AT91C_DDRC2_ZQ_RESET (0x3 << 10)
+#define AT91C_DDRC2_OCD (0x7UL << 12)
+#define AT91C_DDRC2_OCD_EXIT (0x0UL << 12)
+#define AT91C_DDRC2_OCD_DEFAULT (0x7UL << 12)
+#define AT91C_DDRC2_EBISHARE (0x1UL << 16)
+#define AT91C_DDRC2_DQMS (0x1UL << 16)
+#define AT91C_DDRC2_DQMS_NOT_SHARED (0x0UL << 16)
+#define AT91C_DDRC2_DQMS_SHARED (0x1UL << 16)
+#define AT91C_DDRC2_ENRDM (0x1UL << 17)
+#define AT91C_DDRC2_ENRDM_DISABLE (0x0UL << 17)
+#define AT91C_DDRC2_ENRDM_ENABLE (0x1UL << 17)
+#define AT91C_DDRC2_ACTBST (0x1UL << 18)
+#define AT91C_DDRC2_NB_BANKS (0x1UL << 20)
+#define AT91C_DDRC2_NB_BANKS_4 (0x0UL << 20)
+#define AT91C_DDRC2_NB_BANKS_8 (0x1UL << 20)
+#define AT91C_DDRC2_NDQS (0x1UL << 21) /* Not DQS(sama5d3x only) */
+#define AT91C_DDRC2_NDQS_ENABLED (0x0UL << 21)
+#define AT91C_DDRC2_NDQS_DISABLED (0x1UL << 21)
+#define AT91C_DDRC2_DECOD (0x1UL << 22)
+#define AT91C_DDRC2_DECOD_SEQUENTIAL (0x0UL << 22)
+#define AT91C_DDRC2_DECOD_INTERLEAVED (0x1UL << 22)
+#define AT91C_DDRC2_UNAL (0x1UL << 23) /* Support Unaligned Access(sama5d3x only) */
+#define AT91C_DDRC2_UNAL_UNSUPPORTED (0x0UL << 23)
+#define AT91C_DDRC2_UNAL_SUPPORTED (0x1UL << 23)
+
+/* -------- HDDRSDRC2_T0PR : (HDDRSDRC2 Offset: 0xc) Timing0 Register --------*/
+#define AT91C_DDRC2_TRAS (0xFUL << 0)
+#define AT91C_DDRC2_TRAS_(x) (x & 0x0f)
+#define AT91C_DDRC2_TRCD (0xFUL << 4)
+#define AT91C_DDRC2_TRCD_(x) ((x & 0x0f) << 4)
+#define AT91C_DDRC2_TWR (0xFUL << 8)
+#define AT91C_DDRC2_TWR_(x) ((x & 0x0f) << 8)
+#define AT91C_DDRC2_TRC (0xFUL << 12)
+#define AT91C_DDRC2_TRC_(x) ((x & 0x0f) << 12)
+#define AT91C_DDRC2_TRP (0xFUL << 16)
+#define AT91C_DDRC2_TRP_(x) ((x & 0x0f) << 16)
+#define AT91C_DDRC2_TRRD (0xFUL << 20)
+#define AT91C_DDRC2_TRRD_(x) ((x & 0x0f) << 20)
+#define AT91C_DDRC2_TWTR (0xFUL << 24)
+#define AT91C_DDRC2_TWTR_(x) ((x & 0x0f) << 24)
+#define AT91C_DDRC2_TMRD (0xFUL << 28)
+#define AT91C_DDRC2_TMRD_(x) ((x & 0x0f) << 28)
+
+/* -------- HDDRSDRC2_T1PR : (HDDRSDRC2 Offset: 0x10) Timing1 Register -------- */
+#define AT91C_DDRC2_TRFC (0x7FUL << 0)
+#define AT91C_DDRC2_TRFC_(x) (x & 0x7f)
+#define AT91C_DDRC2_TXSNR (0xFFUL << 8)
+#define AT91C_DDRC2_TXSNR_(x) ((x & 0xff) << 8)
+#define AT91C_DDRC2_TXSRD (0xFFUL << 16)
+#define AT91C_DDRC2_TXSRD_(x) ((x & 0xff) << 16)
+#define AT91C_DDRC2_TXP (0xFUL << 24)
+#define AT91C_DDRC2_TXP_(x) ((x & 0x0f) << 24)
+
+/* -------- HDDRSDRC2_T2PR : (HDDRSDRC2 Offset: 0x14) Timing2 Register --------*/
+#define AT91C_DDRC2_TXARD (0xFUL << 0)
+#define AT91C_DDRC2_TXARD_(x) (x & 0x0f)
+#define AT91C_DDRC2_TXARDS (0xFUL << 4)
+#define AT91C_DDRC2_TXARDS_(x) ((x & 0x0f) << 4)
+#define AT91C_DDRC2_TRPA (0xFUL << 8)
+#define AT91C_DDRC2_TRPA_(x) ((x & 0x0f) << 8)
+#define AT91C_DDRC2_TRT (0xFUL << 12)
+#define AT91C_DDRC2_TRTP_(x) ((x & 0x0f) << 12)
+#define AT91C_DDRC2_TFA (0xFUL << 16)
+#define AT91C_DDRC2_TFAW_(x) ((x & 0x0f) << 16)
+
+/* -------- HDDRSDRC2_LPR : (HDDRSDRC2 Offset: 0x1c) --------*/
+#define AT91C_DDRC2_LPCB (0x3UL << 0)
+#define AT91C_DDRC2_LPCB_DISABLED (0x0UL)
+#define AT91C_DDRC2_LPCB_SELFREFRESH (0x1UL)
+#define AT91C_DDRC2_LPCB_POWERDOWN (0x2UL)
+#define AT91C_DDRC2_LPCB_DEEP_PWD (0x3UL)
+#define AT91C_DDRC2_CLK_FR (0x1UL << 2)
+#define AT91C_DDRC2_PASR (0x7UL << 4)
+#define AT91C_DDRC2_PASR_(x) ((x & 0x7) << 4)
+#define AT91C_DDRC2_DS (0x7UL << 8)
+#define AT91C_DDRC2_DS_(x) ((x & 0x7) << 8)
+#define AT91C_DDRC2_TIMEOUT (0x3UL << 12)
+#define AT91C_DDRC2_TIMEOUT_0 (0x0UL << 12)
+#define AT91C_DDRC2_TIMEOUT_64 (0x1UL << 12)
+#define AT91C_DDRC2_TIMEOUT_128 (0x2UL << 12)
+#define AT91C_DDRC2_TIMEOUT_Reserved (0x3UL << 12)
+#define AT91C_DDRC2_ADPE (0x1UL << 16)
+#define AT91C_DDRC2_ADPE_FAST (0x0UL << 16)
+#define AT91C_DDRC2_ADPE_SLOW (0x1UL << 16)
+#define AT91C_DDRC2_UPD_MR (0x3UL << 20)
+#define AT91C_DDRC2_UPD_MR_NO_UPDATE (0x0UL << 20)
+#define AT91C_DDRC2_UPD_MR_SHARED_BUS (0x1UL << 20)
+#define AT91C_DDRC2_UPD_MR_NO_SHARED_BUS (0x2UL << 20)
+#define AT91C_DDRC2_SELF_DONE (0x1UL << 25)
+
+/* -------- HDDRSDRC2_MDR : (HDDRSDRC2 Offset: 0x20) Memory Device Register -------- */
+#define AT91C_DDRC2_MD (0x7UL << 0)
+#define AT91C_DDRC2_MD_SDR_SDRAM (0x0UL)
+#define AT91C_DDRC2_MD_LP_SDR_SDRAM (0x1UL)
+#define AT91C_DDRC2_MD_DDR_SDRAM (0x2UL)
+#define AT91C_DDRC2_MD_LP_DDR_SDRAM (0x3UL)
+#define AT91C_DDRC2_MD_DDR3_SDRAM (0x4UL)
+#define AT91C_DDRC2_MD_LPDDR3_SDRAM (0x5UL)
+#define AT91C_DDRC2_MD_DDR2_SDRAM (0x6UL)
+#define AT91C_DDRC2_MD_LPDDR2_SDRAM (0x7UL)
+#define AT91C_DDRC2_DBW (0x1UL << 4)
+#define AT91C_DDRC2_DBW_32_BITS (0x0UL << 4)
+#define AT91C_DDRC2_DBW_16_BITS (0x1UL << 4)
+
+/* -------- HDDRSDRC2_DLL : (HDDRSDRC2 Offset: 0x24) DLL Information Register --------*/
+#define AT91C_DDRC2_MDINC (0x1UL << 0)
+#define AT91C_DDRC2_MDDEC (0x1UL << 1)
+#define AT91C_DDRC2_MDOVF (0x1UL << 2)
+#define AT91C_DDRC2_MDVAL (0xFFUL << 8)
+
+/* ------- MPDDRC_LPDDR2_LPR (offset: 0x28) */
+#define AT91C_LPDDRC2_BK_MASK_PASR(value) (value << 0)
+#define AT91C_LPDDRC2_SEG_MASK(value) (value << 8)
+#define AT91C_LPDDRC2_DS(value) (value << 24)
+
+/* -------- HDDRSDRC2_HS : (HDDRSDRC2 Offset: 0x2c) High Speed Register --------*/
+#define AT91C_DDRC2_NO_ANT (0x1UL << 2)
+
+/* -------- MPDDRC_LPDDR2_CAL_MR4: (MPDDRC Offset: 0x2c) Calibration and MR4 Register --------*/
+#define AT91C_DDRC2_COUNT_CAL_MASK (0xFFFFUL)
+#define AT91C_DDRC2_COUNT_CAL(value) (((value) & AT91C_DDRC2_COUNT_CAL_MASK) << 0)
+
+/* -------- MPDDRC_LPDDR2_TIM_CAL : (MPDDRC Offset: 0x30) */
+#define AT91C_DDRC2_ZQCS(value) (value << 0)
+
+/* -------- MPDDRC_IO_CALIBR : (MPDDRC Offset: 0x34) IO Calibration --------*/
+#define AT91C_MPDDRC_RDIV (0x7UL << 0)
+#define AT91C_MPDDRC_RDIV_LPDDR2_RZQ_34 (0x1UL << 0)
+#define AT91C_MPDDRC_RDIV_LPDDR2_RZQ_48 (0x3UL << 0)
+#define AT91C_MPDDRC_RDIV_LPDDR2_RZQ_60 (0x4UL << 0)
+#define AT91C_MPDDRC_RDIV_LPDDR2_RZQ_120 (0x7UL << 0)
+
+#define AT91C_MPDDRC_RDIV_DDR2_RZQ_33_3 (0x2UL << 0)
+#define AT91C_MPDDRC_RDIV_DDR2_RZQ_50 (0x4UL << 0)
+#define AT91C_MPDDRC_RDIV_DDR2_RZQ_66_7 (0x6UL << 0)
+#define AT91C_MPDDRC_RDIV_DDR2_RZQ_100 (0x7UL << 0)
+
+#define AT91C_MPDDRC_RDIV_LPDDR3_RZQ_38 (0x02UL << 0)
+#define AT91C_MPDDRC_RDIV_LPDDR3_RZQ_46 (0x03UL << 0)
+#define AT91C_MPDDRC_RDIV_LPDDR3_RZQ_57 (0x04UL << 0)
+#define AT91C_MPDDRC_RDIV_LPDDR3_RZQ_77 (0x06UL << 0)
+#define AT91C_MPDDRC_RDIV_LPDDR3_RZQ_115 (0x07UL << 0)
+
+#define AT91C_MPDDRC_ENABLE_CALIB (0x01 << 4)
+#define AT91C_MPDDRC_DISABLE_CALIB (0x00 << 4)
+#define AT91C_MPDDRC_EN_CALIB (0x01 << 4)
+
+#define AT91C_MPDDRC_TZQIO (0x7FUL << 8)
+#define AT91C_MPDDRC_TZQIO_(x) ((x) << 8)
+#define AT91C_MPDDRC_TZQIO_0 (0x0UL << 8)
+#define AT91C_MPDDRC_TZQIO_1 (0x1UL << 8)
+#define AT91C_MPDDRC_TZQIO_3 (0x3UL << 8)
+#define AT91C_MPDDRC_TZQIO_4 (0x4UL << 8)
+#define AT91C_MPDDRC_TZQIO_5 (0x5UL << 8)
+#define AT91C_MPDDRC_TZQIO_31 (0x1FUL << 8)
+
+#define AT91C_MPDDRC_CALCODEP (0xFUL << 16)
+#define AT91C_MPDDRC_CALCODEP_(x) ((x) << 16)
+
+#define AT91C_MPDDRC_CALCODEN (0xFUL << 20)
+#define AT91C_MPDDRC_CALCODEN_(x) ((x) << 20)
+
+/* ---- MPDDRC_RD_DATA_PATH : (MPDDRC Offset: 0x5c) MPDDRC Read Data Path */
+#define AT91_MPDDRC_SHIFT_SAMPLING (0x03 << 0)
+#define AT91C_MPDDRC_RD_DATA_PATH_NO_SHIFT (0x00 << 0)
+#define AT91C_MPDDRC_RD_DATA_PATH_ONE_CYCLES (0x01 << 0)
+#define AT91C_MPDDRC_RD_DATA_PATH_TWO_CYCLES (0x02 << 0)
+#define AT91C_MPDDRC_RD_DATA_PATH_THREE_CYCLES (0x03 << 0)
+
+/* -------- MPDDRC_DLL_MOR : (MPDDRC Offset: 0x74) DLL Master Offset Register --------*/
+#define AT91C_MPDDRC_MOFF(value) (value << 0)
+#define AT91C_MPDDRC_MOFF_1 (0x1UL << 0)
+#define AT91C_MPDDRC_MOFF_7 (0x7UL << 0)
+#define AT91C_MPDDRC_CLK90OFF(value) (value << 8)
+#define AT91C_MPDDRC_CLK90OFF_1 (0x1UL << 8)
+#define AT91C_MPDDRC_CLK90OFF_31 (0x1FUL << 8)
+#define AT91C_MPDDRC_SELOFF (0x1UL << 16)
+#define AT91C_MPDDRC_SELOFF_DISABLED (0x0UL << 16)
+#define AT91C_MPDDRC_SELOFF_ENABLED (0x1UL << 16)
+#define AT91C_MPDDRC_KEY (0xC5UL << 24)
+
+/* -------- MPDDRC_DLL_SOR : (MPDDRC Offset: 0x78) DLL Slave Offset Register --------*/
+#define AT91C_MPDDRC_S0OFF_1 (0x1UL << 0)
+#define AT91C_MPDDRC_S1OFF_1 (0x1UL << 8)
+#define AT91C_MPDDRC_S2OFF_1 (0x1UL << 16)
+#define AT91C_MPDDRC_S3OFF_1 (0x1UL << 24)
+
+#define AT91C_MPDDRC_S0OFF(value) (value << 0)
+#define AT91C_MPDDRC_S1OFF(value) (value << 8)
+#define AT91C_MPDDRC_S2OFF(value) (value << 16)
+#define AT91C_MPDDRC_S3OFF(value) (value << 24)
+
+/* -------- HDDRSDRC2_WPCR : (HDDRSDRC2 Offset: 0xe4) Write Protect Control Register --------*/
+#define AT91C_DDRC2_WPEN (0x1UL << 0)
+#define AT91C_DDRC2_WPKEY (0xFFFFFFUL << 8)
+
+/* -------- HDDRSDRC2_WPSR : (HDDRSDRC2 Offset: 0xe8) Write Protect Status Register --------*/
+#define AT91C_DDRC2_WPVS (0x1UL << 0)
+#define AT91C_DDRC2_WPSRC (0xFFFFUL << 8)
+
+#endif /* __AT91_DDRSDRC_H__ */
--
2.20.1
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^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH v3 02/15] ARM: at91: import at91bootstrap's at91_ddrsdrc.h
2019-04-01 10:18 ` [PATCH v3 02/15] ARM: at91: import at91bootstrap's at91_ddrsdrc.h Ahmad Fatoum
@ 2019-04-01 12:32 ` Roland Hieber
2019-04-01 13:36 ` Ahmad Fatoum
0 siblings, 1 reply; 43+ messages in thread
From: Roland Hieber @ 2019-04-01 12:32 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox, sam
On Mon, Apr 01, 2019 at 12:18:10PM +0200, Ahmad Fatoum wrote:
> Instead of adding missing definitions to the existing at91sam9_ddrsdr.h
> and adapting the incoming DDRAM initialization code from at91bootstrap,
> just replace the lightly used existing header with:
> https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/include/arch/at91_ddrsdrc.h
>
> For easier comprehension, the replacement is done in three steps:
> Here the header is imported.
>
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> .../arm/mach-at91/include/mach/at91_ddrsdrc.h | 288 ++++++++++++++++++
> 1 file changed, 288 insertions(+)
> create mode 100644 arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
>
> diff --git a/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
> new file mode 100644
> index 000000000000..57d0d8f489c4
> --- /dev/null
> +++ b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
> @@ -0,0 +1,288 @@
> +// SPDX-License-Identifier: BSD-1-Clause
I've told you this in our personal converation before, but I'll happily
repeat it here for a broader audience: The original GitHub source says
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED.
which additionally disclaims warranty for "NON-INFRINGEMENT", which is
not in BSD-1-Clause text you added in the previous commit. I regard this
as a substantive change of the licensing conditions according to the
SPDX License List Matching Guidelines [s] and rather use the original
license headers here as long as there is no SPDX license identifier for
it.
Same probably also applies to the other source files.
[s]: https://spdx.org/spdx-license-list/matching-guidelines
- Roland
> +/*
> + * Copyright (c) 2006, Atmel Corporation
> + */
> +#ifndef __AT91_DDRSDRC_H__
> +#define __AT91_DDRSDRC_H__
> +
> +/**** Register offset in AT91S_HDDRSDRC2 structure ***/
> +#define AT91C_HDDRSDRC2_MR 0x00 /* Mode Register */
> +#define AT91C_HDDRSDRC2_RTR 0x04 /* Refresh Timer Register */
> +#define AT91C_HDDRSDRC2_CR 0x08 /* Configuration Register */
> +#define AT91C_HDDRSDRC2_T0PR 0x0C /* Timing Parameter 0 Register */
> +#define AT91C_HDDRSDRC2_T1PR 0x10 /* Timing Parameter 1 Register */
> +#define AT91C_HDDRSDRC2_T2PR 0x14 /* Timing Parameter 2 Register */
> +#define AT91C_HDDRSDRC2_T3PR 0x18 /* Timing Parameter 3 Register */
> +#define AT91C_HDDRSDRC2_LPR 0x1C /* Low-power Register */
> +#define AT91C_HDDRSDRC2_MDR 0x20 /* Memory Device Register */
> +#define AT91C_HDDRSDRC2_DLL 0x24 /* DLL Information Register */
> +#define AT91C_HDDRSDRC2_HS 0x2C /* High Speed Register */
> +
> +/* below items defined for sama5d3x */
> +#define AT91C_MPDDRC_LPDDR2_HS 0x24 /* MPDDRC LPDDR2 High Speed Register */
> +#define AT91C_MPDDRC_LPDDR2_LPR 0x28 /* MPDDRC LPDDR2 Low-power Register */
> +#define AT91C_MPDDRC_LPDDR2_CAL_MR4 0x2C /* MPDDRC LPDDR2 Calibration and MR4 Register */
> +#define AT91C_MPDDRC_LPDDR2_TIM_CAL 0x30 /* MPDDRC LPDDR2 Timing Calibration Register */
> +#define AT91C_MPDDRC_IO_CALIBR 0x34 /* MPDDRC IO Calibration */
> +#define AT91C_MPDDRC_OCMS 0x38 /* MPDDRC OCMS Register */
> +#define AT91C_MPDDRC_OCMS_KEY1 0x3C /* MPDDRC OCMS KEY1 Register */
> +#define AT91C_MPDDRC_OCMS_KEY2 0x40 /* MPDDRC OCMS KEY2 Register */
> +/* 0x54 ~ 0x70 Reserved */
> +#define AT91C_MPDDRC_DLL_MOR 0x74 /* MPDDRC DLL Master Offset Register */
> +#define AT91C_MPDDRC_DLL_SOR 0x78 /* MPDDRC DLL Slave Offset Register */
> +#define AT91C_MPDDRC_DLL_MSR 0x7C /* MPDDRC DLL Master Status Register */
> +#define AT91C_MPDDRC_DLL_S0SR 0x80 /* MPDDRC DLL Slave 0 Status Register */
> +#define AT91C_MPDDRC_DLL_S1SR 0x84 /* MPDDRC DLL Slave 1 Status Register */
> +
> +#define AT91C_MPDDRC_RD_DATA_PATH 0x5C /* MPDDRC Read Data Path */
> +
> +/* 0x94 ~ 0xE0 Reserved */
> +#define AT91C_HDDRSDRC2_WPCR 0xE4 /* Write Protect Mode Register */
> +#define AT91C_HDDRSDRC2_WPSR 0xE8 /* Write Protect Status Register */
> +
> +/* -------- HDDRSDRC2_MR : (HDDRSDRC2 Offset: 0x0) Mode Register --------*/
> +#define AT91C_DDRC2_MODE (0x7UL << 0)
> +#define AT91C_DDRC2_MODE_NORMAL_CMD (0x0UL)
> +#define AT91C_DDRC2_MODE_NOP_CMD (0x1UL)
> +#define AT91C_DDRC2_MODE_PRCGALL_CMD (0x2UL)
> +#define AT91C_DDRC2_MODE_LMR_CMD (0x3UL)
> +#define AT91C_DDRC2_MODE_RFSH_CMD (0x4UL)
> +#define AT91C_DDRC2_MODE_EXT_LMR_CMD (0x5UL)
> +#define AT91C_DDRC2_MODE_DEEP_CMD (0x6UL)
> +#define AT91C_DDRC2_MODE_LPDDR2_CMD (0x7UL)
> +#define AT91C_DDRC2_MRS(value) (value << 8)
> +
> +/* -------- HDDRSDRC2_RTR : (HDDRSDRC2 Offset: 0x4) Refresh Timer Register -------- */
> +#define AT91C_DDRC2_COUNT (0xFFFUL << 0)
> +
> +/* -------- HDDRSDRC2_CR : (HDDRSDRC2 Offset: 0x8) Configuration Register --------*/
> +#define AT91C_DDRC2_NC (0x3UL << 0)
> +#define AT91C_DDRC2_NC_DDR9_SDR8 (0x0UL)
> +#define AT91C_DDRC2_NC_DDR10_SDR9 (0x1UL)
> +#define AT91C_DDRC2_NC_DDR11_SDR10 (0x2UL)
> +#define AT91C_DDRC2_NC_DDR12_SDR11 (0x3UL)
> +#define AT91C_DDRC2_NR (0x3UL << 2)
> +#define AT91C_DDRC2_NR_11 (0x0UL << 2)
> +#define AT91C_DDRC2_NR_12 (0x1UL << 2)
> +#define AT91C_DDRC2_NR_13 (0x2UL << 2)
> +#define AT91C_DDRC2_NR_14 (0x3UL << 2)
> +#define AT91C_DDRC2_CAS (0x7UL << 4)
> +#define AT91C_DDRC2_CAS_2 (0x2UL << 4)
> +#define AT91C_DDRC2_CAS_3 (0x3UL << 4)
> +#define AT91C_DDRC2_CAS_4 (0x4UL << 4)
> +#define AT91C_DDRC2_CAS_5 (0x5UL << 4)
> +#define AT91C_DDRC2_CAS_6 (0x6UL << 4)
> +#define AT91C_DDRC2_RESET_DLL (0x1UL << 7)
> +#define AT91C_DDRC2_DISABLE_RESET_DLL (0x0UL << 7)
> +#define AT91C_DDRC2_ENABLE_RESET_DLL (0x1UL << 7)
> +#define AT91C_DDRC2_DIC_DS (0x1UL << 8)
> +#define AT91C_DDRC2_NORMAL_STRENGTH_RZQ6 (0x0UL << 8)
> +#define AT91C_DDRC2_WEAK_STRENGTH_RZQ7 (0x1UL << 8)
> +#define AT91C_DDRC2_DLL (0x1UL << 9)
> +#define AT91C_DDRC2_ENABLE_DLL (0x0UL << 9)
> +#define AT91C_DDRC2_DISABLE_DLL (0x1UL << 9)
> +#define AT91C_DDRC2_ZQ (0x03 << 10)
> +#define AT91C_DDRC2_ZQ_INIT (0x0 << 10)
> +#define AT91C_DDRC2_ZQ_LONG (0x1 << 10)
> +#define AT91C_DDRC2_ZQ_SHORT (0x2 << 10)
> +#define AT91C_DDRC2_ZQ_RESET (0x3 << 10)
> +#define AT91C_DDRC2_OCD (0x7UL << 12)
> +#define AT91C_DDRC2_OCD_EXIT (0x0UL << 12)
> +#define AT91C_DDRC2_OCD_DEFAULT (0x7UL << 12)
> +#define AT91C_DDRC2_EBISHARE (0x1UL << 16)
> +#define AT91C_DDRC2_DQMS (0x1UL << 16)
> +#define AT91C_DDRC2_DQMS_NOT_SHARED (0x0UL << 16)
> +#define AT91C_DDRC2_DQMS_SHARED (0x1UL << 16)
> +#define AT91C_DDRC2_ENRDM (0x1UL << 17)
> +#define AT91C_DDRC2_ENRDM_DISABLE (0x0UL << 17)
> +#define AT91C_DDRC2_ENRDM_ENABLE (0x1UL << 17)
> +#define AT91C_DDRC2_ACTBST (0x1UL << 18)
> +#define AT91C_DDRC2_NB_BANKS (0x1UL << 20)
> +#define AT91C_DDRC2_NB_BANKS_4 (0x0UL << 20)
> +#define AT91C_DDRC2_NB_BANKS_8 (0x1UL << 20)
> +#define AT91C_DDRC2_NDQS (0x1UL << 21) /* Not DQS(sama5d3x only) */
> +#define AT91C_DDRC2_NDQS_ENABLED (0x0UL << 21)
> +#define AT91C_DDRC2_NDQS_DISABLED (0x1UL << 21)
> +#define AT91C_DDRC2_DECOD (0x1UL << 22)
> +#define AT91C_DDRC2_DECOD_SEQUENTIAL (0x0UL << 22)
> +#define AT91C_DDRC2_DECOD_INTERLEAVED (0x1UL << 22)
> +#define AT91C_DDRC2_UNAL (0x1UL << 23) /* Support Unaligned Access(sama5d3x only) */
> +#define AT91C_DDRC2_UNAL_UNSUPPORTED (0x0UL << 23)
> +#define AT91C_DDRC2_UNAL_SUPPORTED (0x1UL << 23)
> +
> +/* -------- HDDRSDRC2_T0PR : (HDDRSDRC2 Offset: 0xc) Timing0 Register --------*/
> +#define AT91C_DDRC2_TRAS (0xFUL << 0)
> +#define AT91C_DDRC2_TRAS_(x) (x & 0x0f)
> +#define AT91C_DDRC2_TRCD (0xFUL << 4)
> +#define AT91C_DDRC2_TRCD_(x) ((x & 0x0f) << 4)
> +#define AT91C_DDRC2_TWR (0xFUL << 8)
> +#define AT91C_DDRC2_TWR_(x) ((x & 0x0f) << 8)
> +#define AT91C_DDRC2_TRC (0xFUL << 12)
> +#define AT91C_DDRC2_TRC_(x) ((x & 0x0f) << 12)
> +#define AT91C_DDRC2_TRP (0xFUL << 16)
> +#define AT91C_DDRC2_TRP_(x) ((x & 0x0f) << 16)
> +#define AT91C_DDRC2_TRRD (0xFUL << 20)
> +#define AT91C_DDRC2_TRRD_(x) ((x & 0x0f) << 20)
> +#define AT91C_DDRC2_TWTR (0xFUL << 24)
> +#define AT91C_DDRC2_TWTR_(x) ((x & 0x0f) << 24)
> +#define AT91C_DDRC2_TMRD (0xFUL << 28)
> +#define AT91C_DDRC2_TMRD_(x) ((x & 0x0f) << 28)
> +
> +/* -------- HDDRSDRC2_T1PR : (HDDRSDRC2 Offset: 0x10) Timing1 Register -------- */
> +#define AT91C_DDRC2_TRFC (0x7FUL << 0)
> +#define AT91C_DDRC2_TRFC_(x) (x & 0x7f)
> +#define AT91C_DDRC2_TXSNR (0xFFUL << 8)
> +#define AT91C_DDRC2_TXSNR_(x) ((x & 0xff) << 8)
> +#define AT91C_DDRC2_TXSRD (0xFFUL << 16)
> +#define AT91C_DDRC2_TXSRD_(x) ((x & 0xff) << 16)
> +#define AT91C_DDRC2_TXP (0xFUL << 24)
> +#define AT91C_DDRC2_TXP_(x) ((x & 0x0f) << 24)
> +
> +/* -------- HDDRSDRC2_T2PR : (HDDRSDRC2 Offset: 0x14) Timing2 Register --------*/
> +#define AT91C_DDRC2_TXARD (0xFUL << 0)
> +#define AT91C_DDRC2_TXARD_(x) (x & 0x0f)
> +#define AT91C_DDRC2_TXARDS (0xFUL << 4)
> +#define AT91C_DDRC2_TXARDS_(x) ((x & 0x0f) << 4)
> +#define AT91C_DDRC2_TRPA (0xFUL << 8)
> +#define AT91C_DDRC2_TRPA_(x) ((x & 0x0f) << 8)
> +#define AT91C_DDRC2_TRT (0xFUL << 12)
> +#define AT91C_DDRC2_TRTP_(x) ((x & 0x0f) << 12)
> +#define AT91C_DDRC2_TFA (0xFUL << 16)
> +#define AT91C_DDRC2_TFAW_(x) ((x & 0x0f) << 16)
> +
> +/* -------- HDDRSDRC2_LPR : (HDDRSDRC2 Offset: 0x1c) --------*/
> +#define AT91C_DDRC2_LPCB (0x3UL << 0)
> +#define AT91C_DDRC2_LPCB_DISABLED (0x0UL)
> +#define AT91C_DDRC2_LPCB_SELFREFRESH (0x1UL)
> +#define AT91C_DDRC2_LPCB_POWERDOWN (0x2UL)
> +#define AT91C_DDRC2_LPCB_DEEP_PWD (0x3UL)
> +#define AT91C_DDRC2_CLK_FR (0x1UL << 2)
> +#define AT91C_DDRC2_PASR (0x7UL << 4)
> +#define AT91C_DDRC2_PASR_(x) ((x & 0x7) << 4)
> +#define AT91C_DDRC2_DS (0x7UL << 8)
> +#define AT91C_DDRC2_DS_(x) ((x & 0x7) << 8)
> +#define AT91C_DDRC2_TIMEOUT (0x3UL << 12)
> +#define AT91C_DDRC2_TIMEOUT_0 (0x0UL << 12)
> +#define AT91C_DDRC2_TIMEOUT_64 (0x1UL << 12)
> +#define AT91C_DDRC2_TIMEOUT_128 (0x2UL << 12)
> +#define AT91C_DDRC2_TIMEOUT_Reserved (0x3UL << 12)
> +#define AT91C_DDRC2_ADPE (0x1UL << 16)
> +#define AT91C_DDRC2_ADPE_FAST (0x0UL << 16)
> +#define AT91C_DDRC2_ADPE_SLOW (0x1UL << 16)
> +#define AT91C_DDRC2_UPD_MR (0x3UL << 20)
> +#define AT91C_DDRC2_UPD_MR_NO_UPDATE (0x0UL << 20)
> +#define AT91C_DDRC2_UPD_MR_SHARED_BUS (0x1UL << 20)
> +#define AT91C_DDRC2_UPD_MR_NO_SHARED_BUS (0x2UL << 20)
> +#define AT91C_DDRC2_SELF_DONE (0x1UL << 25)
> +
> +/* -------- HDDRSDRC2_MDR : (HDDRSDRC2 Offset: 0x20) Memory Device Register -------- */
> +#define AT91C_DDRC2_MD (0x7UL << 0)
> +#define AT91C_DDRC2_MD_SDR_SDRAM (0x0UL)
> +#define AT91C_DDRC2_MD_LP_SDR_SDRAM (0x1UL)
> +#define AT91C_DDRC2_MD_DDR_SDRAM (0x2UL)
> +#define AT91C_DDRC2_MD_LP_DDR_SDRAM (0x3UL)
> +#define AT91C_DDRC2_MD_DDR3_SDRAM (0x4UL)
> +#define AT91C_DDRC2_MD_LPDDR3_SDRAM (0x5UL)
> +#define AT91C_DDRC2_MD_DDR2_SDRAM (0x6UL)
> +#define AT91C_DDRC2_MD_LPDDR2_SDRAM (0x7UL)
> +#define AT91C_DDRC2_DBW (0x1UL << 4)
> +#define AT91C_DDRC2_DBW_32_BITS (0x0UL << 4)
> +#define AT91C_DDRC2_DBW_16_BITS (0x1UL << 4)
> +
> +/* -------- HDDRSDRC2_DLL : (HDDRSDRC2 Offset: 0x24) DLL Information Register --------*/
> +#define AT91C_DDRC2_MDINC (0x1UL << 0)
> +#define AT91C_DDRC2_MDDEC (0x1UL << 1)
> +#define AT91C_DDRC2_MDOVF (0x1UL << 2)
> +#define AT91C_DDRC2_MDVAL (0xFFUL << 8)
> +
> +/* ------- MPDDRC_LPDDR2_LPR (offset: 0x28) */
> +#define AT91C_LPDDRC2_BK_MASK_PASR(value) (value << 0)
> +#define AT91C_LPDDRC2_SEG_MASK(value) (value << 8)
> +#define AT91C_LPDDRC2_DS(value) (value << 24)
> +
> +/* -------- HDDRSDRC2_HS : (HDDRSDRC2 Offset: 0x2c) High Speed Register --------*/
> +#define AT91C_DDRC2_NO_ANT (0x1UL << 2)
> +
> +/* -------- MPDDRC_LPDDR2_CAL_MR4: (MPDDRC Offset: 0x2c) Calibration and MR4 Register --------*/
> +#define AT91C_DDRC2_COUNT_CAL_MASK (0xFFFFUL)
> +#define AT91C_DDRC2_COUNT_CAL(value) (((value) & AT91C_DDRC2_COUNT_CAL_MASK) << 0)
> +
> +/* -------- MPDDRC_LPDDR2_TIM_CAL : (MPDDRC Offset: 0x30) */
> +#define AT91C_DDRC2_ZQCS(value) (value << 0)
> +
> +/* -------- MPDDRC_IO_CALIBR : (MPDDRC Offset: 0x34) IO Calibration --------*/
> +#define AT91C_MPDDRC_RDIV (0x7UL << 0)
> +#define AT91C_MPDDRC_RDIV_LPDDR2_RZQ_34 (0x1UL << 0)
> +#define AT91C_MPDDRC_RDIV_LPDDR2_RZQ_48 (0x3UL << 0)
> +#define AT91C_MPDDRC_RDIV_LPDDR2_RZQ_60 (0x4UL << 0)
> +#define AT91C_MPDDRC_RDIV_LPDDR2_RZQ_120 (0x7UL << 0)
> +
> +#define AT91C_MPDDRC_RDIV_DDR2_RZQ_33_3 (0x2UL << 0)
> +#define AT91C_MPDDRC_RDIV_DDR2_RZQ_50 (0x4UL << 0)
> +#define AT91C_MPDDRC_RDIV_DDR2_RZQ_66_7 (0x6UL << 0)
> +#define AT91C_MPDDRC_RDIV_DDR2_RZQ_100 (0x7UL << 0)
> +
> +#define AT91C_MPDDRC_RDIV_LPDDR3_RZQ_38 (0x02UL << 0)
> +#define AT91C_MPDDRC_RDIV_LPDDR3_RZQ_46 (0x03UL << 0)
> +#define AT91C_MPDDRC_RDIV_LPDDR3_RZQ_57 (0x04UL << 0)
> +#define AT91C_MPDDRC_RDIV_LPDDR3_RZQ_77 (0x06UL << 0)
> +#define AT91C_MPDDRC_RDIV_LPDDR3_RZQ_115 (0x07UL << 0)
> +
> +#define AT91C_MPDDRC_ENABLE_CALIB (0x01 << 4)
> +#define AT91C_MPDDRC_DISABLE_CALIB (0x00 << 4)
> +#define AT91C_MPDDRC_EN_CALIB (0x01 << 4)
> +
> +#define AT91C_MPDDRC_TZQIO (0x7FUL << 8)
> +#define AT91C_MPDDRC_TZQIO_(x) ((x) << 8)
> +#define AT91C_MPDDRC_TZQIO_0 (0x0UL << 8)
> +#define AT91C_MPDDRC_TZQIO_1 (0x1UL << 8)
> +#define AT91C_MPDDRC_TZQIO_3 (0x3UL << 8)
> +#define AT91C_MPDDRC_TZQIO_4 (0x4UL << 8)
> +#define AT91C_MPDDRC_TZQIO_5 (0x5UL << 8)
> +#define AT91C_MPDDRC_TZQIO_31 (0x1FUL << 8)
> +
> +#define AT91C_MPDDRC_CALCODEP (0xFUL << 16)
> +#define AT91C_MPDDRC_CALCODEP_(x) ((x) << 16)
> +
> +#define AT91C_MPDDRC_CALCODEN (0xFUL << 20)
> +#define AT91C_MPDDRC_CALCODEN_(x) ((x) << 20)
> +
> +/* ---- MPDDRC_RD_DATA_PATH : (MPDDRC Offset: 0x5c) MPDDRC Read Data Path */
> +#define AT91_MPDDRC_SHIFT_SAMPLING (0x03 << 0)
> +#define AT91C_MPDDRC_RD_DATA_PATH_NO_SHIFT (0x00 << 0)
> +#define AT91C_MPDDRC_RD_DATA_PATH_ONE_CYCLES (0x01 << 0)
> +#define AT91C_MPDDRC_RD_DATA_PATH_TWO_CYCLES (0x02 << 0)
> +#define AT91C_MPDDRC_RD_DATA_PATH_THREE_CYCLES (0x03 << 0)
> +
> +/* -------- MPDDRC_DLL_MOR : (MPDDRC Offset: 0x74) DLL Master Offset Register --------*/
> +#define AT91C_MPDDRC_MOFF(value) (value << 0)
> +#define AT91C_MPDDRC_MOFF_1 (0x1UL << 0)
> +#define AT91C_MPDDRC_MOFF_7 (0x7UL << 0)
> +#define AT91C_MPDDRC_CLK90OFF(value) (value << 8)
> +#define AT91C_MPDDRC_CLK90OFF_1 (0x1UL << 8)
> +#define AT91C_MPDDRC_CLK90OFF_31 (0x1FUL << 8)
> +#define AT91C_MPDDRC_SELOFF (0x1UL << 16)
> +#define AT91C_MPDDRC_SELOFF_DISABLED (0x0UL << 16)
> +#define AT91C_MPDDRC_SELOFF_ENABLED (0x1UL << 16)
> +#define AT91C_MPDDRC_KEY (0xC5UL << 24)
> +
> +/* -------- MPDDRC_DLL_SOR : (MPDDRC Offset: 0x78) DLL Slave Offset Register --------*/
> +#define AT91C_MPDDRC_S0OFF_1 (0x1UL << 0)
> +#define AT91C_MPDDRC_S1OFF_1 (0x1UL << 8)
> +#define AT91C_MPDDRC_S2OFF_1 (0x1UL << 16)
> +#define AT91C_MPDDRC_S3OFF_1 (0x1UL << 24)
> +
> +#define AT91C_MPDDRC_S0OFF(value) (value << 0)
> +#define AT91C_MPDDRC_S1OFF(value) (value << 8)
> +#define AT91C_MPDDRC_S2OFF(value) (value << 16)
> +#define AT91C_MPDDRC_S3OFF(value) (value << 24)
> +
> +/* -------- HDDRSDRC2_WPCR : (HDDRSDRC2 Offset: 0xe4) Write Protect Control Register --------*/
> +#define AT91C_DDRC2_WPEN (0x1UL << 0)
> +#define AT91C_DDRC2_WPKEY (0xFFFFFFUL << 8)
> +
> +/* -------- HDDRSDRC2_WPSR : (HDDRSDRC2 Offset: 0xe8) Write Protect Status Register --------*/
> +#define AT91C_DDRC2_WPVS (0x1UL << 0)
> +#define AT91C_DDRC2_WPSRC (0xFFFFUL << 8)
> +
> +#endif /* __AT91_DDRSDRC_H__ */
> --
> 2.20.1
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
--
Roland Hieber | r.hieber@pengutronix.de |
Pengutronix e.K. | https://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim | Phone: +49-5121-206917-5086 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH v3 02/15] ARM: at91: import at91bootstrap's at91_ddrsdrc.h
2019-04-01 12:32 ` Roland Hieber
@ 2019-04-01 13:36 ` Ahmad Fatoum
2019-04-01 14:23 ` Roland Hieber
0 siblings, 1 reply; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-01 13:36 UTC (permalink / raw)
To: Roland Hieber; +Cc: barebox, sam
Hello Roland,
On 4/1/19 2:32 PM, Roland Hieber wrote:
> On Mon, Apr 01, 2019 at 12:18:10PM +0200, Ahmad Fatoum wrote:
>> Instead of adding missing definitions to the existing at91sam9_ddrsdr.h
>> and adapting the incoming DDRAM initialization code from at91bootstrap,
>> just replace the lightly used existing header with:
>> https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/include/arch/at91_ddrsdrc.h
>>
>> For easier comprehension, the replacement is done in three steps:
>> Here the header is imported.
>>
>> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
>> ---
>> .../arm/mach-at91/include/mach/at91_ddrsdrc.h | 288 ++++++++++++++++++
>> 1 file changed, 288 insertions(+)
>> create mode 100644 arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
>>
>> diff --git a/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
>> new file mode 100644
>> index 000000000000..57d0d8f489c4
>> --- /dev/null
>> +++ b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
>> @@ -0,0 +1,288 @@
>> +// SPDX-License-Identifier: BSD-1-Clause
>
> I've told you this in our personal converation before, but I'll happily
> repeat it here for a broader audience: The original GitHub source says
>
> * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
> * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
> * DISCLAIMED.
>
> which additionally disclaims warranty for "NON-INFRINGEMENT", which is
> not in BSD-1-Clause text you added in the previous commit. I regard this
> as a substantive change of the licensing conditions according to the
> SPDX License List Matching Guidelines [s] and rather use the original
> license headers here as long as there is no SPDX license identifier for
> it.
To restate my opinion:
Atmel already disclaims ANY EXPRESS or IMPLIED WARRANTIES, which should
include NON-INFRINGEMENT regardless if whether it was explicitly listed
or not.
At least one person agrees with me:
http://lists.opensource.org/pipermail/license-discuss_lists.opensource.org/2006-August/011643.html
>
> Same probably also applies to the other source files.
>
> [s]: https://spdx.org/spdx-license-list/matching-guidelines
>
> - Roland
>
>> +/*
>> + * Copyright (c) 2006, Atmel Corporation
>> + */
>> +#ifndef __AT91_DDRSDRC_H__
>> +#define __AT91_DDRSDRC_H__
>> +
>> +/**** Register offset in AT91S_HDDRSDRC2 structure ***/
>> +#define AT91C_HDDRSDRC2_MR 0x00 /* Mode Register */
>> +#define AT91C_HDDRSDRC2_RTR 0x04 /* Refresh Timer Register */
>> +#define AT91C_HDDRSDRC2_CR 0x08 /* Configuration Register */
>> +#define AT91C_HDDRSDRC2_T0PR 0x0C /* Timing Parameter 0 Register */
>> +#define AT91C_HDDRSDRC2_T1PR 0x10 /* Timing Parameter 1 Register */
>> +#define AT91C_HDDRSDRC2_T2PR 0x14 /* Timing Parameter 2 Register */
>> +#define AT91C_HDDRSDRC2_T3PR 0x18 /* Timing Parameter 3 Register */
>> +#define AT91C_HDDRSDRC2_LPR 0x1C /* Low-power Register */
>> +#define AT91C_HDDRSDRC2_MDR 0x20 /* Memory Device Register */
>> +#define AT91C_HDDRSDRC2_DLL 0x24 /* DLL Information Register */
>> +#define AT91C_HDDRSDRC2_HS 0x2C /* High Speed Register */
>> +
>> +/* below items defined for sama5d3x */
>> +#define AT91C_MPDDRC_LPDDR2_HS 0x24 /* MPDDRC LPDDR2 High Speed Register */
>> +#define AT91C_MPDDRC_LPDDR2_LPR 0x28 /* MPDDRC LPDDR2 Low-power Register */
>> +#define AT91C_MPDDRC_LPDDR2_CAL_MR4 0x2C /* MPDDRC LPDDR2 Calibration and MR4 Register */
>> +#define AT91C_MPDDRC_LPDDR2_TIM_CAL 0x30 /* MPDDRC LPDDR2 Timing Calibration Register */
>> +#define AT91C_MPDDRC_IO_CALIBR 0x34 /* MPDDRC IO Calibration */
>> +#define AT91C_MPDDRC_OCMS 0x38 /* MPDDRC OCMS Register */
>> +#define AT91C_MPDDRC_OCMS_KEY1 0x3C /* MPDDRC OCMS KEY1 Register */
>> +#define AT91C_MPDDRC_OCMS_KEY2 0x40 /* MPDDRC OCMS KEY2 Register */
>> +/* 0x54 ~ 0x70 Reserved */
>> +#define AT91C_MPDDRC_DLL_MOR 0x74 /* MPDDRC DLL Master Offset Register */
>> +#define AT91C_MPDDRC_DLL_SOR 0x78 /* MPDDRC DLL Slave Offset Register */
>> +#define AT91C_MPDDRC_DLL_MSR 0x7C /* MPDDRC DLL Master Status Register */
>> +#define AT91C_MPDDRC_DLL_S0SR 0x80 /* MPDDRC DLL Slave 0 Status Register */
>> +#define AT91C_MPDDRC_DLL_S1SR 0x84 /* MPDDRC DLL Slave 1 Status Register */
>> +
>> +#define AT91C_MPDDRC_RD_DATA_PATH 0x5C /* MPDDRC Read Data Path */
>> +
>> +/* 0x94 ~ 0xE0 Reserved */
>> +#define AT91C_HDDRSDRC2_WPCR 0xE4 /* Write Protect Mode Register */
>> +#define AT91C_HDDRSDRC2_WPSR 0xE8 /* Write Protect Status Register */
>> +
>> +/* -------- HDDRSDRC2_MR : (HDDRSDRC2 Offset: 0x0) Mode Register --------*/
>> +#define AT91C_DDRC2_MODE (0x7UL << 0)
>> +#define AT91C_DDRC2_MODE_NORMAL_CMD (0x0UL)
>> +#define AT91C_DDRC2_MODE_NOP_CMD (0x1UL)
>> +#define AT91C_DDRC2_MODE_PRCGALL_CMD (0x2UL)
>> +#define AT91C_DDRC2_MODE_LMR_CMD (0x3UL)
>> +#define AT91C_DDRC2_MODE_RFSH_CMD (0x4UL)
>> +#define AT91C_DDRC2_MODE_EXT_LMR_CMD (0x5UL)
>> +#define AT91C_DDRC2_MODE_DEEP_CMD (0x6UL)
>> +#define AT91C_DDRC2_MODE_LPDDR2_CMD (0x7UL)
>> +#define AT91C_DDRC2_MRS(value) (value << 8)
>> +
>> +/* -------- HDDRSDRC2_RTR : (HDDRSDRC2 Offset: 0x4) Refresh Timer Register -------- */
>> +#define AT91C_DDRC2_COUNT (0xFFFUL << 0)
>> +
>> +/* -------- HDDRSDRC2_CR : (HDDRSDRC2 Offset: 0x8) Configuration Register --------*/
>> +#define AT91C_DDRC2_NC (0x3UL << 0)
>> +#define AT91C_DDRC2_NC_DDR9_SDR8 (0x0UL)
>> +#define AT91C_DDRC2_NC_DDR10_SDR9 (0x1UL)
>> +#define AT91C_DDRC2_NC_DDR11_SDR10 (0x2UL)
>> +#define AT91C_DDRC2_NC_DDR12_SDR11 (0x3UL)
>> +#define AT91C_DDRC2_NR (0x3UL << 2)
>> +#define AT91C_DDRC2_NR_11 (0x0UL << 2)
>> +#define AT91C_DDRC2_NR_12 (0x1UL << 2)
>> +#define AT91C_DDRC2_NR_13 (0x2UL << 2)
>> +#define AT91C_DDRC2_NR_14 (0x3UL << 2)
>> +#define AT91C_DDRC2_CAS (0x7UL << 4)
>> +#define AT91C_DDRC2_CAS_2 (0x2UL << 4)
>> +#define AT91C_DDRC2_CAS_3 (0x3UL << 4)
>> +#define AT91C_DDRC2_CAS_4 (0x4UL << 4)
>> +#define AT91C_DDRC2_CAS_5 (0x5UL << 4)
>> +#define AT91C_DDRC2_CAS_6 (0x6UL << 4)
>> +#define AT91C_DDRC2_RESET_DLL (0x1UL << 7)
>> +#define AT91C_DDRC2_DISABLE_RESET_DLL (0x0UL << 7)
>> +#define AT91C_DDRC2_ENABLE_RESET_DLL (0x1UL << 7)
>> +#define AT91C_DDRC2_DIC_DS (0x1UL << 8)
>> +#define AT91C_DDRC2_NORMAL_STRENGTH_RZQ6 (0x0UL << 8)
>> +#define AT91C_DDRC2_WEAK_STRENGTH_RZQ7 (0x1UL << 8)
>> +#define AT91C_DDRC2_DLL (0x1UL << 9)
>> +#define AT91C_DDRC2_ENABLE_DLL (0x0UL << 9)
>> +#define AT91C_DDRC2_DISABLE_DLL (0x1UL << 9)
>> +#define AT91C_DDRC2_ZQ (0x03 << 10)
>> +#define AT91C_DDRC2_ZQ_INIT (0x0 << 10)
>> +#define AT91C_DDRC2_ZQ_LONG (0x1 << 10)
>> +#define AT91C_DDRC2_ZQ_SHORT (0x2 << 10)
>> +#define AT91C_DDRC2_ZQ_RESET (0x3 << 10)
>> +#define AT91C_DDRC2_OCD (0x7UL << 12)
>> +#define AT91C_DDRC2_OCD_EXIT (0x0UL << 12)
>> +#define AT91C_DDRC2_OCD_DEFAULT (0x7UL << 12)
>> +#define AT91C_DDRC2_EBISHARE (0x1UL << 16)
>> +#define AT91C_DDRC2_DQMS (0x1UL << 16)
>> +#define AT91C_DDRC2_DQMS_NOT_SHARED (0x0UL << 16)
>> +#define AT91C_DDRC2_DQMS_SHARED (0x1UL << 16)
>> +#define AT91C_DDRC2_ENRDM (0x1UL << 17)
>> +#define AT91C_DDRC2_ENRDM_DISABLE (0x0UL << 17)
>> +#define AT91C_DDRC2_ENRDM_ENABLE (0x1UL << 17)
>> +#define AT91C_DDRC2_ACTBST (0x1UL << 18)
>> +#define AT91C_DDRC2_NB_BANKS (0x1UL << 20)
>> +#define AT91C_DDRC2_NB_BANKS_4 (0x0UL << 20)
>> +#define AT91C_DDRC2_NB_BANKS_8 (0x1UL << 20)
>> +#define AT91C_DDRC2_NDQS (0x1UL << 21) /* Not DQS(sama5d3x only) */
>> +#define AT91C_DDRC2_NDQS_ENABLED (0x0UL << 21)
>> +#define AT91C_DDRC2_NDQS_DISABLED (0x1UL << 21)
>> +#define AT91C_DDRC2_DECOD (0x1UL << 22)
>> +#define AT91C_DDRC2_DECOD_SEQUENTIAL (0x0UL << 22)
>> +#define AT91C_DDRC2_DECOD_INTERLEAVED (0x1UL << 22)
>> +#define AT91C_DDRC2_UNAL (0x1UL << 23) /* Support Unaligned Access(sama5d3x only) */
>> +#define AT91C_DDRC2_UNAL_UNSUPPORTED (0x0UL << 23)
>> +#define AT91C_DDRC2_UNAL_SUPPORTED (0x1UL << 23)
>> +
>> +/* -------- HDDRSDRC2_T0PR : (HDDRSDRC2 Offset: 0xc) Timing0 Register --------*/
>> +#define AT91C_DDRC2_TRAS (0xFUL << 0)
>> +#define AT91C_DDRC2_TRAS_(x) (x & 0x0f)
>> +#define AT91C_DDRC2_TRCD (0xFUL << 4)
>> +#define AT91C_DDRC2_TRCD_(x) ((x & 0x0f) << 4)
>> +#define AT91C_DDRC2_TWR (0xFUL << 8)
>> +#define AT91C_DDRC2_TWR_(x) ((x & 0x0f) << 8)
>> +#define AT91C_DDRC2_TRC (0xFUL << 12)
>> +#define AT91C_DDRC2_TRC_(x) ((x & 0x0f) << 12)
>> +#define AT91C_DDRC2_TRP (0xFUL << 16)
>> +#define AT91C_DDRC2_TRP_(x) ((x & 0x0f) << 16)
>> +#define AT91C_DDRC2_TRRD (0xFUL << 20)
>> +#define AT91C_DDRC2_TRRD_(x) ((x & 0x0f) << 20)
>> +#define AT91C_DDRC2_TWTR (0xFUL << 24)
>> +#define AT91C_DDRC2_TWTR_(x) ((x & 0x0f) << 24)
>> +#define AT91C_DDRC2_TMRD (0xFUL << 28)
>> +#define AT91C_DDRC2_TMRD_(x) ((x & 0x0f) << 28)
>> +
>> +/* -------- HDDRSDRC2_T1PR : (HDDRSDRC2 Offset: 0x10) Timing1 Register -------- */
>> +#define AT91C_DDRC2_TRFC (0x7FUL << 0)
>> +#define AT91C_DDRC2_TRFC_(x) (x & 0x7f)
>> +#define AT91C_DDRC2_TXSNR (0xFFUL << 8)
>> +#define AT91C_DDRC2_TXSNR_(x) ((x & 0xff) << 8)
>> +#define AT91C_DDRC2_TXSRD (0xFFUL << 16)
>> +#define AT91C_DDRC2_TXSRD_(x) ((x & 0xff) << 16)
>> +#define AT91C_DDRC2_TXP (0xFUL << 24)
>> +#define AT91C_DDRC2_TXP_(x) ((x & 0x0f) << 24)
>> +
>> +/* -------- HDDRSDRC2_T2PR : (HDDRSDRC2 Offset: 0x14) Timing2 Register --------*/
>> +#define AT91C_DDRC2_TXARD (0xFUL << 0)
>> +#define AT91C_DDRC2_TXARD_(x) (x & 0x0f)
>> +#define AT91C_DDRC2_TXARDS (0xFUL << 4)
>> +#define AT91C_DDRC2_TXARDS_(x) ((x & 0x0f) << 4)
>> +#define AT91C_DDRC2_TRPA (0xFUL << 8)
>> +#define AT91C_DDRC2_TRPA_(x) ((x & 0x0f) << 8)
>> +#define AT91C_DDRC2_TRT (0xFUL << 12)
>> +#define AT91C_DDRC2_TRTP_(x) ((x & 0x0f) << 12)
>> +#define AT91C_DDRC2_TFA (0xFUL << 16)
>> +#define AT91C_DDRC2_TFAW_(x) ((x & 0x0f) << 16)
>> +
>> +/* -------- HDDRSDRC2_LPR : (HDDRSDRC2 Offset: 0x1c) --------*/
>> +#define AT91C_DDRC2_LPCB (0x3UL << 0)
>> +#define AT91C_DDRC2_LPCB_DISABLED (0x0UL)
>> +#define AT91C_DDRC2_LPCB_SELFREFRESH (0x1UL)
>> +#define AT91C_DDRC2_LPCB_POWERDOWN (0x2UL)
>> +#define AT91C_DDRC2_LPCB_DEEP_PWD (0x3UL)
>> +#define AT91C_DDRC2_CLK_FR (0x1UL << 2)
>> +#define AT91C_DDRC2_PASR (0x7UL << 4)
>> +#define AT91C_DDRC2_PASR_(x) ((x & 0x7) << 4)
>> +#define AT91C_DDRC2_DS (0x7UL << 8)
>> +#define AT91C_DDRC2_DS_(x) ((x & 0x7) << 8)
>> +#define AT91C_DDRC2_TIMEOUT (0x3UL << 12)
>> +#define AT91C_DDRC2_TIMEOUT_0 (0x0UL << 12)
>> +#define AT91C_DDRC2_TIMEOUT_64 (0x1UL << 12)
>> +#define AT91C_DDRC2_TIMEOUT_128 (0x2UL << 12)
>> +#define AT91C_DDRC2_TIMEOUT_Reserved (0x3UL << 12)
>> +#define AT91C_DDRC2_ADPE (0x1UL << 16)
>> +#define AT91C_DDRC2_ADPE_FAST (0x0UL << 16)
>> +#define AT91C_DDRC2_ADPE_SLOW (0x1UL << 16)
>> +#define AT91C_DDRC2_UPD_MR (0x3UL << 20)
>> +#define AT91C_DDRC2_UPD_MR_NO_UPDATE (0x0UL << 20)
>> +#define AT91C_DDRC2_UPD_MR_SHARED_BUS (0x1UL << 20)
>> +#define AT91C_DDRC2_UPD_MR_NO_SHARED_BUS (0x2UL << 20)
>> +#define AT91C_DDRC2_SELF_DONE (0x1UL << 25)
>> +
>> +/* -------- HDDRSDRC2_MDR : (HDDRSDRC2 Offset: 0x20) Memory Device Register -------- */
>> +#define AT91C_DDRC2_MD (0x7UL << 0)
>> +#define AT91C_DDRC2_MD_SDR_SDRAM (0x0UL)
>> +#define AT91C_DDRC2_MD_LP_SDR_SDRAM (0x1UL)
>> +#define AT91C_DDRC2_MD_DDR_SDRAM (0x2UL)
>> +#define AT91C_DDRC2_MD_LP_DDR_SDRAM (0x3UL)
>> +#define AT91C_DDRC2_MD_DDR3_SDRAM (0x4UL)
>> +#define AT91C_DDRC2_MD_LPDDR3_SDRAM (0x5UL)
>> +#define AT91C_DDRC2_MD_DDR2_SDRAM (0x6UL)
>> +#define AT91C_DDRC2_MD_LPDDR2_SDRAM (0x7UL)
>> +#define AT91C_DDRC2_DBW (0x1UL << 4)
>> +#define AT91C_DDRC2_DBW_32_BITS (0x0UL << 4)
>> +#define AT91C_DDRC2_DBW_16_BITS (0x1UL << 4)
>> +
>> +/* -------- HDDRSDRC2_DLL : (HDDRSDRC2 Offset: 0x24) DLL Information Register --------*/
>> +#define AT91C_DDRC2_MDINC (0x1UL << 0)
>> +#define AT91C_DDRC2_MDDEC (0x1UL << 1)
>> +#define AT91C_DDRC2_MDOVF (0x1UL << 2)
>> +#define AT91C_DDRC2_MDVAL (0xFFUL << 8)
>> +
>> +/* ------- MPDDRC_LPDDR2_LPR (offset: 0x28) */
>> +#define AT91C_LPDDRC2_BK_MASK_PASR(value) (value << 0)
>> +#define AT91C_LPDDRC2_SEG_MASK(value) (value << 8)
>> +#define AT91C_LPDDRC2_DS(value) (value << 24)
>> +
>> +/* -------- HDDRSDRC2_HS : (HDDRSDRC2 Offset: 0x2c) High Speed Register --------*/
>> +#define AT91C_DDRC2_NO_ANT (0x1UL << 2)
>> +
>> +/* -------- MPDDRC_LPDDR2_CAL_MR4: (MPDDRC Offset: 0x2c) Calibration and MR4 Register --------*/
>> +#define AT91C_DDRC2_COUNT_CAL_MASK (0xFFFFUL)
>> +#define AT91C_DDRC2_COUNT_CAL(value) (((value) & AT91C_DDRC2_COUNT_CAL_MASK) << 0)
>> +
>> +/* -------- MPDDRC_LPDDR2_TIM_CAL : (MPDDRC Offset: 0x30) */
>> +#define AT91C_DDRC2_ZQCS(value) (value << 0)
>> +
>> +/* -------- MPDDRC_IO_CALIBR : (MPDDRC Offset: 0x34) IO Calibration --------*/
>> +#define AT91C_MPDDRC_RDIV (0x7UL << 0)
>> +#define AT91C_MPDDRC_RDIV_LPDDR2_RZQ_34 (0x1UL << 0)
>> +#define AT91C_MPDDRC_RDIV_LPDDR2_RZQ_48 (0x3UL << 0)
>> +#define AT91C_MPDDRC_RDIV_LPDDR2_RZQ_60 (0x4UL << 0)
>> +#define AT91C_MPDDRC_RDIV_LPDDR2_RZQ_120 (0x7UL << 0)
>> +
>> +#define AT91C_MPDDRC_RDIV_DDR2_RZQ_33_3 (0x2UL << 0)
>> +#define AT91C_MPDDRC_RDIV_DDR2_RZQ_50 (0x4UL << 0)
>> +#define AT91C_MPDDRC_RDIV_DDR2_RZQ_66_7 (0x6UL << 0)
>> +#define AT91C_MPDDRC_RDIV_DDR2_RZQ_100 (0x7UL << 0)
>> +
>> +#define AT91C_MPDDRC_RDIV_LPDDR3_RZQ_38 (0x02UL << 0)
>> +#define AT91C_MPDDRC_RDIV_LPDDR3_RZQ_46 (0x03UL << 0)
>> +#define AT91C_MPDDRC_RDIV_LPDDR3_RZQ_57 (0x04UL << 0)
>> +#define AT91C_MPDDRC_RDIV_LPDDR3_RZQ_77 (0x06UL << 0)
>> +#define AT91C_MPDDRC_RDIV_LPDDR3_RZQ_115 (0x07UL << 0)
>> +
>> +#define AT91C_MPDDRC_ENABLE_CALIB (0x01 << 4)
>> +#define AT91C_MPDDRC_DISABLE_CALIB (0x00 << 4)
>> +#define AT91C_MPDDRC_EN_CALIB (0x01 << 4)
>> +
>> +#define AT91C_MPDDRC_TZQIO (0x7FUL << 8)
>> +#define AT91C_MPDDRC_TZQIO_(x) ((x) << 8)
>> +#define AT91C_MPDDRC_TZQIO_0 (0x0UL << 8)
>> +#define AT91C_MPDDRC_TZQIO_1 (0x1UL << 8)
>> +#define AT91C_MPDDRC_TZQIO_3 (0x3UL << 8)
>> +#define AT91C_MPDDRC_TZQIO_4 (0x4UL << 8)
>> +#define AT91C_MPDDRC_TZQIO_5 (0x5UL << 8)
>> +#define AT91C_MPDDRC_TZQIO_31 (0x1FUL << 8)
>> +
>> +#define AT91C_MPDDRC_CALCODEP (0xFUL << 16)
>> +#define AT91C_MPDDRC_CALCODEP_(x) ((x) << 16)
>> +
>> +#define AT91C_MPDDRC_CALCODEN (0xFUL << 20)
>> +#define AT91C_MPDDRC_CALCODEN_(x) ((x) << 20)
>> +
>> +/* ---- MPDDRC_RD_DATA_PATH : (MPDDRC Offset: 0x5c) MPDDRC Read Data Path */
>> +#define AT91_MPDDRC_SHIFT_SAMPLING (0x03 << 0)
>> +#define AT91C_MPDDRC_RD_DATA_PATH_NO_SHIFT (0x00 << 0)
>> +#define AT91C_MPDDRC_RD_DATA_PATH_ONE_CYCLES (0x01 << 0)
>> +#define AT91C_MPDDRC_RD_DATA_PATH_TWO_CYCLES (0x02 << 0)
>> +#define AT91C_MPDDRC_RD_DATA_PATH_THREE_CYCLES (0x03 << 0)
>> +
>> +/* -------- MPDDRC_DLL_MOR : (MPDDRC Offset: 0x74) DLL Master Offset Register --------*/
>> +#define AT91C_MPDDRC_MOFF(value) (value << 0)
>> +#define AT91C_MPDDRC_MOFF_1 (0x1UL << 0)
>> +#define AT91C_MPDDRC_MOFF_7 (0x7UL << 0)
>> +#define AT91C_MPDDRC_CLK90OFF(value) (value << 8)
>> +#define AT91C_MPDDRC_CLK90OFF_1 (0x1UL << 8)
>> +#define AT91C_MPDDRC_CLK90OFF_31 (0x1FUL << 8)
>> +#define AT91C_MPDDRC_SELOFF (0x1UL << 16)
>> +#define AT91C_MPDDRC_SELOFF_DISABLED (0x0UL << 16)
>> +#define AT91C_MPDDRC_SELOFF_ENABLED (0x1UL << 16)
>> +#define AT91C_MPDDRC_KEY (0xC5UL << 24)
>> +
>> +/* -------- MPDDRC_DLL_SOR : (MPDDRC Offset: 0x78) DLL Slave Offset Register --------*/
>> +#define AT91C_MPDDRC_S0OFF_1 (0x1UL << 0)
>> +#define AT91C_MPDDRC_S1OFF_1 (0x1UL << 8)
>> +#define AT91C_MPDDRC_S2OFF_1 (0x1UL << 16)
>> +#define AT91C_MPDDRC_S3OFF_1 (0x1UL << 24)
>> +
>> +#define AT91C_MPDDRC_S0OFF(value) (value << 0)
>> +#define AT91C_MPDDRC_S1OFF(value) (value << 8)
>> +#define AT91C_MPDDRC_S2OFF(value) (value << 16)
>> +#define AT91C_MPDDRC_S3OFF(value) (value << 24)
>> +
>> +/* -------- HDDRSDRC2_WPCR : (HDDRSDRC2 Offset: 0xe4) Write Protect Control Register --------*/
>> +#define AT91C_DDRC2_WPEN (0x1UL << 0)
>> +#define AT91C_DDRC2_WPKEY (0xFFFFFFUL << 8)
>> +
>> +/* -------- HDDRSDRC2_WPSR : (HDDRSDRC2 Offset: 0xe8) Write Protect Status Register --------*/
>> +#define AT91C_DDRC2_WPVS (0x1UL << 0)
>> +#define AT91C_DDRC2_WPSRC (0xFFFFUL << 8)
>> +
>> +#endif /* __AT91_DDRSDRC_H__ */
>> --
>> 2.20.1
>>
>>
>> _______________________________________________
>> barebox mailing list
>> barebox@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/barebox
>>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 02/15] ARM: at91: import at91bootstrap's at91_ddrsdrc.h
2019-04-01 13:36 ` Ahmad Fatoum
@ 2019-04-01 14:23 ` Roland Hieber
0 siblings, 0 replies; 43+ messages in thread
From: Roland Hieber @ 2019-04-01 14:23 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox, sam
On Mon, Apr 01, 2019 at 03:36:06PM +0200, Ahmad Fatoum wrote:
> Hello Roland,
>
> On 4/1/19 2:32 PM, Roland Hieber wrote:
> > On Mon, Apr 01, 2019 at 12:18:10PM +0200, Ahmad Fatoum wrote:
> >> Instead of adding missing definitions to the existing at91sam9_ddrsdr.h
> >> and adapting the incoming DDRAM initialization code from at91bootstrap,
> >> just replace the lightly used existing header with:
> >> https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/include/arch/at91_ddrsdrc.h
> >>
> >> For easier comprehension, the replacement is done in three steps:
> >> Here the header is imported.
> >>
> >> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> >> ---
> >> .../arm/mach-at91/include/mach/at91_ddrsdrc.h | 288 ++++++++++++++++++
> >> 1 file changed, 288 insertions(+)
> >> create mode 100644 arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
> >>
> >> diff --git a/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
> >> new file mode 100644
> >> index 000000000000..57d0d8f489c4
> >> --- /dev/null
> >> +++ b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
> >> @@ -0,0 +1,288 @@
> >> +// SPDX-License-Identifier: BSD-1-Clause
> >
> > I've told you this in our personal converation before, but I'll happily
> > repeat it here for a broader audience: The original GitHub source says
> >
> > * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
> > * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
> > * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
> > * DISCLAIMED.
> >
> > which additionally disclaims warranty for "NON-INFRINGEMENT", which is
> > not in BSD-1-Clause text you added in the previous commit. I regard this
> > as a substantive change of the licensing conditions according to the
> > SPDX License List Matching Guidelines [s] and rather use the original
> > license headers here as long as there is no SPDX license identifier for
> > it.
> To restate my opinion:
> Atmel already disclaims ANY EXPRESS or IMPLIED WARRANTIES, which should
> include NON-INFRINGEMENT regardless if whether it was explicitly listed
> or not.
Ah, good, it seems I misinterpreted your argument earlier. Sorry, so no
objections from my side then.
- Roland
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^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 03/15] ARM: at91: migrate at91sam9_ddrsdr.h to use at91bootstrap's at91_ddrsdrc.h
2019-04-01 10:18 [PATCH v3 00/15] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
2019-04-01 10:18 ` [PATCH v3 01/15] LICENSES: add BSD-1-Clause license Ahmad Fatoum
2019-04-01 10:18 ` [PATCH v3 02/15] ARM: at91: import at91bootstrap's at91_ddrsdrc.h Ahmad Fatoum
@ 2019-04-01 10:18 ` Ahmad Fatoum
2019-04-01 10:18 ` [PATCH v3 04/15] ARM: at91: replace at91sam9_ddrsdr.h with " Ahmad Fatoum
` (12 subsequent siblings)
15 siblings, 0 replies; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-01 10:18 UTC (permalink / raw)
To: barebox; +Cc: sam
Instead of adding missing definitions to the existing at91sam9_ddrsdr.h
and adapting the incoming DDRAM initialization code from at91bootstrap,
just replace the lightly used existing header with:
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/include/arch/at91_ddrsdrc.h
For easier comprehension, the replacement is done in three steps:
Here the existing at91sam9_ddrsdr.h has its now duplicate (in function,
not name) macros removed and existing users are migrated to use the new
header.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/mach-at91/at91sam9g45_reset.S | 6 +-
.../mach-at91/include/mach/at91sam9_ddrsdr.h | 138 ++----------------
2 files changed, 12 insertions(+), 132 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
index 6a58de618ce0..085683c7f9d8 100644
--- a/arch/arm/mach-at91/at91sam9g45_reset.S
+++ b/arch/arm/mach-at91/at91sam9g45_reset.S
@@ -20,13 +20,13 @@
.globl at91sam9g45_reset
at91sam9g45_reset: mov r2, #1
- mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
+ mov r3, #AT91C_DDRC2_LPCB_POWERDOWN
ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
.balign 32 @ align to cache line
- str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access
- str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0
+ str r2, [r0, #AT91C_HDDRSDRC2_RTR] @ disable DDR0 access
+ str r3, [r0, #AT91C_HDDRSDRC2_LPR] @ power down DDR0
str r4, [r1] @ reset processor
b .
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
index b50c11b128bf..22c00d9edaac 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -12,130 +12,10 @@
#ifndef AT91SAM9_DDRSDR_H
#define AT91SAM9_DDRSDR_H
-#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
-#define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */
-#define AT91_DDRSDRC_MODE_NORMAL 0
-#define AT91_DDRSDRC_MODE_NOP 1
-#define AT91_DDRSDRC_MODE_PRECHARGE 2
-#define AT91_DDRSDRC_MODE_LMR 3
-#define AT91_DDRSDRC_MODE_REFRESH 4
-#define AT91_DDRSDRC_MODE_EXT_LMR 5
-#define AT91_DDRSDRC_MODE_DEEP 6
-
-#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
-#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
-
-#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
-#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
-#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
-#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
-#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
-#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
-#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
-#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
-#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
-#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
-#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
-#define AT91_DDRSDRC_NR_11 (0 << 2)
-#define AT91_DDRSDRC_NR_12 (1 << 2)
-#define AT91_DDRSDRC_NR_13 (2 << 2)
-#define AT91_DDRSDRC_NR_14 (3 << 2)
-#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
-#define AT91_DDRSDRC_CAS_2 (2 << 4)
-#define AT91_DDRSDRC_CAS_3 (3 << 4)
-#define AT91_DDRSDRC_CAS_25 (6 << 4)
-#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */
-#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
-#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */
-#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
-#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */
-#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */
-#define AT91_DDRSDRC_NB (1 << 20) /* Number of
-Banks [not SAM9G45] */
-#define AT91_SDRAMC_NB_4 (0 << 20)
-#define AT91_SDRAMC_NB_8 (1 << 20)
-
-#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
-#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
-#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
-#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
-#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
-#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
-#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
-#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
-#define AT91CAP9_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
-#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
-#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
-
-#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
-#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
-#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
-#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
-#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
-
-#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register [SAM9 Only] */
-#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */
-#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */
-#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */
-#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
-
-#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
-#define AT91CAP9_DDRSDRC_LPR 0x18 /* Low Power Register */
-#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
-#define AT91_DDRSDRC_LPCB_DISABLE 0
-#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
-#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
-#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
-#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
-#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
-#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
-#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
-#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
-#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
-#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
-#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
-#define AT91_DDRSDRC_APDE (1 << 16) /* Active power down exit time */
-#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
-
-#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
-#define AT91CAP9_DDRSDRC_MDR 0x1C /* Memory Device Register */
-#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
-#define AT91_DDRSDRC_MD_SDR 0
-#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
-#define AT91CAP9_DDRSDRC_MD_DDR 2
-#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
-#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */
-#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
-#define AT91_DDRSDRC_DBW_32BITS (0 << 4)
-#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
-
-#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
-#define AT91CAP9_DDRSDRC_DLL 0x20 /* DLL Information Register */
-#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
-#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
-#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
-#define AT91CAP9_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
-#define AT91CAP9_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
-#define AT91CAP9_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
-#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
-#define AT91CAP9_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
-#define AT91CAP9_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
-
-#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */
-#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
-
-#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */
-
-#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */
-#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */
-#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */
-#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */
-
-#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register [SAM9 Only] */
-#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
-#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
+#include <mach/at91_ddrsdrc.h>
#ifndef __ASSEMBLY__
+#include <common.h>
#include <io.h>
static inline u32 at91_get_ddram_size(void * __iomem base, bool is_nb)
@@ -145,11 +25,11 @@ static inline u32 at91_get_ddram_size(void * __iomem base, bool is_nb)
u32 size;
bool is_sdram;
- cr = readl(base + AT91_DDRSDRC_CR);
- mdr = readl(base + AT91_DDRSDRC_MDR);
+ cr = readl(base + AT91C_HDDRSDRC2_CR);
+ mdr = readl(base + AT91C_HDDRSDRC2_MDR);
/* will always be false for sama5d2, sama5d3 or sama5d4 */
- is_sdram = (mdr & AT91_DDRSDRC_MD) <= AT91_DDRSDRC_MD_LOW_POWER_SDR;
+ is_sdram = (mdr & AT91C_DDRC2_MD) <= AT91C_DDRC2_MD_LP_SDR_SDRAM;
/* Formula:
* size = bank << (col + row + 1);
@@ -158,19 +38,19 @@ static inline u32 at91_get_ddram_size(void * __iomem base, bool is_nb)
*/
size = 1;
/* COL */
- size += (cr & AT91_DDRSDRC_NC) + 8;
+ size += (cr & AT91C_DDRC2_NC) + 8;
if (!is_sdram)
size ++;
/* ROW */
- size += ((cr & AT91_DDRSDRC_NR) >> 2) + 11;
+ size += ((cr & AT91C_DDRC2_NR) >> 2) + 11;
/* BANK */
if (is_nb)
- size = ((cr & AT91_DDRSDRC_NB) ? 8 : 4) << size;
+ size = ((cr & AT91C_DDRC2_NB_BANKS) ? 8 : 4) << size;
else
size = 4 << size;
/* bandwidth */
- if (!(mdr & AT91_DDRSDRC_DBW))
+ if (!(mdr & AT91C_DDRC2_DBW))
size <<= 1;
return size;
--
2.20.1
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^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v3 04/15] ARM: at91: replace at91sam9_ddrsdr.h with at91bootstrap's at91_ddrsdrc.h
2019-04-01 10:18 [PATCH v3 00/15] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
` (2 preceding siblings ...)
2019-04-01 10:18 ` [PATCH v3 03/15] ARM: at91: migrate at91sam9_ddrsdr.h to use " Ahmad Fatoum
@ 2019-04-01 10:18 ` Ahmad Fatoum
2019-04-02 17:25 ` Sam Ravnborg
2019-04-01 10:18 ` [PATCH v3 05/15] ARM: at91: watchdog: implement at91_wdt_disable Ahmad Fatoum
` (11 subsequent siblings)
15 siblings, 1 reply; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-01 10:18 UTC (permalink / raw)
To: barebox; +Cc: sam
Instead of adding missing definitions to the existing at91sam9_ddrsdr.h
and adapting the incoming DDRAM initialization code from at91bootstrap,
just replace the lightly used existing header with:
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/include/arch/at91_ddrsdrc.h
For easier comprehension, the replacement is done in three steps:
This last step copies the memory size querying functions from at91sam9_ddrsdr.h
to at91_ddrsdrc.h, then deletes it and fixes all references.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/boards/at91sam9m10g45ek/lowlevel.c | 2 +-
arch/arm/boards/at91sam9m10ihd/lowlevel.c | 2 +-
arch/arm/boards/at91sam9n12ek/lowlevel.c | 2 +-
arch/arm/boards/at91sam9x5ek/lowlevel.c | 2 +-
arch/arm/boards/pm9g45/lowlevel.c | 3 +-
arch/arm/boards/sama5d3_xplained/lowlevel.c | 2 +-
arch/arm/boards/sama5d3xek/lowlevel.c | 2 +-
arch/arm/boards/sama5d4_xplained/lowlevel.c | 2 +-
arch/arm/boards/sama5d4ek/lowlevel.c | 2 +-
arch/arm/mach-at91/at91sam9g45_devices.c | 2 +-
arch/arm/mach-at91/at91sam9g45_reset.S | 2 +-
arch/arm/mach-at91/at91sam9n12_devices.c | 2 +-
arch/arm/mach-at91/at91sam9x5_devices.c | 2 +-
.../arm/mach-at91/include/mach/at91_ddrsdrc.h | 44 +++++++++++++++++++
arch/arm/mach-at91/sama5d3_devices.c | 2 +-
arch/arm/mach-at91/sama5d4_devices.c | 2 +-
16 files changed, 60 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boards/at91sam9m10g45ek/lowlevel.c b/arch/arm/boards/at91sam9m10g45ek/lowlevel.c
index d5deedfc37b5..add97c641998 100644
--- a/arch/arm/boards/at91sam9m10g45ek/lowlevel.c
+++ b/arch/arm/boards/at91sam9m10g45ek/lowlevel.c
@@ -11,7 +11,7 @@
#include <asm/barebox-arm.h>
#include <mach/hardware.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
{
diff --git a/arch/arm/boards/at91sam9m10ihd/lowlevel.c b/arch/arm/boards/at91sam9m10ihd/lowlevel.c
index 24d41cfa70ea..92988d1945e8 100644
--- a/arch/arm/boards/at91sam9m10ihd/lowlevel.c
+++ b/arch/arm/boards/at91sam9m10ihd/lowlevel.c
@@ -10,7 +10,7 @@
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/at91sam9g45.h>
#include <mach/hardware.h>
diff --git a/arch/arm/boards/at91sam9n12ek/lowlevel.c b/arch/arm/boards/at91sam9n12ek/lowlevel.c
index 094fd941bc8c..9f460f71a896 100644
--- a/arch/arm/boards/at91sam9n12ek/lowlevel.c
+++ b/arch/arm/boards/at91sam9n12ek/lowlevel.c
@@ -10,7 +10,7 @@
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/hardware.h>
void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
diff --git a/arch/arm/boards/at91sam9x5ek/lowlevel.c b/arch/arm/boards/at91sam9x5ek/lowlevel.c
index 14c239408d6a..d87c0a99f424 100644
--- a/arch/arm/boards/at91sam9x5ek/lowlevel.c
+++ b/arch/arm/boards/at91sam9x5ek/lowlevel.c
@@ -1,6 +1,6 @@
#include <common.h>
#include <linux/sizes.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
#include <io.h>
diff --git a/arch/arm/boards/pm9g45/lowlevel.c b/arch/arm/boards/pm9g45/lowlevel.c
index fbf2b655c708..ec2ab7262245 100644
--- a/arch/arm/boards/pm9g45/lowlevel.c
+++ b/arch/arm/boards/pm9g45/lowlevel.c
@@ -10,7 +10,8 @@
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
+
#include <mach/hardware.h>
void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
diff --git a/arch/arm/boards/sama5d3_xplained/lowlevel.c b/arch/arm/boards/sama5d3_xplained/lowlevel.c
index 31c176a3a4c2..37384a160651 100644
--- a/arch/arm/boards/sama5d3_xplained/lowlevel.c
+++ b/arch/arm/boards/sama5d3_xplained/lowlevel.c
@@ -10,7 +10,7 @@
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/hardware.h>
void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
diff --git a/arch/arm/boards/sama5d3xek/lowlevel.c b/arch/arm/boards/sama5d3xek/lowlevel.c
index 31c176a3a4c2..37384a160651 100644
--- a/arch/arm/boards/sama5d3xek/lowlevel.c
+++ b/arch/arm/boards/sama5d3xek/lowlevel.c
@@ -10,7 +10,7 @@
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/hardware.h>
void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
diff --git a/arch/arm/boards/sama5d4_xplained/lowlevel.c b/arch/arm/boards/sama5d4_xplained/lowlevel.c
index 47cadfe6750c..89f0b8202eb1 100644
--- a/arch/arm/boards/sama5d4_xplained/lowlevel.c
+++ b/arch/arm/boards/sama5d4_xplained/lowlevel.c
@@ -10,7 +10,7 @@
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/hardware.h>
void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
diff --git a/arch/arm/boards/sama5d4ek/lowlevel.c b/arch/arm/boards/sama5d4ek/lowlevel.c
index 47cadfe6750c..89f0b8202eb1 100644
--- a/arch/arm/boards/sama5d4ek/lowlevel.c
+++ b/arch/arm/boards/sama5d4ek/lowlevel.c
@@ -10,7 +10,7 @@
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/hardware.h>
void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index df0c8a4e4f4e..ed655863e5c9 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -17,7 +17,7 @@
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
#include <mach/at91sam9g45_matrix.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/at91_rtt.h>
#include <mach/board.h>
#include <mach/iomux.h>
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
index 085683c7f9d8..9077871d7203 100644
--- a/arch/arm/mach-at91/at91sam9g45_reset.S
+++ b/arch/arm/mach-at91/at91sam9g45_reset.S
@@ -12,7 +12,7 @@
#include <linux/linkage.h>
#include <mach/hardware.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/at91_rstc.h>
.arm
diff --git a/arch/arm/mach-at91/at91sam9n12_devices.c b/arch/arm/mach-at91/at91sam9n12_devices.c
index 3ee07568f2c7..6ed7e4fdec41 100644
--- a/arch/arm/mach-at91/at91sam9n12_devices.c
+++ b/arch/arm/mach-at91/at91sam9n12_devices.c
@@ -18,7 +18,7 @@
#include <mach/board.h>
#include <mach/at91_pmc.h>
#include <mach/at91sam9n12_matrix.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/iomux.h>
#include <mach/cpu.h>
#include <i2c/i2c-gpio.h>
diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c
index f794d9ae8f73..e85d712293ac 100644
--- a/arch/arm/mach-at91/at91sam9x5_devices.c
+++ b/arch/arm/mach-at91/at91sam9x5_devices.c
@@ -17,7 +17,7 @@
#include <mach/board.h>
#include <mach/at91_pmc.h>
#include <mach/at91sam9x5_matrix.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/iomux.h>
#include <mach/cpu.h>
#include <i2c/i2c-gpio.h>
diff --git a/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
index 57d0d8f489c4..7e68e7dd63eb 100644
--- a/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
+++ b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
@@ -285,4 +285,48 @@
#define AT91C_DDRC2_WPVS (0x1UL << 0)
#define AT91C_DDRC2_WPSRC (0xFFFFUL << 8)
+#ifndef __ASSEMBLY__
+#include <common.h>
+#include <io.h>
+
+static inline u32 at91_get_ddram_size(void * __iomem base, bool is_nb)
+{
+ u32 cr;
+ u32 mdr;
+ u32 size;
+ bool is_sdram;
+
+ cr = readl(base + AT91C_HDDRSDRC2_CR);
+ mdr = readl(base + AT91C_HDDRSDRC2_MDR);
+
+ /* will always be false for sama5d2, sama5d3 or sama5d4 */
+ is_sdram = (mdr & AT91C_DDRC2_MD) <= AT91C_DDRC2_MD_LP_SDR_SDRAM;
+
+ /* Formula:
+ * size = bank << (col + row + 1);
+ * if (bandwidth == 32 bits)
+ * size <<= 1;
+ */
+ size = 1;
+ /* COL */
+ size += (cr & AT91C_DDRC2_NC) + 8;
+ if (!is_sdram)
+ size ++;
+ /* ROW */
+ size += ((cr & AT91C_DDRC2_NR) >> 2) + 11;
+ /* BANK */
+ if (is_nb)
+ size = ((cr & AT91C_DDRC2_NB_BANKS) ? 8 : 4) << size;
+ else
+ size = 4 << size;
+
+ /* bandwidth */
+ if (!(mdr & AT91C_DDRC2_DBW))
+ size <<= 1;
+
+ return size;
+}
+
+#endif /* __ASSEMBLY__ */
+
#endif /* __AT91_DDRSDRC_H__ */
diff --git a/arch/arm/mach-at91/sama5d3_devices.c b/arch/arm/mach-at91/sama5d3_devices.c
index 479e81f0f588..35e66de3f5f7 100644
--- a/arch/arm/mach-at91/sama5d3_devices.c
+++ b/arch/arm/mach-at91/sama5d3_devices.c
@@ -18,7 +18,7 @@
#include <mach/board.h>
#include <mach/at91_pmc.h>
#include <mach/at91sam9x5_matrix.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/iomux.h>
#include <mach/cpu.h>
#include <i2c/i2c-gpio.h>
diff --git a/arch/arm/mach-at91/sama5d4_devices.c b/arch/arm/mach-at91/sama5d4_devices.c
index 4a6683981595..c9c3960258eb 100644
--- a/arch/arm/mach-at91/sama5d4_devices.c
+++ b/arch/arm/mach-at91/sama5d4_devices.c
@@ -19,7 +19,7 @@
#include <mach/board.h>
#include <mach/at91_pmc.h>
#include <mach/at91sam9x5_matrix.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/iomux.h>
#include <mach/cpu.h>
#include <i2c/i2c-gpio.h>
--
2.20.1
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^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH v3 04/15] ARM: at91: replace at91sam9_ddrsdr.h with at91bootstrap's at91_ddrsdrc.h
2019-04-01 10:18 ` [PATCH v3 04/15] ARM: at91: replace at91sam9_ddrsdr.h with " Ahmad Fatoum
@ 2019-04-02 17:25 ` Sam Ravnborg
2019-04-02 18:36 ` Ahmad Fatoum
0 siblings, 1 reply; 43+ messages in thread
From: Sam Ravnborg @ 2019-04-02 17:25 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
Hi Ahmad.
On Mon, Apr 01, 2019 at 12:18:12PM +0200, Ahmad Fatoum wrote:
> Instead of adding missing definitions to the existing at91sam9_ddrsdr.h
> and adapting the incoming DDRAM initialization code from at91bootstrap,
> just replace the lightly used existing header with:
> https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/include/arch/at91_ddrsdrc.h
>
> For easier comprehension, the replacement is done in three steps:
> This last step copies the memory size querying functions from at91sam9_ddrsdr.h
> to at91_ddrsdrc.h, then deletes it and fixes all references.
>
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> diff --git a/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
> index 57d0d8f489c4..7e68e7dd63eb 100644
> --- a/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
> +++ b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
> @@ -285,4 +285,48 @@
> #define AT91C_DDRC2_WPVS (0x1UL << 0)
> #define AT91C_DDRC2_WPSRC (0xFFFFUL << 8)
>
> +#ifndef __ASSEMBLY__
> +#include <common.h>
> +#include <io.h>
> +
> +static inline u32 at91_get_ddram_size(void * __iomem base, bool is_nb)
> +{
I should have brought this up in the previous patch-set, but it continue to itch me.
So you get the feedback here....
We have at91_get_ddram_size(IOMEM(xxx), {true or false})
If we introduced the following small helpers we could simplify the call sites
to just use at91_get_ddram_size(AT91SAM9G45_BASE_DDRSDRC0) and similar.
static inline u32 at91_get_ddram_size(void __force __iomem * addr)
{
return __at91_get_ddram_size(IOMEM(addr), true);
}
static inline u32 at91sam9g45_get_ddram_size(void __force __iomem * addr)
{
return __at91_get_ddram_size(IOMEM(addr), false);
}
But then for the few call sites it is not really worth it anyway.
Anyway, just a small itch. Just ignore it.
Sam
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^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH v3 04/15] ARM: at91: replace at91sam9_ddrsdr.h with at91bootstrap's at91_ddrsdrc.h
2019-04-02 17:25 ` Sam Ravnborg
@ 2019-04-02 18:36 ` Ahmad Fatoum
2019-04-02 19:18 ` Sam Ravnborg
0 siblings, 1 reply; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-02 18:36 UTC (permalink / raw)
To: Sam Ravnborg; +Cc: barebox
Hi Sam,
On 2/4/19 19:25, Sam Ravnborg wrote:
> Hi Ahmad.
>
> On Mon, Apr 01, 2019 at 12:18:12PM +0200, Ahmad Fatoum wrote:
>> Instead of adding missing definitions to the existing at91sam9_ddrsdr.h
>> and adapting the incoming DDRAM initialization code from at91bootstrap,
>> just replace the lightly used existing header with:
>> https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/include/arch/at91_ddrsdrc.h
>>
>> For easier comprehension, the replacement is done in three steps:
>> This last step copies the memory size querying functions from at91sam9_ddrsdr.h
>> to at91_ddrsdrc.h, then deletes it and fixes all references.
>>
>> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
>> ---
>
>
>> diff --git a/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
>> index 57d0d8f489c4..7e68e7dd63eb 100644
>> --- a/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
>> +++ b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
>> @@ -285,4 +285,48 @@
>> #define AT91C_DDRC2_WPVS (0x1UL << 0)
>> #define AT91C_DDRC2_WPSRC (0xFFFFUL << 8)
>>
>> +#ifndef __ASSEMBLY__
>> +#include <common.h>
>> +#include <io.h>
>> +
>> +static inline u32 at91_get_ddram_size(void * __iomem base, bool is_nb)
>> +{
>
> I should have brought this up in the previous patch-set, but it continue to itch me.
> So you get the feedback here....
>
> We have at91_get_ddram_size(IOMEM(xxx), {true or false})
>
> If we introduced the following small helpers we could simplify the call sites
> to just use at91_get_ddram_size(AT91SAM9G45_BASE_DDRSDRC0) and similar.
>
> static inline u32 at91_get_ddram_size(void __force __iomem * addr)
> {
> return __at91_get_ddram_size(IOMEM(addr), true);
> }
>
> static inline u32 at91sam9g45_get_ddram_size(void __force __iomem * addr)
> {
> return __at91_get_ddram_size(IOMEM(addr), false);
> }
That would still require the pointer cast to pacify the -Wint-conversion.
And (void*)ADDR looks only marginally better IOMEM(ADDR) IMO
at the cost of having sparse miss passing memory pointers
(__force __iomem would be equivalent to just __attribute__((noderef)), wouldn't it?)
My preference would've been that AT91SAM9G45_BASE_DDRSDRC0 already expands
to a void __iomem *. We could do that in a follow-up patch.
>
> But then for the few call sites it is not really worth it anyway.
> Anyway, just a small itch. Just ignore it.
>
> Sam
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH v3 04/15] ARM: at91: replace at91sam9_ddrsdr.h with at91bootstrap's at91_ddrsdrc.h
2019-04-02 18:36 ` Ahmad Fatoum
@ 2019-04-02 19:18 ` Sam Ravnborg
2019-04-03 7:22 ` Sascha Hauer
2019-04-03 9:54 ` Ahmad Fatoum
0 siblings, 2 replies; 43+ messages in thread
From: Sam Ravnborg @ 2019-04-02 19:18 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
Hi Ahmad.
> >
> > If we introduced the following small helpers we could simplify the call sites
> > to just use at91_get_ddram_size(AT91SAM9G45_BASE_DDRSDRC0) and similar.
> >
> > static inline u32 at91_get_ddram_size(void __force __iomem * addr)
> > {
> > return __at91_get_ddram_size(IOMEM(addr), true);
> > }
> >
> > static inline u32 at91sam9g45_get_ddram_size(void __force __iomem * addr)
> > {
> > return __at91_get_ddram_size(IOMEM(addr), false);
> > }
>
> That would still require the pointer cast to pacify the -Wint-conversion.
> And (void*)ADDR looks only marginally better IOMEM(ADDR) IMO
> at the cost of having sparse miss passing memory pointers
> (__force __iomem would be equivalent to just __attribute__((noderef)), wouldn't it?)
>
> My preference would've been that AT91SAM9G45_BASE_DDRSDRC0 already expands
> to a void __iomem *.
The main idea was to get rid of the bool argument and use more explicit function
names. Moving IOMEM() was the added extra.
> We could do that in a follow-up patch.
Agreed, maybe later if we do it.
The original patch in this mail was fine.
You can add my:
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
If you respin the series.
Sam
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^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH v3 04/15] ARM: at91: replace at91sam9_ddrsdr.h with at91bootstrap's at91_ddrsdrc.h
2019-04-02 19:18 ` Sam Ravnborg
@ 2019-04-03 7:22 ` Sascha Hauer
2019-04-03 9:54 ` Ahmad Fatoum
1 sibling, 0 replies; 43+ messages in thread
From: Sascha Hauer @ 2019-04-03 7:22 UTC (permalink / raw)
To: Sam Ravnborg; +Cc: barebox, Ahmad Fatoum
On Tue, Apr 02, 2019 at 09:18:37PM +0200, Sam Ravnborg wrote:
> Hi Ahmad.
>
> > >
> > > If we introduced the following small helpers we could simplify the call sites
> > > to just use at91_get_ddram_size(AT91SAM9G45_BASE_DDRSDRC0) and similar.
> > >
> > > static inline u32 at91_get_ddram_size(void __force __iomem * addr)
> > > {
> > > return __at91_get_ddram_size(IOMEM(addr), true);
> > > }
> > >
> > > static inline u32 at91sam9g45_get_ddram_size(void __force __iomem * addr)
> > > {
> > > return __at91_get_ddram_size(IOMEM(addr), false);
> > > }
> >
> > That would still require the pointer cast to pacify the -Wint-conversion.
> > And (void*)ADDR looks only marginally better IOMEM(ADDR) IMO
> > at the cost of having sparse miss passing memory pointers
> > (__force __iomem would be equivalent to just __attribute__((noderef)), wouldn't it?)
> >
> > My preference would've been that AT91SAM9G45_BASE_DDRSDRC0 already expands
> > to a void __iomem *.
> The main idea was to get rid of the bool argument and use more explicit function
> names.
+1 for explicit function names. It's easier for the caller to get it
right.
Sascha
--
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Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH v3 04/15] ARM: at91: replace at91sam9_ddrsdr.h with at91bootstrap's at91_ddrsdrc.h
2019-04-02 19:18 ` Sam Ravnborg
2019-04-03 7:22 ` Sascha Hauer
@ 2019-04-03 9:54 ` Ahmad Fatoum
1 sibling, 0 replies; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-03 9:54 UTC (permalink / raw)
To: Sam Ravnborg; +Cc: barebox
Hi,
On 2/4/19 21:18, Sam Ravnborg wrote:
> Hi Ahmad.
>
>>>
>>> If we introduced the following small helpers we could simplify the call sites
>>> to just use at91_get_ddram_size(AT91SAM9G45_BASE_DDRSDRC0) and similar.
>>>
>>> static inline u32 at91_get_ddram_size(void __force __iomem * addr)
>>> {
>>> return __at91_get_ddram_size(IOMEM(addr), true);
>>> }
>>>
>>> static inline u32 at91sam9g45_get_ddram_size(void __force __iomem * addr)
>>> {
>>> return __at91_get_ddram_size(IOMEM(addr), false);
>>> }
>>
>> That would still require the pointer cast to pacify the -Wint-conversion.
>> And (void*)ADDR looks only marginally better IOMEM(ADDR) IMO
>> at the cost of having sparse miss passing memory pointers
>> (__force __iomem would be equivalent to just __attribute__((noderef)), wouldn't it?)
>>
>> My preference would've been that AT91SAM9G45_BASE_DDRSDRC0 already expands
>> to a void __iomem *.
> The main idea was to get rid of the bool argument and use more explicit function
> names. Moving IOMEM() was the added extra.
Ah, I see now what you mean. I'll respin the series anyway, so I'll revert to
what I did in the previous series version (SoC-family-specific helper).
>
>> We could do that in a follow-up patch.
> Agreed, maybe later if we do it.
> The original patch in this mail was fine.
>
> You can add my:
> Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
>
> If you respin the series.
>
> Sam
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 05/15] ARM: at91: watchdog: implement at91_wdt_disable
2019-04-01 10:18 [PATCH v3 00/15] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
` (3 preceding siblings ...)
2019-04-01 10:18 ` [PATCH v3 04/15] ARM: at91: replace at91sam9_ddrsdr.h with " Ahmad Fatoum
@ 2019-04-01 10:18 ` Ahmad Fatoum
2019-04-02 17:38 ` Sam Ravnborg
2019-04-01 10:18 ` [PATCH v3 06/15] ARM: at91: import lowlevel clock initialization from at91bootstrap Ahmad Fatoum
` (10 subsequent siblings)
15 siblings, 1 reply; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-01 10:18 UTC (permalink / raw)
To: barebox; +Cc: sam
Low level init code might want to disable the watchdog in PBL.
Provide a helper to do so.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/mach-at91/include/mach/at91_wdt.h | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h
index 36d37b9d2d64..d295d35d1b5c 100644
--- a/arch/arm/mach-at91/include/mach/at91_wdt.h
+++ b/arch/arm/mach-at91/include/mach/at91_wdt.h
@@ -35,4 +35,20 @@
#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */
#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */
+#ifndef __ASSEMBLY__
+// SPDX-License-Identifier: BSD-1-Clause
+/*
+ * Copyright (c) 2006, Atmel Corporation
+ */
+
+#include <asm-generic/io.h>
+
+static inline void at91_wdt_disable(void __iomem *wdt_base)
+{
+ u32 reg = readl(wdt_base + AT91_WDT_MR);
+ reg |= AT91_WDT_WDDIS;
+ writel(reg, wdt_base + AT91_WDT_MR);
+}
+
+#endif /* __ASSEMBLY__ */
#endif
--
2.20.1
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^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH v3 05/15] ARM: at91: watchdog: implement at91_wdt_disable
2019-04-01 10:18 ` [PATCH v3 05/15] ARM: at91: watchdog: implement at91_wdt_disable Ahmad Fatoum
@ 2019-04-02 17:38 ` Sam Ravnborg
2019-04-02 18:39 ` Ahmad Fatoum
0 siblings, 1 reply; 43+ messages in thread
From: Sam Ravnborg @ 2019-04-02 17:38 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
Hi Ahmad.
On Mon, Apr 01, 2019 at 12:18:13PM +0200, Ahmad Fatoum wrote:
> Low level init code might want to disable the watchdog in PBL.
> Provide a helper to do so.
>
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> arch/arm/mach-at91/include/mach/at91_wdt.h | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h
> index 36d37b9d2d64..d295d35d1b5c 100644
> --- a/arch/arm/mach-at91/include/mach/at91_wdt.h
> +++ b/arch/arm/mach-at91/include/mach/at91_wdt.h
> @@ -35,4 +35,20 @@
> #define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */
> #define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */
>
> +#ifndef __ASSEMBLY__
> +// SPDX-License-Identifier: BSD-1-Clause
> +/*
> + * Copyright (c) 2006, Atmel Corporation
> + */
> +
> +#include <asm-generic/io.h>
> +
> +static inline void at91_wdt_disable(void __iomem *wdt_base)
As we are copying a lot of code from at91bootstrap could
we then use the same name for this function:
driver/at91_wdt.c:void at91_disable_wdt(void)
In at91bootstrap the address is a build time constant,
but passing it as an value is better.
So that part I do not ask you to consider to copy.
Sam
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^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 05/15] ARM: at91: watchdog: implement at91_wdt_disable
2019-04-02 17:38 ` Sam Ravnborg
@ 2019-04-02 18:39 ` Ahmad Fatoum
2019-04-02 19:20 ` Sam Ravnborg
0 siblings, 1 reply; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-02 18:39 UTC (permalink / raw)
To: Sam Ravnborg; +Cc: barebox
Hello Sam,
On 2/4/19 19:38, Sam Ravnborg wrote:
> Hi Ahmad.
>
> On Mon, Apr 01, 2019 at 12:18:13PM +0200, Ahmad Fatoum wrote:
>> Low level init code might want to disable the watchdog in PBL.
>> Provide a helper to do so.
>>
>> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
>> ---
>> arch/arm/mach-at91/include/mach/at91_wdt.h | 16 ++++++++++++++++
>> 1 file changed, 16 insertions(+)
>>
>> diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h
>> index 36d37b9d2d64..d295d35d1b5c 100644
>> --- a/arch/arm/mach-at91/include/mach/at91_wdt.h
>> +++ b/arch/arm/mach-at91/include/mach/at91_wdt.h
>> @@ -35,4 +35,20 @@
>> #define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */
>> #define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */
>>
>> +#ifndef __ASSEMBLY__
>> +// SPDX-License-Identifier: BSD-1-Clause
>> +/*
>> + * Copyright (c) 2006, Atmel Corporation
>> + */
>> +
>> +#include <asm-generic/io.h>
>> +
>> +static inline void at91_wdt_disable(void __iomem *wdt_base)
>
> As we are copying a lot of code from at91bootstrap could
> we then use the same name for this function:
> driver/at91_wdt.c:void at91_disable_wdt(void)
${arch}_${subsystem}_${function} seems to be the usual naming scheme
for "globals". Why differ? I don't see the utility of copying
the at91bootstrap name.
>
> In at91bootstrap the address is a build time constant,
> but passing it as an value is better.
> So that part I do not ask you to consider to copy.
>
> Sam
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH v3 05/15] ARM: at91: watchdog: implement at91_wdt_disable
2019-04-02 18:39 ` Ahmad Fatoum
@ 2019-04-02 19:20 ` Sam Ravnborg
0 siblings, 0 replies; 43+ messages in thread
From: Sam Ravnborg @ 2019-04-02 19:20 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
On Tue, Apr 02, 2019 at 08:39:56PM +0200, Ahmad Fatoum wrote:
> Hello Sam,
>
> On 2/4/19 19:38, Sam Ravnborg wrote:
> > Hi Ahmad.
> >
> > On Mon, Apr 01, 2019 at 12:18:13PM +0200, Ahmad Fatoum wrote:
> >> Low level init code might want to disable the watchdog in PBL.
> >> Provide a helper to do so.
> >>
> >> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> >> ---
> >> arch/arm/mach-at91/include/mach/at91_wdt.h | 16 ++++++++++++++++
> >> 1 file changed, 16 insertions(+)
> >>
> >> diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h
> >> index 36d37b9d2d64..d295d35d1b5c 100644
> >> --- a/arch/arm/mach-at91/include/mach/at91_wdt.h
> >> +++ b/arch/arm/mach-at91/include/mach/at91_wdt.h
> >> @@ -35,4 +35,20 @@
> >> #define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */
> >> #define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */
> >>
> >> +#ifndef __ASSEMBLY__
> >> +// SPDX-License-Identifier: BSD-1-Clause
> >> +/*
> >> + * Copyright (c) 2006, Atmel Corporation
> >> + */
> >> +
> >> +#include <asm-generic/io.h>
> >> +
> >> +static inline void at91_wdt_disable(void __iomem *wdt_base)
> >
> > As we are copying a lot of code from at91bootstrap could
> > we then use the same name for this function:
> > driver/at91_wdt.c:void at91_disable_wdt(void)
>
> ${arch}_${subsystem}_${function} seems to be the usual naming scheme
> for "globals". Why differ? I don't see the utility of copying
> the at91bootstrap name.
Yeah, keep it in line with barebox is better.
It was more a something I stumbled upon comment.
Here you can also add my:
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Sam
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^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 06/15] ARM: at91: import lowlevel clock initialization from at91bootstrap
2019-04-01 10:18 [PATCH v3 00/15] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
` (4 preceding siblings ...)
2019-04-01 10:18 ` [PATCH v3 05/15] ARM: at91: watchdog: implement at91_wdt_disable Ahmad Fatoum
@ 2019-04-01 10:18 ` Ahmad Fatoum
2019-04-02 17:42 ` Sam Ravnborg
2019-04-01 10:18 ` [PATCH v3 07/15] ARM: at91: import early_udelay " Ahmad Fatoum
` (9 subsequent siblings)
15 siblings, 1 reply; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-01 10:18 UTC (permalink / raw)
To: barebox; +Cc: sam
For use by future at91 first stage bootloaders, this commit imports
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/pmc.c
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/mach-at91/Makefile | 1 +
arch/arm/mach-at91/at91_pmc_ll.c | 184 ++++++++++++++++++
arch/arm/mach-at91/include/mach/at91_pmc.h | 24 ++-
arch/arm/mach-at91/include/mach/at91_pmc_ll.h | 78 ++++++++
4 files changed, 284 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/mach-at91/at91_pmc_ll.c
create mode 100644 arch/arm/mach-at91/include/mach/at91_pmc_ll.h
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index d81683ac121a..91b06c085107 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,4 +1,5 @@
obj-y += setup.o
+pbl-y += at91_pmc_ll.o
ifeq ($(CONFIG_COMMON_CLK_OF_PROVIDER),)
obj-y += clock.o
diff --git a/arch/arm/mach-at91/at91_pmc_ll.c b/arch/arm/mach-at91/at91_pmc_ll.c
new file mode 100644
index 000000000000..bb3b3e6cf970
--- /dev/null
+++ b/arch/arm/mach-at91/at91_pmc_ll.c
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: BSD-1-Clause
+/*
+ * Copyright (c) 2006, Atmel Corporation
+ */
+
+#include <common.h>
+#include <mach/at91_pmc_ll.h>
+
+#define at91_pmc_write(off, val) writel(val, pmc_base + off)
+#define at91_pmc_read(off) readl(pmc_base + off)
+
+void at91_pmc_init(void __iomem *pmc_base, unsigned int flags)
+{
+ u32 tmp;
+
+ /*
+ * Switch the master clock to the slow clock without modifying other
+ * parameters. It is assumed that ROM code set H32MXDIV, PLLADIV2,
+ * PCK_DIV3.
+ */
+ tmp = at91_pmc_read(AT91_PMC_MCKR);
+ tmp &= ~AT91_PMC_ALT_PCKR_CSS;
+ tmp |= AT91_PMC_CSS_SLOW;
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MCKRDY))
+ ;
+
+ if (flags & AT91_PMC_LL_FLAG_SAM9X5_PMC) {
+ /*
+ * Enable the Main Crystal Oscillator
+ * tST_max = 2ms
+ * Startup Time: 32768 * 2ms / 8 = 8
+ */
+ tmp = at91_pmc_read(AT91_CKGR_MOR);
+ tmp &= ~AT91_PMC_OSCOUNT;
+ tmp &= ~AT91_PMC_KEY_MASK;
+ tmp |= AT91_PMC_MOSCEN;
+ tmp |= AT91_PMC_OSCOUNT_(8);
+ tmp |= AT91_PMC_KEY;
+ at91_pmc_write(AT91_CKGR_MOR, tmp);
+
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MOSCS))
+ ;
+
+ if (flags & AT91_PMC_LL_FLAG_MEASURE_XTAL) {
+ /* Enable a measurement of the Main Crystal Oscillator */
+ tmp = at91_pmc_read(AT91_CKGR_MCFR);
+ tmp |= AT91_PMC_CCSS_XTAL_OSC;
+ tmp |= AT91_PMC_RCMEAS;
+ at91_pmc_write(AT91_CKGR_MCFR, tmp);
+
+ while (!(at91_pmc_read(AT91_CKGR_MCFR) & AT91_PMC_MAINRDY))
+ ;
+ }
+
+
+ /* Switch from internal 12MHz RC to the Main Crystal Oscillator */
+ tmp = at91_pmc_read(AT91_CKGR_MOR);
+ tmp &= ~AT91_PMC_OSCBYPASS;
+ tmp &= ~AT91_PMC_KEY_MASK;
+ tmp |= AT91_PMC_KEY;
+ at91_pmc_write(AT91_CKGR_MOR, tmp);
+
+ tmp = at91_pmc_read(AT91_CKGR_MOR);
+ tmp |= AT91_PMC_MOSCSEL;
+ tmp &= ~AT91_PMC_KEY_MASK;
+ tmp |= AT91_PMC_KEY;
+ at91_pmc_write(AT91_CKGR_MOR, tmp);
+
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MOSCSELS))
+ ;
+
+ if (flags & AT91_PMC_LL_FLAG_DISABLE_RC) {
+ /* Disable the 12MHz RC Oscillator */
+ tmp = at91_pmc_read(AT91_CKGR_MOR);
+ tmp &= ~AT91_PMC_MOSCRCEN;
+ tmp &= ~AT91_PMC_KEY_MASK;
+ tmp |= AT91_PMC_KEY;
+ at91_pmc_write(AT91_CKGR_MOR, tmp);
+ }
+
+ } else {
+ /*
+ * Enable the Main Crystal Oscillator
+ * tST_max = 2ms
+ * Startup Time: 32768 * 2ms / 8 = 8
+ */
+ tmp = at91_pmc_read(AT91_CKGR_MOR);
+ tmp &= ~AT91_PMC_OSCOUNT;
+ tmp |= AT91_PMC_MOSCEN;
+ tmp |= AT91_PMC_OSCOUNT_(8);
+ at91_pmc_write(AT91_CKGR_MOR, tmp);
+
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MOSCS))
+ ;
+ }
+
+ /* After stablization, switch to Main Clock */
+ if ((at91_pmc_read(AT91_PMC_MCKR) & AT91_PMC_ALT_PCKR_CSS) == AT91_PMC_CSS_SLOW) {
+ tmp = at91_pmc_read(AT91_PMC_MCKR);
+ tmp &= ~(0x1 << 13);
+ tmp &= ~AT91_PMC_ALT_PCKR_CSS;
+ tmp |= AT91_PMC_CSS_MAIN;
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MCKRDY))
+ ;
+
+ tmp &= ~AT91_PMC_PRES;
+ tmp |= AT91_PMC_PRES_1;
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MCKRDY))
+ ;
+ }
+}
+
+void at91_pmc_cfg_plla(void __iomem *pmc_base, u32 pmc_pllar,
+ unsigned int __always_unused flags)
+{
+ /* Always disable PLL before configuring it */
+ at91_pmc_write(AT91_CKGR_PLLAR, AT91_PMC_PLLA_WR_ERRATA);
+ at91_pmc_write(AT91_CKGR_PLLAR, AT91_PMC_PLLA_WR_ERRATA | pmc_pllar);
+
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKA))
+ ;
+}
+
+void at91_pmc_cfg_mck(void __iomem *pmc_base, u32 pmc_mckr, unsigned int flags)
+{
+ u32 tmp;
+
+ /*
+ * Program the PRES field in the AT91_PMC_MCKR register
+ */
+ tmp = at91_pmc_read(AT91_PMC_MCKR);
+ tmp &= ~(0x1 << 13);
+
+ if (flags & AT91_PMC_LL_FLAG_SAM9X5_PMC) {
+ tmp &= ~AT91_PMC_ALT_PRES;
+ tmp |= pmc_mckr & AT91_PMC_ALT_PRES;
+ } else {
+ tmp &= ~AT91_PMC_PRES;
+ tmp |= pmc_mckr & AT91_PMC_PRES;
+ }
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+
+ /*
+ * Program the MDIV field in the AT91_PMC_MCKR register
+ */
+ tmp = at91_pmc_read(AT91_PMC_MCKR);
+ tmp &= ~AT91_PMC_MDIV;
+ tmp |= pmc_mckr & AT91_PMC_MDIV;
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+
+ /*
+ * Program the PLLADIV2 field in the AT91_PMC_MCKR register
+ */
+ tmp = at91_pmc_read(AT91_PMC_MCKR);
+ tmp &= ~AT91_PMC_PLLADIV2;
+ tmp |= pmc_mckr & AT91_PMC_PLLADIV2;
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+
+ /*
+ * Program the H32MXDIV field in the AT91_PMC_MCKR register
+ */
+ tmp = at91_pmc_read(AT91_PMC_MCKR);
+ tmp &= ~AT91_PMC_H32MXDIV;
+ tmp |= pmc_mckr & AT91_PMC_H32MXDIV;
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+
+ /*
+ * Program the CSS field in the AT91_PMC_MCKR register,
+ * wait for MCKRDY bit to be set in the PMC_SR register
+ */
+ tmp = at91_pmc_read(AT91_PMC_MCKR);
+ tmp &= ~AT91_PMC_ALT_PCKR_CSS;
+ tmp |= pmc_mckr & AT91_PMC_ALT_PCKR_CSS;
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MCKRDY))
+ ;
+}
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index bbbd497afaed..4d60becefbab 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -50,14 +50,19 @@
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */
#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
-#define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */
+#define AT91_PMC_OSCOUNT_(x) ((x) << 8)
+#define AT91_PMC_KEY_MASK (0xff << 16) /* MOR Writing Key */
+#define AT91_PMC_KEY (0x37 << 16)
#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */
#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */
#define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
-#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
-
+#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Frequency Measure Ready */
+#define AT91_PMC_RCMEAS (1 << 20) /* RC Oscillator Frequency Measure (write-only) */
+#define AT91_PMC_CCSS (1 << 24) /* Counter Clock Source Selection */
+#define AT91_PMC_CCSS_RC_OSC (0 << 24) /* MAINF counter clock is the RC oscillator. */
+#define AT91_PMC_CCSS_XTAL_OSC (1 << 24) /* MAINF counter clock is the crystal oscillator. */
#define AT91_CKGR_PLLAR 0x28 /* PLL A Register */
#define AT91_CKGR_PLLBR 0x2c /* PLL B Register */
#define AT91_PMC_DIV (0xff << 0) /* Divider */
@@ -133,6 +138,7 @@
#define AT91_PMC_CSSMCK_MCK (1 << 8)
#define AT91_PMC_IER 0x60 /* Interrupt Enable Register */
+#define AT91_PMC_MOSCXTS (1 << 0) /* Oscillator Startup Time */
#define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */
#define AT91_PMC_SR 0x68 /* Status Register */
#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
@@ -148,6 +154,17 @@
#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */
#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */
+#define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */
+#define AT91_PMC_ICPPLLA (0xf << 0)
+#define AT91_PMC_ICPPLLA_0 (0 << 0)
+#define AT91_PMC_ICPPLLA_1 (1 << 0)
+#define AT91_PMC_REALLOCK (0x1 << 7)
+#define AT91_PMC_IPLLA (0xf << 8)
+#define AT91_PMC_IPLLA_0 (0 << 8)
+#define AT91_PMC_IPLLA_1 (1 << 8)
+#define AT91_PMC_IPLLA_2 (2 << 8)
+#define AT91_PMC_IPLLA_3 (3 << 8)
+
#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */
#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */
@@ -163,6 +180,7 @@
#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9] */
#define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */
#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command */
+#define AT91_PMC_PCR_DIV_MASK (0x3 << 16)
#define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor value */
#define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */
#define AT91_PMC_PCR_DIV2 0x1 /* Peripheral clock is MCK/2 */
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc_ll.h b/arch/arm/mach-at91/include/mach/at91_pmc_ll.h
new file mode 100644
index 000000000000..eda40e8e12e7
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_pmc_ll.h
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: BSD-1-Clause
+/*
+ * Copyright (c) 2006, Atmel Corporation
+ */
+
+#ifndef AT91_PMC_LL_H
+#define AT91_PMC_LL_H
+
+#include <errno.h>
+#include <asm/io.h>
+#include <mach/at91_pmc.h>
+
+#define AT91_PMC_LL_FLAG_SAM9X5_PMC (1 << 0)
+#define AT91_PMC_LL_FLAG_MEASURE_XTAL (1 << 1)
+#define AT91_PMC_LL_FLAG_DISABLE_RC (1 << 2)
+
+#define AT91_PMC_LL_AT91RM9200 (0)
+#define AT91_PMC_LL_AT91SAM9260 (0)
+#define AT91_PMC_LL_AT91SAM9261 (0)
+#define AT91_PMC_LL_AT91SAM9263 (0)
+#define AT91_PMC_LL_AT91SAM9G45 (0)
+#define AT91_PMC_LL_AT91SAM9X5 (AT91_PMC_LL_FLAG_SAM9X5_PMC | \
+ AT91_PMC_LL_FLAG_DISABLE_RC)
+#define AT91_PMC_LL_AT91SAM9N12 (AT91_PMC_LL_FLAG_SAM9X5_PMC | \
+ AT91_PMC_LL_FLAG_DISABLE_RC)
+#define AT91_PMC_LL_SAMA5D2 (AT91_PMC_LL_FLAG_SAM9X5_PMC | \
+ AT91_PMC_LL_FLAG_MEASURE_XTAL)
+#define AT91_PMC_LL_SAMA5D3 (AT91_PMC_LL_FLAG_SAM9X5_PMC | \
+ AT91_PMC_LL_FLAG_DISABLE_RC)
+#define AT91_PMC_LL_SAMA5D4 (AT91_PMC_LL_FLAG_SAM9X5_PMC)
+
+void at91_pmc_init(void __iomem *pmc_base, unsigned int flags);
+void at91_pmc_cfg_mck(void __iomem *pmc_base, u32 pmc_mckr, unsigned int flags);
+void at91_pmc_cfg_plla(void __iomem *pmc_base, u32 pmc_pllar, unsigned int flags);
+
+static inline void at91_pmc_init_pll(void __iomem *pmc_base, u32 pmc_pllicpr)
+{
+ writel(pmc_pllicpr, pmc_base + AT91_PMC_PLLICPR);
+}
+
+static inline void at91_pmc_enable_system_clock(void __iomem *pmc_base,
+ unsigned clock_id)
+{
+ writel(clock_id, pmc_base + AT91_PMC_SCER);
+}
+
+static inline int at91_pmc_enable_periph_clock(void __iomem *pmc_base,
+ unsigned periph_id)
+{
+ u32 mask = 0x01 << (periph_id % 32);
+
+ if ((periph_id / 32) == 1)
+ writel(mask, pmc_base + AT91_PMC_PCER1);
+ else if ((periph_id / 32) == 0)
+ writel(mask, pmc_base + AT91_PMC_PCER);
+ else
+ return -EINVAL;
+
+ return 0;
+}
+
+static inline int at91_pmc_sam9x5_enable_periph_clock(void __iomem *pmc_base,
+ unsigned periph_id)
+{
+ u32 pcr = periph_id;
+
+ if (periph_id >= 0x80) /* 7 bits only */
+ return -EINVAL;
+
+ writel(pcr, pmc_base + AT91_PMC_PCR);
+ pcr |= readl(pmc_base + AT91_PMC_PCR) & AT91_PMC_PCR_DIV_MASK;
+ pcr |= AT91_PMC_PCR_CMD | AT91_PMC_PCR_EN;
+ writel(pcr, pmc_base + AT91_PMC_PCR);
+
+ return 0;
+}
+
+#endif
--
2.20.1
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^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH v3 06/15] ARM: at91: import lowlevel clock initialization from at91bootstrap
2019-04-01 10:18 ` [PATCH v3 06/15] ARM: at91: import lowlevel clock initialization from at91bootstrap Ahmad Fatoum
@ 2019-04-02 17:42 ` Sam Ravnborg
2019-04-02 18:44 ` Ahmad Fatoum
0 siblings, 1 reply; 43+ messages in thread
From: Sam Ravnborg @ 2019-04-02 17:42 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
Hi Ahmad.
On Mon, Apr 01, 2019 at 12:18:14PM +0200, Ahmad Fatoum wrote:
> For use by future at91 first stage bootloaders, this commit imports
> https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/pmc.c
>
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> arch/arm/mach-at91/Makefile | 1 +
> arch/arm/mach-at91/at91_pmc_ll.c | 184 ++++++++++++++++++
> arch/arm/mach-at91/include/mach/at91_pmc.h | 24 ++-
> arch/arm/mach-at91/include/mach/at91_pmc_ll.h | 78 ++++++++
> 4 files changed, 284 insertions(+), 3 deletions(-)
> create mode 100644 arch/arm/mach-at91/at91_pmc_ll.c
> create mode 100644 arch/arm/mach-at91/include/mach/at91_pmc_ll.h
>
> diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
> index d81683ac121a..91b06c085107 100644
> --- a/arch/arm/mach-at91/Makefile
> +++ b/arch/arm/mach-at91/Makefile
> @@ -1,4 +1,5 @@
> obj-y += setup.o
> +pbl-y += at91_pmc_ll.o
Will this always make my pbl image larger or do we have some linker
magic that throws away the unused code?
If the pbl image become larger then we need to add this in a conditional manner
as we cannot allow this for all at91 variants.
Sam
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^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 06/15] ARM: at91: import lowlevel clock initialization from at91bootstrap
2019-04-02 17:42 ` Sam Ravnborg
@ 2019-04-02 18:44 ` Ahmad Fatoum
2019-04-02 19:22 ` Sam Ravnborg
0 siblings, 1 reply; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-02 18:44 UTC (permalink / raw)
To: Sam Ravnborg; +Cc: barebox
Hello Sam,
On 2/4/19 19:42, Sam Ravnborg wrote:
> Hi Ahmad.
>
> On Mon, Apr 01, 2019 at 12:18:14PM +0200, Ahmad Fatoum wrote:
>> For use by future at91 first stage bootloaders, this commit imports
>> https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/pmc.c
>>
>> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
>> ---
>> arch/arm/mach-at91/Makefile | 1 +
>> arch/arm/mach-at91/at91_pmc_ll.c | 184 ++++++++++++++++++
>> arch/arm/mach-at91/include/mach/at91_pmc.h | 24 ++-
>> arch/arm/mach-at91/include/mach/at91_pmc_ll.h | 78 ++++++++
>> 4 files changed, 284 insertions(+), 3 deletions(-)
>> create mode 100644 arch/arm/mach-at91/at91_pmc_ll.c
>> create mode 100644 arch/arm/mach-at91/include/mach/at91_pmc_ll.h
>>
>> diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
>> index d81683ac121a..91b06c085107 100644
>> --- a/arch/arm/mach-at91/Makefile
>> +++ b/arch/arm/mach-at91/Makefile
>> @@ -1,4 +1,5 @@
>> obj-y += setup.o
>> +pbl-y += at91_pmc_ll.o
>
> Will this always make my pbl image larger or do we have some linker
> magic that throws away the unused code?
My understanding is that barebox instructs GCC to place each out-of-line function
into a separate section (with -ffunction-sections) and then the linker prunes all
unreferenced sections.
> If the pbl image become larger then we need to add this in a conditional manner
> as we cannot allow this for all at91 variants.
I used to have conditional function definitions in a prior version (albeit
for the SDRAM variants initialization routines) and Sascha commented that
the #ifdefery can be removed as the linker takes care of it.
>
> Sam
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 06/15] ARM: at91: import lowlevel clock initialization from at91bootstrap
2019-04-02 18:44 ` Ahmad Fatoum
@ 2019-04-02 19:22 ` Sam Ravnborg
0 siblings, 0 replies; 43+ messages in thread
From: Sam Ravnborg @ 2019-04-02 19:22 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
Hi Ahmad.
> >> @@ -1,4 +1,5 @@
> >> obj-y += setup.o
> >> +pbl-y += at91_pmc_ll.o
> >
> > Will this always make my pbl image larger or do we have some linker
> > magic that throws away the unused code?
>
> My understanding is that barebox instructs GCC to place each out-of-line function
> into a separate section (with -ffunction-sections) and then the linker prunes all
> unreferenced sections.
>
> > If the pbl image become larger then we need to add this in a conditional manner
> > as we cannot allow this for all at91 variants.
>
> I used to have conditional function definitions in a prior version (albeit
> for the SDRAM variants initialization routines) and Sascha commented that
> the #ifdefery can be removed as the linker takes care of it.
I should have known already that we used --function-sections as I worked
with this in the kernel in my former life.
Much better than ifdeffery all over the code or in Makefiles.
Sam
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^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 07/15] ARM: at91: import early_udelay from at91bootstrap
2019-04-01 10:18 [PATCH v3 00/15] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
` (5 preceding siblings ...)
2019-04-01 10:18 ` [PATCH v3 06/15] ARM: at91: import lowlevel clock initialization from at91bootstrap Ahmad Fatoum
@ 2019-04-01 10:18 ` Ahmad Fatoum
2019-04-01 10:18 ` [PATCH v3 08/15] ARM: at91: import low level DDRAMC initialization code " Ahmad Fatoum
` (8 subsequent siblings)
15 siblings, 0 replies; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-01 10:18 UTC (permalink / raw)
To: barebox; +Cc: sam
For use by the incoming at91bootstrap DDRAMC initialization code,
this commit provides an early_udelay function usable in PBL imported from
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/at91_pit.c
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/mach-at91/Makefile | 1 +
arch/arm/mach-at91/early_udelay.c | 56 +++++++++++++++++++
arch/arm/mach-at91/include/mach/at91_pmc_ll.h | 13 ++++-
.../arm/mach-at91/include/mach/early_udelay.h | 14 +++++
4 files changed, 83 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-at91/early_udelay.c
create mode 100644 arch/arm/mach-at91/include/mach/early_udelay.h
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 91b06c085107..25a7916c34e4 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,5 +1,6 @@
obj-y += setup.o
pbl-y += at91_pmc_ll.o
+pbl-$(CONFIG_CLOCKSOURCE_ATMEL_PIT) += early_udelay.o
ifeq ($(CONFIG_COMMON_CLK_OF_PROVIDER),)
obj-y += clock.o
diff --git a/arch/arm/mach-at91/early_udelay.c b/arch/arm/mach-at91/early_udelay.c
new file mode 100644
index 000000000000..632e797bebe9
--- /dev/null
+++ b/arch/arm/mach-at91/early_udelay.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: BSD-1-Clause
+/*
+ * Copyright (c) 2012, Atmel Corporation
+ */
+
+#include <mach/hardware.h>
+#include <asm/io.h>
+#include <mach/at91_pmc_ll.h>
+#include <mach/at91_pit.h>
+#include <mach/early_udelay.h>
+
+static unsigned int master_clock;
+static void __iomem *pmc, *pit;
+static bool has_h32mxdiv;
+
+/* Because the below statement is used in the function:
+ * ((MASTER_CLOCK >> 10) * usec) is used,
+ * to our 32-bit system. the argu "usec" maximum value is:
+ * supposed "MASTER_CLOCK" is 132M.
+ * 132000000 / 1024 = 128906
+ * (0xffffffff) / 128906 = 33318.
+ * So the maximum delay time is 33318 us.
+ */
+/* requires PIT to be initialized, but not the clocksource framework */
+void early_udelay(unsigned int usec)
+{
+ unsigned int delay;
+ unsigned int current;
+ unsigned int base = readl(pit + AT91_PIT_PIIR);
+
+ if (has_h32mxdiv)
+ master_clock /= 2;
+
+ delay = ((master_clock >> 10) * usec) >> 14;
+
+ do {
+ current = readl(pit + AT91_PIT_PIIR);
+ current -= base;
+ } while (current < delay);
+}
+
+void early_udelay_init(void __iomem *pmc_base,
+ void __iomem *pit_base,
+ unsigned int clock,
+ unsigned int master_clock_rate,
+ unsigned int flags)
+{
+ master_clock = master_clock_rate;
+ pmc = pmc_base;
+ pit = pit_base;
+ has_h32mxdiv = at91_pmc_check_mck_h32mxdiv(pmc, flags);
+
+ writel(AT91_PIT_PIV | AT91_PIT_PITEN, pit + AT91_PIT_MR);
+
+ at91_pmc_enable_periph_clock(pmc_base, clock);
+}
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc_ll.h b/arch/arm/mach-at91/include/mach/at91_pmc_ll.h
index eda40e8e12e7..e3d3e3ad59db 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc_ll.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc_ll.h
@@ -13,6 +13,7 @@
#define AT91_PMC_LL_FLAG_SAM9X5_PMC (1 << 0)
#define AT91_PMC_LL_FLAG_MEASURE_XTAL (1 << 1)
#define AT91_PMC_LL_FLAG_DISABLE_RC (1 << 2)
+#define AT91_PMC_LL_FLAG_H32MXDIV (1 << 3)
#define AT91_PMC_LL_AT91RM9200 (0)
#define AT91_PMC_LL_AT91SAM9260 (0)
@@ -27,7 +28,8 @@
AT91_PMC_LL_FLAG_MEASURE_XTAL)
#define AT91_PMC_LL_SAMA5D3 (AT91_PMC_LL_FLAG_SAM9X5_PMC | \
AT91_PMC_LL_FLAG_DISABLE_RC)
-#define AT91_PMC_LL_SAMA5D4 (AT91_PMC_LL_FLAG_SAM9X5_PMC)
+#define AT91_PMC_LL_SAMA5D4 (AT91_PMC_LL_FLAG_SAM9X5_PMC | \
+ AT91_PMC_LL_FLAG_H32MXDIV)
void at91_pmc_init(void __iomem *pmc_base, unsigned int flags);
void at91_pmc_cfg_mck(void __iomem *pmc_base, u32 pmc_mckr, unsigned int flags);
@@ -75,4 +77,13 @@ static inline int at91_pmc_sam9x5_enable_periph_clock(void __iomem *pmc_base,
return 0;
}
+static inline bool at91_pmc_check_mck_h32mxdiv(void __iomem *pmc_base,
+ unsigned flags)
+{
+ if (flags & AT91_PMC_LL_FLAG_H32MXDIV)
+ return readl(pmc_base + AT91_PMC_MCKR) & AT91_PMC_H32MXDIV;
+
+ return false;
+}
+
#endif
diff --git a/arch/arm/mach-at91/include/mach/early_udelay.h b/arch/arm/mach-at91/include/mach/early_udelay.h
new file mode 100644
index 000000000000..1c1b0123fee8
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/early_udelay.h
@@ -0,0 +1,14 @@
+#ifndef __EARLY_UDELAY_H__
+#define __EARLY_UDELAY_H__
+
+#include <linux/compiler.h>
+
+/* requires PIT to be initialized, but not the clocksource framework */
+void early_udelay(unsigned int usec);
+void early_udelay_init(void __iomem *pmc_base,
+ void __iomem *pit_base,
+ unsigned int clock,
+ unsigned int master_clock_rate,
+ unsigned int flags);
+
+#endif
--
2.20.1
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^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v3 08/15] ARM: at91: import low level DDRAMC initialization code from at91bootstrap
2019-04-01 10:18 [PATCH v3 00/15] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
` (6 preceding siblings ...)
2019-04-01 10:18 ` [PATCH v3 07/15] ARM: at91: import early_udelay " Ahmad Fatoum
@ 2019-04-01 10:18 ` Ahmad Fatoum
2019-04-03 7:48 ` Sascha Hauer
2019-04-01 10:18 ` [PATCH v3 09/15] ARM: at91: import lowlevel dbgu UART init " Ahmad Fatoum
` (7 subsequent siblings)
15 siblings, 1 reply; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-01 10:18 UTC (permalink / raw)
To: barebox; +Cc: sam
This commit imports DDRAMC initialization routines for use in PBL from
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/ddramc.c
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/mach-at91/Makefile | 1 +
arch/arm/mach-at91/ddramc.c | 507 +++++++++++++++++++++++
arch/arm/mach-at91/include/mach/ddramc.h | 36 ++
3 files changed, 544 insertions(+)
create mode 100644 arch/arm/mach-at91/ddramc.c
create mode 100644 arch/arm/mach-at91/include/mach/ddramc.h
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 25a7916c34e4..f4eb412a2397 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,6 +1,7 @@
obj-y += setup.o
pbl-y += at91_pmc_ll.o
pbl-$(CONFIG_CLOCKSOURCE_ATMEL_PIT) += early_udelay.o
+pbl-y += ddramc.o
ifeq ($(CONFIG_COMMON_CLK_OF_PROVIDER),)
obj-y += clock.o
diff --git a/arch/arm/mach-at91/ddramc.c b/arch/arm/mach-at91/ddramc.c
new file mode 100644
index 000000000000..a67c8266af4b
--- /dev/null
+++ b/arch/arm/mach-at91/ddramc.c
@@ -0,0 +1,507 @@
+// SPDX-License-Identifier: BSD-1-Clause
+/*
+ * Copyright (c) 2007, Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Copyright (c) 2007 Lead Tech Design <www.leadtechdesign.com>
+ */
+
+#include <linux/kconfig.h>
+#include <asm/system.h>
+#include <mach/at91_ddrsdrc.h>
+#include <mach/ddramc.h>
+#include <mach/early_udelay.h>
+
+void at91_ddram_initialize(unsigned long base_address,
+ unsigned long ram_address,
+ struct at91_ddramc_register *ddramc_config)
+{
+ unsigned long ba_offset;
+ unsigned long cr = 0;
+
+ /* compute BA[] offset according to CR configuration */
+ ba_offset = (ddramc_config->cr & AT91C_DDRC2_NC) + 9;
+ if ((ddramc_config->cr & AT91C_DDRC2_DECOD) == AT91C_DDRC2_DECOD_SEQUENTIAL)
+ ba_offset += ((ddramc_config->cr & AT91C_DDRC2_NR) >> 2) + 11;
+
+ ba_offset += (ddramc_config->mdr & AT91C_DDRC2_DBW) ? 1 : 2;
+
+ /*
+ * Step 1: Program the memory device type into the Memory Device Register
+ */
+ writel(ddramc_config->mdr, base_address + AT91C_HDDRSDRC2_MDR);
+
+ /*
+ * Step 2: Program the feature of DDR2-SDRAM device into
+ * the Timing Register, and into the Configuration Register
+ */
+ writel(ddramc_config->cr, base_address + AT91C_HDDRSDRC2_CR);
+
+ writel(ddramc_config->t0pr, base_address + AT91C_HDDRSDRC2_T0PR);
+ writel(ddramc_config->t1pr, base_address + AT91C_HDDRSDRC2_T1PR);
+ writel(ddramc_config->t2pr, base_address + AT91C_HDDRSDRC2_T2PR);
+
+ /*
+ * Step 3: An NOP command is issued to the DDR2-SDRAM
+ */
+ writel(AT91C_DDRC2_MODE_NOP_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address);
+ /* Now, clocks which drive the DDR2-SDRAM device are enabled */
+
+ /* A minimum pause wait 200 us is provided to precede any signal toggle.
+ (6 core cycles per iteration, core is at 396MHz: min 13340 loops) */
+ early_udelay(200);
+
+ /*
+ * Step 4: An NOP command is issued to the DDR2-SDRAM
+ */
+ writel(AT91C_DDRC2_MODE_NOP_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address);
+ /* Now, CKE is driven high */
+ /* wait 400 ns min */
+ early_udelay(1);
+
+ /*
+ * Step 5: An all banks precharge command is issued to the DDR2-SDRAM.
+ */
+ writel(AT91C_DDRC2_MODE_PRCGALL_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address);
+
+ /* wait 2 cycles min (of tCK) = 15 ns min */
+ early_udelay(1);
+
+ /*
+ * Step 6: An Extended Mode Register set(EMRS2) cycle is issued to chose between commercial or high
+ * temperature operations.
+ * Perform a write access to DDR2-SDRAM to acknowledge this command.
+ * The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0.
+ */
+ writel(AT91C_DDRC2_MODE_EXT_LMR_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address + (0x2 << ba_offset));
+
+ /* wait 2 cycles min (of tCK) = 15 ns min */
+ early_udelay(1);
+
+ /*
+ * Step 7: An Extended Mode Register set(EMRS3) cycle is issued
+ * to set the Extended Mode Register to "0".
+ * Perform a write access to DDR2-SDRAM to acknowledge this command.
+ * The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 1.
+ */
+ writel(AT91C_DDRC2_MODE_EXT_LMR_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address + (0x3 << ba_offset));
+
+ /* wait 2 cycles min (of tCK) = 15 ns min */
+ early_udelay(1);
+
+ /*
+ * Step 8: An Extened Mode Register set(EMRS1) cycle is issued to enable DLL,
+ * and to program D.I.C(Output Driver Impedance Control)
+ * Perform a write access to DDR2-SDRAM to acknowledge this command.
+ * The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.
+ */
+ writel(AT91C_DDRC2_MODE_EXT_LMR_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address + (0x1 << ba_offset));
+
+ /* An additional 200 cycles of clock are required for locking DLL */
+ early_udelay(1);
+
+ /*
+ * Step 9: Program DLL field into the Configuration Register to high(Enable DLL reset)
+ */
+ cr = readl(base_address + AT91C_HDDRSDRC2_CR);
+ writel(cr | AT91C_DDRC2_ENABLE_RESET_DLL, base_address + AT91C_HDDRSDRC2_CR);
+
+ /*
+ * Step 10: A Mode Register set(MRS) cycle is issied to reset DLL.
+ * Perform a write access to DDR2-SDRAM to acknowledge this command.
+ * The write address must be chosen so that BA[1:0] bits are set to 0.
+ */
+ writel(AT91C_DDRC2_MODE_LMR_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address + (0x0 << ba_offset));
+
+ /* wait 2 cycles min (of tCK) = 15 ns min */
+ early_udelay(1);
+
+ /*
+ * Step 11: An all banks precharge command is issued to the DDR2-SDRAM.
+ */
+ writel(AT91C_DDRC2_MODE_PRCGALL_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address);
+
+ /* wait 400 ns min (not needed on certain DDR2 devices) */
+ early_udelay(1);
+
+ /*
+ * Step 12: Two auto-refresh (CBR) cycles are provided.
+ * Program the auto refresh command (CBR) into the Mode Register.
+ */
+ writel(AT91C_DDRC2_MODE_RFSH_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address);
+
+ /* wait TRFC cycles min (135 ns min) extended to 400 ns */
+ early_udelay(1);
+
+ /* Set 2nd CBR */
+ writel(AT91C_DDRC2_MODE_RFSH_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address);
+
+ /* wait TRFC cycles min (135 ns min) extended to 400 ns */
+ early_udelay(1);
+
+ /*
+ * Step 13: Program DLL field into the Configuration Register to low(Disable DLL reset).
+ */
+ cr = readl(base_address + AT91C_HDDRSDRC2_CR);
+ writel(cr & ~AT91C_DDRC2_ENABLE_RESET_DLL, base_address + AT91C_HDDRSDRC2_CR);
+
+ /*
+ * Step 14: A Mode Register set (MRS) cycle is issued to program
+ * the parameters of the DDR2-SDRAM devices, in particular CAS latency,
+ * burst length and to disable DDL reset.
+ * Perform a write access to DDR2-SDRAM to acknowledge this command.
+ * The write address must be chosen so that BA[1:0] bits are set to 0.
+ */
+ writel(AT91C_DDRC2_MODE_LMR_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address + (0x0 << ba_offset));
+
+ /* wait 2 cycles min (of tCK) = 15 ns min */
+ early_udelay(1);
+
+ /*
+ * Step 15: Program OCD field into the Configuration Register
+ * to high (OCD calibration default).
+ */
+ cr = readl(base_address + AT91C_HDDRSDRC2_CR);
+ writel(cr | AT91C_DDRC2_OCD_DEFAULT, base_address + AT91C_HDDRSDRC2_CR);
+
+ /* wait 2 cycles min (of tCK) = 15 ns min */
+ early_udelay(1);
+
+ /*
+ * Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD default value.
+ * Perform a write access to DDR2-SDRAM to acknowledge this command.
+ * The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.
+ */
+ writel(AT91C_DDRC2_MODE_EXT_LMR_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address + (0x1 << ba_offset));
+
+ /* wait 2 cycles min (of tCK) = 15 ns min */
+ early_udelay(1);
+
+ /*
+ * Step 17: Program OCD field into the Configuration Register
+ * to low (OCD calibration mode exit).
+ */
+ cr = readl(base_address + AT91C_HDDRSDRC2_CR);
+ writel(cr & ~AT91C_DDRC2_OCD_DEFAULT, base_address + AT91C_HDDRSDRC2_CR);
+
+ /* wait 2 cycles min (of tCK) = 15 ns min */
+ early_udelay(1);
+
+ /*
+ * Step 18: An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit.
+ * Perform a write access to DDR2-SDRAM to acknowledge this command.
+ * The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.
+ */
+ writel(AT91C_DDRC2_MODE_EXT_LMR_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address + (0x1 << ba_offset));
+
+ /* wait 2 cycles min (of tCK) = 15 ns min */
+ early_udelay(1);
+
+ /*
+ * Step 19: A Nornal mode command is provided.
+ */
+ writel(AT91C_DDRC2_MODE_NORMAL_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address);
+
+ /*
+ * Step 20: Perform a write access to any DDR2-SDRAM address
+ */
+ writel(0, ram_address);
+
+ /*
+ * Step 21: Write the refresh rate into the count field in the Refresh Timer register.
+ */
+ writel(ddramc_config->rtr, base_address + AT91C_HDDRSDRC2_RTR);
+
+ /*
+ * Now we are ready to work on the DDRSDR
+ * wait for end of calibration
+ */
+ early_udelay(10);
+}
+
+/* This initialization sequence is sama5d3 and sama5d4 LP-DDR2 specific */
+
+void at91_lpddr2_sdram_initialize(unsigned long base_address,
+ unsigned long ram_address,
+ struct at91_ddramc_register *ddramc_config)
+{
+ unsigned long reg;
+
+ writel(ddramc_config->lpddr2_lpr, base_address + AT91C_MPDDRC_LPDDR2_LPR);
+
+ writel(ddramc_config->tim_calr, base_address + AT91C_MPDDRC_LPDDR2_TIM_CAL);
+
+ /*
+ * Step 1: Program the memory device type.
+ */
+ writel(ddramc_config->mdr, base_address + AT91C_HDDRSDRC2_MDR);
+
+ /*
+ * Step 2: Program the feature of the low-power DDR2-SDRAM device.
+ */
+ writel(ddramc_config->cr, base_address + AT91C_HDDRSDRC2_CR);
+
+ writel(ddramc_config->t0pr, base_address + AT91C_HDDRSDRC2_T0PR);
+ writel(ddramc_config->t1pr, base_address + AT91C_HDDRSDRC2_T1PR);
+ writel(ddramc_config->t2pr, base_address + AT91C_HDDRSDRC2_T2PR);
+
+ /*
+ * Step 3: A NOP command is issued to the low-power DDR2-SDRAM.
+ */
+ writel(AT91C_DDRC2_MODE_NOP_CMD, base_address + AT91C_HDDRSDRC2_MR);
+
+ /*
+ * Step 3bis: Add memory barrier then Perform a write access to
+ * any low-power DDR2-SDRAM address to acknowledge the command.
+ */
+ dmb();
+ writel(0, ram_address);
+
+ /*
+ * Step 4: A pause of at least 100 ns must be observed before
+ * a single toggle.
+ */
+ early_udelay(1);
+
+ /*
+ * Step 5: A NOP command is issued to the low-power DDR2-SDRAM.
+ */
+ writel(AT91C_DDRC2_MODE_NOP_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ dmb();
+ writel(0, ram_address);
+
+ /*
+ * Step 6: A pause of at least 200 us must be observed before a Reset
+ * Command.
+ */
+ early_udelay(200);
+
+ /*
+ * Step 7: A Reset command is issued to the low-power DDR2-SDRAM.
+ */
+ writel(AT91C_DDRC2_MRS(63) | AT91C_DDRC2_MODE_LPDDR2_CMD,
+ base_address + AT91C_HDDRSDRC2_MR);
+ dmb();
+ writel(0, ram_address);
+
+ /*
+ * Step 8: A pause of at least tINIT5 must be observed before issuing
+ * any commands.
+ */
+ early_udelay(1);
+
+ /*
+ * Step 9: A Calibration command is issued to the low-power DDR2-SDRAM.
+ */
+ reg = readl(base_address + AT91C_HDDRSDRC2_CR);
+ reg &= ~AT91C_DDRC2_ZQ;
+ reg |= AT91C_DDRC2_ZQ_RESET;
+ writel(reg, base_address + AT91C_HDDRSDRC2_CR);
+
+ writel(AT91C_DDRC2_MRS(10) | AT91C_DDRC2_MODE_LPDDR2_CMD,
+ base_address + AT91C_HDDRSDRC2_MR);
+ dmb();
+ writel(0, ram_address);
+
+ /*
+ * Step 9bis: The ZQ Calibration command is now issued.
+ * Program the type of calibration in the MPDDRC_CR: set the
+ * ZQ field to the SHORT value.
+ */
+ reg = readl(base_address + AT91C_HDDRSDRC2_CR);
+ reg &= ~AT91C_DDRC2_ZQ;
+ reg |= AT91C_DDRC2_ZQ_SHORT;
+ writel(reg, base_address + AT91C_HDDRSDRC2_CR);
+
+ /*
+ * Step 10: A Mode Register Write command with 1 to the MRS field
+ * is issued to the low-power DDR2-SDRAM.
+ */
+ writel(AT91C_DDRC2_MRS(1) | AT91C_DDRC2_MODE_LPDDR2_CMD,
+ base_address + AT91C_HDDRSDRC2_MR);
+ dmb();
+ writel(0, ram_address);
+
+ /*
+ * Step 11: A Mode Register Write command with 2 to the MRS field
+ * is issued to the low-power DDR2-SDRAM.
+ */
+ writel(AT91C_DDRC2_MRS(2) | AT91C_DDRC2_MODE_LPDDR2_CMD,
+ base_address + AT91C_HDDRSDRC2_MR);
+ dmb();
+ writel(0, ram_address);
+
+ /*
+ * Step 12: A Mode Register Write command with 3 to the MRS field
+ * is issued to the low-power DDR2-SDRAM.
+ */
+ writel(AT91C_DDRC2_MRS(3) | AT91C_DDRC2_MODE_LPDDR2_CMD,
+ base_address + AT91C_HDDRSDRC2_MR);
+ dmb();
+ writel(0, ram_address);
+
+ /*
+ * Step 13: A Mode Register Write command with 16 to the MRS field
+ * is issued to the low-power DDR2-SDRAM.
+ */
+ writel(AT91C_DDRC2_MRS(16) | AT91C_DDRC2_MODE_LPDDR2_CMD,
+ base_address + AT91C_HDDRSDRC2_MR);
+ dmb();
+ writel(0, ram_address);
+
+ /*
+ * Step 14: A Normal Mode command is provided.
+ */
+ writel(AT91C_DDRC2_MODE_NORMAL_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ dmb();
+ writel(0, ram_address);
+
+ /*
+ * Step 15: close the input buffers: error in documentation: no need.
+ */
+
+ /*
+ * Step 16: Write the refresh rate into the COUNT field in the MPDDRC
+ * Refresh Timer Register.
+ */
+ writel(ddramc_config->rtr, base_address + AT91C_HDDRSDRC2_RTR);
+
+ /*
+ * Now configure the CAL MR4 register.
+ */
+ writel(ddramc_config->cal_mr4r, base_address + AT91C_MPDDRC_LPDDR2_CAL_MR4);
+}
+
+void at91_lpddr1_sdram_initialize(unsigned long base_address,
+ unsigned long ram_address,
+ struct at91_ddramc_register *ddramc_config)
+{
+ unsigned long ba_offset;
+
+ /* Compute BA[] offset according to CR configuration */
+ ba_offset = (ddramc_config->cr & AT91C_DDRC2_NC) + 8;
+ if (!(ddramc_config->cr & AT91C_DDRC2_DECOD_INTERLEAVED))
+ ba_offset += ((ddramc_config->cr & AT91C_DDRC2_NR) >> 2) + 11;
+
+ ba_offset += (ddramc_config->mdr & AT91C_DDRC2_DBW) ? 1 : 2;
+
+ /*
+ * Step 1: Program the memory device type in the MPDDRC Memory Device Register
+ */
+ writel(ddramc_config->mdr, base_address + AT91C_HDDRSDRC2_MDR);
+
+ /*
+ * Step 2: Program the features of the low-power DDR1-SDRAM device
+ * in the MPDDRC Configuration Register and in the MPDDRC Timing
+ * Parameter 0 Register/MPDDRC Timing Parameter 1 Register.
+ */
+ writel(ddramc_config->cr, base_address + AT91C_HDDRSDRC2_CR);
+
+ writel(ddramc_config->t0pr, base_address + AT91C_HDDRSDRC2_T0PR);
+ writel(ddramc_config->t1pr, base_address + AT91C_HDDRSDRC2_T1PR);
+ writel(ddramc_config->t2pr, base_address + AT91C_HDDRSDRC2_T2PR);
+
+ /*
+ * Step 3: Program Temperature Compensated Self-refresh (TCR),
+ * Partial Array Self-refresh (PASR) and Drive Strength (DS) parameters
+ * in the MPDDRC Low-power Register.
+ */
+ writel(ddramc_config->lpr, base_address + AT91C_HDDRSDRC2_LPR);
+
+ /*
+ * Step 4: A NOP command is issued to the low-power DDR1-SDRAM.
+ * Program the NOP command in the MPDDRC Mode Register (MPDDRC_MR).
+ * The clocks which drive the low-power DDR1-SDRAM device
+ * are now enabled.
+ */
+ writel(AT91C_DDRC2_MODE_NOP_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address);
+
+ /*
+ * Step 5: A pause of at least 200 us must be observed before
+ * a signal toggle.
+ */
+ early_udelay(200);
+
+ /*
+ * Step 6: A NOP command is issued to the low-power DDR1-SDRAM.
+ * Program the NOP command in the MPDDRC_MR. calibration request is
+ * now made to the I/O pad.
+ */
+ writel(AT91C_DDRC2_MODE_NOP_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address);
+
+ /*
+ * Step 7: An All Banks Precharge command is issued
+ * to the low-power DDR1-SDRAM.
+ * Program All Banks Precharge command in the MPDDRC_MR.
+ */
+ writel(AT91C_DDRC2_MODE_PRCGALL_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address);
+
+ /*
+ * Step 8: Two auto-refresh (CBR) cycles are provided.
+ * Program the Auto Refresh command (CBR) in the MPDDRC_MR.
+ * The application must write a four to the MODE field
+ * in the MPDDRC_MR. Perform a write access to any low-power
+ * DDR1-SDRAM location twice to acknowledge these commands.
+ */
+ writel(AT91C_DDRC2_MODE_RFSH_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address);
+
+ writel(AT91C_DDRC2_MODE_RFSH_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address);
+
+ /*
+ * Step 9: An Extended Mode Register Set (EMRS) cycle is issued to
+ * program the low-power DDR1-SDRAM parameters (TCSR, PASR, DS).
+ * The application must write a five to the MODE field in the MPDDRC_MR
+ * and perform a write access to the SDRAM to acknowledge this command.
+ * The write address must be chosen so that signal BA[1] is set to 1
+ * and BA[0] is set to 0.
+ */
+ writel(AT91C_DDRC2_MODE_EXT_LMR_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address + (0x2 << ba_offset));
+
+ /*
+ * Step 10: A Mode Register Set (MRS) cycle is issued to program
+ * parameters of the low-power DDR1-SDRAM devices, in particular
+ * CAS latency.
+ * The application must write a three to the MODE field in the MPDDRC_MR
+ * and perform a write access to the SDRAM to acknowledge this command.
+ * The write address must be chosen so that signals BA[1:0] are set to 0.
+ */
+ writel(AT91C_DDRC2_MODE_LMR_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address + (0x0 << ba_offset));
+
+ /*
+ * Step 11: The application must enter Normal mode, write a zero
+ * to the MODE field in the MPDDRC_MR and perform a write access
+ * at any location in the SDRAM to acknowledge this command.
+ */
+ writel(AT91C_DDRC2_MODE_NORMAL_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address);
+
+ /*
+ * Step 12: Perform a write access to any low-power DDR1-SDRAM address.
+ */
+ writel(0, ram_address);
+
+ /*
+ * Step 14: Write the refresh rate into the COUNT field in the MPDDRC
+ * Refresh Timer Register (MPDDRC_RTR):
+ */
+ writel(ddramc_config->rtr, base_address + AT91C_HDDRSDRC2_RTR);
+}
diff --git a/arch/arm/mach-at91/include/mach/ddramc.h b/arch/arm/mach-at91/include/mach/ddramc.h
new file mode 100644
index 000000000000..5744555a17be
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/ddramc.h
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: BSD-1-Clause
+/*
+ * Copyright (c) 2006, Atmel Corporation
+ */
+#ifndef __DDRAMC_H__
+#define __DDRAMC_H__
+
+/* Note: reserved bits must always be zeroed */
+struct at91_ddramc_register {
+ unsigned long mdr;
+ unsigned long cr;
+ unsigned long rtr;
+ unsigned long t0pr;
+ unsigned long t1pr;
+ unsigned long t2pr;
+ unsigned long lpr;
+ unsigned long lpddr2_lpr;
+ unsigned long tim_calr;
+ unsigned long cal_mr4r;
+};
+
+void at91_ddram_initialize(unsigned long base_address,
+ unsigned long ram_address,
+ struct at91_ddramc_register *ddramc_config);
+
+void at91_lpddr2_sdram_initialize(unsigned long base_address,
+ unsigned long ram_address,
+ struct at91_ddramc_register *ddramc_config);
+
+
+void at91_lpddr1_sdram_initialize(unsigned long base_address,
+ unsigned long ram_address,
+ struct at91_ddramc_register *ddramc_config);
+
+
+#endif /* #ifndef __DDRAMC_H__ */
--
2.20.1
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^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH v3 08/15] ARM: at91: import low level DDRAMC initialization code from at91bootstrap
2019-04-01 10:18 ` [PATCH v3 08/15] ARM: at91: import low level DDRAMC initialization code " Ahmad Fatoum
@ 2019-04-03 7:48 ` Sascha Hauer
0 siblings, 0 replies; 43+ messages in thread
From: Sascha Hauer @ 2019-04-03 7:48 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox, sam
On Mon, Apr 01, 2019 at 12:18:16PM +0200, Ahmad Fatoum wrote:
> This commit imports DDRAMC initialization routines for use in PBL from
> https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/ddramc.c
>
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> arch/arm/mach-at91/Makefile | 1 +
> arch/arm/mach-at91/ddramc.c | 507 +++++++++++++++++++++++
> arch/arm/mach-at91/include/mach/ddramc.h | 36 ++
> 3 files changed, 544 insertions(+)
> create mode 100644 arch/arm/mach-at91/ddramc.c
> create mode 100644 arch/arm/mach-at91/include/mach/ddramc.h
>
> diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
> index 25a7916c34e4..f4eb412a2397 100644
> --- a/arch/arm/mach-at91/Makefile
> +++ b/arch/arm/mach-at91/Makefile
> @@ -1,6 +1,7 @@
> obj-y += setup.o
> pbl-y += at91_pmc_ll.o
> pbl-$(CONFIG_CLOCKSOURCE_ATMEL_PIT) += early_udelay.o
> +pbl-y += ddramc.o
>
> ifeq ($(CONFIG_COMMON_CLK_OF_PROVIDER),)
> obj-y += clock.o
> diff --git a/arch/arm/mach-at91/ddramc.c b/arch/arm/mach-at91/ddramc.c
> new file mode 100644
> index 000000000000..a67c8266af4b
> --- /dev/null
> +++ b/arch/arm/mach-at91/ddramc.c
> @@ -0,0 +1,507 @@
> +// SPDX-License-Identifier: BSD-1-Clause
> +/*
> + * Copyright (c) 2007, Stelian Pop <stelian.pop@leadtechdesign.com>
> + * Copyright (c) 2007 Lead Tech Design <www.leadtechdesign.com>
> + */
> +
> +#include <linux/kconfig.h>
> +#include <asm/system.h>
> +#include <mach/at91_ddrsdrc.h>
> +#include <mach/ddramc.h>
> +#include <mach/early_udelay.h>
> +
> +void at91_ddram_initialize(unsigned long base_address,
> + unsigned long ram_address,
> + struct at91_ddramc_register *ddramc_config)
The base_address argument should be of type void __iomem *.
Same for the other functions.
Sascha
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^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 09/15] ARM: at91: import lowlevel dbgu UART init code from at91bootstrap
2019-04-01 10:18 [PATCH v3 00/15] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
` (7 preceding siblings ...)
2019-04-01 10:18 ` [PATCH v3 08/15] ARM: at91: import low level DDRAMC initialization code " Ahmad Fatoum
@ 2019-04-01 10:18 ` Ahmad Fatoum
2019-04-01 10:18 ` [PATCH v3 10/15] images: at91: differentiate between first and second stage images Ahmad Fatoum
` (6 subsequent siblings)
15 siblings, 0 replies; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-01 10:18 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum, sam
From: Ahmad Fatoum <ahmad@a3f.at>
For use in PBL, import dbgu init code from:
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/at91_usart.c
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/mach-at91/include/mach/at91_dbgu.h | 57 ++++++++++++++++++++-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h
index 3b5948566e52..cf35a94b7540 100644
--- a/arch/arm/mach-at91/include/mach/at91_dbgu.h
+++ b/arch/arm/mach-at91/include/mach/at91_dbgu.h
@@ -5,7 +5,7 @@
* Copyright (C) SAN People
*
* Debug Unit (DBGU) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
+ * Based on AT91RM9200 datasheet revision E and SAMA5D3 datasheet revision B.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -16,9 +16,37 @@
#ifndef AT91_DBGU_H
#define AT91_DBGU_H
+#include <asm/io.h>
+
#if !defined(CONFIG_ARCH_AT91X40)
#define AT91_DBGU_CR (0x00) /* Control Register */
+#define AT91_DBGU_RSTRX (1 << 2) /* Reset Receiver */
+#define AT91_DBGU_RSTTX (1 << 3) /* Reset Transmitter */
+#define AT91_DBGU_RXEN (1 << 4) /* Receiver Enable */
+#define AT91_DBGU_RXDIS (1 << 5) /* Receiver Disable */
+#define AT91_DBGU_TXEN (1 << 6) /* Transmitter Enable */
+#define AT91_DBGU_TXDIS (1 << 7) /* Transmitter Disable */
+#define AT91_DBGU_RSTSTA (1 << 8) /* Reset Status Bits */
#define AT91_DBGU_MR (0x04) /* Mode Register */
+#define AT91_DBGU_NBSTOP_1BIT (0 << 12) /* 1 stop bit */
+#define AT91_DBGU_NBSTOP_1_5BIT (1 << 12) /* 1.5 stop bits */
+#define AT91_DBGU_NBSTOP_2BIT (2 << 12) /* 2 stop bits */
+
+#define AT91_DBGU_CHRL_5BIT (0 << 6) /* 5 bit character length */
+#define AT91_DBGU_CHRL_6BIT (1 << 6) /* 6 bit character length */
+#define AT91_DBGU_CHRL_7BIT (2 << 6) /* 7 bit character length */
+#define AT91_DBGU_CHRL_8BIT (3 << 6) /* 8 bit character length */
+
+#define AT91_DBGU_PAR_EVEN (0 << 9) /* Even Parity */
+#define AT91_DBGU_PAR_ODD (1 << 9) /* Odd Parity */
+#define AT91_DBGU_PAR_SPACE (2 << 9) /* Space: Force Parity to 0 */
+#define AT91_DBGU_PAR_MARK (3 << 9) /* Mark: Force Parity to 1 */
+#define AT91_DBGU_PAR_NONE (4 << 9) /* No Parity */
+
+#define AT91_DBGU_CHMODE_NORMAL (0 << 14) /* Normal mode */
+#define AT91_DBGU_CHMODE_AUTO (1 << 14) /* Automatic Echo */
+#define AT91_DBGU_CHMODE_LOCAL (2 << 14) /* Local Loopback */
+#define AT91_DBGU_CHMODE_REMOTE (3 << 14) /* Remote Loopback */
#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */
#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
@@ -63,4 +91,31 @@
#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_DEBUG_LL
+static inline void at91_dbgu_setup_ll(unsigned long dbgu_base, unsigned baudrate)
+{
+ writel(~0, dbgu_base + AT91_DBGU_IDR);
+
+ writel(AT91_DBGU_RSTRX
+ | AT91_DBGU_RSTTX
+ | AT91_DBGU_RXDIS
+ | AT91_DBGU_TXDIS,
+ dbgu_base + AT91_DBGU_CR);
+
+ writel(baudrate, dbgu_base + AT91_DBGU_BRGR);
+
+ writel(AT91_DBGU_PAR_NONE
+ | AT91_DBGU_CHMODE_NORMAL
+ | AT91_DBGU_CHRL_8BIT
+ | AT91_DBGU_NBSTOP_1BIT,
+ dbgu_base + AT91_DBGU_MR);
+
+ writel(AT91_DBGU_RXEN | AT91_DBGU_TXEN, dbgu_base + AT91_DBGU_CR);
+}
+#else
+static inline void at91_dbgu_setup_ll(unsigned long dbgu_base, unsigned baudrate) {}
+#endif
+#endif
+
#endif
--
2.20.1
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^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v3 10/15] images: at91: differentiate between first and second stage images
2019-04-01 10:18 [PATCH v3 00/15] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
` (8 preceding siblings ...)
2019-04-01 10:18 ` [PATCH v3 09/15] ARM: at91: import lowlevel dbgu UART init " Ahmad Fatoum
@ 2019-04-01 10:18 ` Ahmad Fatoum
2019-04-02 17:49 ` Sam Ravnborg
2019-04-01 10:18 ` [PATCH v3 11/15] ARM: at91: microchip-ksz9477-evb: use compressed DTB Ahmad Fatoum
` (5 subsequent siblings)
15 siblings, 1 reply; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-01 10:18 UTC (permalink / raw)
To: barebox; +Cc: sam
Incoming microchip-ksz9477-evb first stage will add one more entry point
for the first stage. As there is a little reason to use the same piggy
data for both images (BOOT.BIN, the first stage, is limited to 64K), have
CONFIG_AT91_LOAD_BAREBOX_SRAM decide which stage should be built.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/mach-at91/Kconfig | 2 +-
images/Makefile.at91 | 12 +++++++++---
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 8e1bf0629ab7..60f427d7d483 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -615,7 +615,7 @@ config AT91_BOOTSTRAP
select BOOTSTRAP
config AT91_LOAD_BAREBOX_SRAM
- bool "at91 load barebox in sram"
+ bool "at91 barebox image will be loaded into SRAM"
depends on SHELL_NONE || HAVE_AT91_LOAD_BAREBOX_SRAM
default y if SHELL_NONE
diff --git a/images/Makefile.at91 b/images/Makefile.at91
index acdb591d2452..3f1dd57f6c58 100644
--- a/images/Makefile.at91
+++ b/images/Makefile.at91
@@ -4,12 +4,18 @@
pblb-$(CONFIG_MACH_AT91SAM9X5EK) += start_at91sam9x5ek
FILE_barebox-at91sam9x5ek.img = start_at91sam9x5ek.pblb
-image-$(CONFIG_MACH_AT91SAM9X5EK) += barebox-at91sam9x5ek.img
+at91-barebox-$(CONFIG_MACH_AT91SAM9X5EK) += barebox-at91sam9x5ek.img
pblb-$(CONFIG_MACH_AT91SAM9263EK) += start_at91sam9263ek
FILE_barebox-at91sam9263ek.img = start_at91sam9263ek.pblb
-image-$(CONFIG_MACH_AT91SAM9263EK) += barebox-at91sam9263ek.img
+at91-barebox-$(CONFIG_MACH_AT91SAM9263EK) += barebox-at91sam9263ek.img
pblb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += start_sama5d3_xplained_ung8071
FILE_barebox-microchip-ksz9477-evb.img = start_sama5d3_xplained_ung8071.pblb
-image-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += barebox-microchip-ksz9477-evb.img
+at91-barebox-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += barebox-microchip-ksz9477-evb.img
+
+ifdef CONFIG_AT91_LOAD_BAREBOX_SRAM
+image-y += $(at91-boot-bin-y)
+else
+image-y += $(at91-barebox-y)
+endif
--
2.20.1
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^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH v3 10/15] images: at91: differentiate between first and second stage images
2019-04-01 10:18 ` [PATCH v3 10/15] images: at91: differentiate between first and second stage images Ahmad Fatoum
@ 2019-04-02 17:49 ` Sam Ravnborg
2019-04-21 9:21 ` Ahmad Fatoum
0 siblings, 1 reply; 43+ messages in thread
From: Sam Ravnborg @ 2019-04-02 17:49 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
Hi Ahmad.
On Mon, Apr 01, 2019 at 12:18:18PM +0200, Ahmad Fatoum wrote:
> Incoming microchip-ksz9477-evb first stage will add one more entry point
> for the first stage. As there is a little reason to use the same piggy
> data for both images (BOOT.BIN, the first stage, is limited to 64K), have
> CONFIG_AT91_LOAD_BAREBOX_SRAM decide which stage should be built.
>
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> arch/arm/mach-at91/Kconfig | 2 +-
> images/Makefile.at91 | 12 +++++++++---
> 2 files changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
> index 8e1bf0629ab7..60f427d7d483 100644
> --- a/arch/arm/mach-at91/Kconfig
> +++ b/arch/arm/mach-at91/Kconfig
> @@ -615,7 +615,7 @@ config AT91_BOOTSTRAP
> select BOOTSTRAP
>
> config AT91_LOAD_BAREBOX_SRAM
> - bool "at91 load barebox in sram"
> + bool "at91 barebox image will be loaded into SRAM"
> depends on SHELL_NONE || HAVE_AT91_LOAD_BAREBOX_SRAM
> default y if SHELL_NONE
>
> diff --git a/images/Makefile.at91 b/images/Makefile.at91
> index acdb591d2452..3f1dd57f6c58 100644
> --- a/images/Makefile.at91
> +++ b/images/Makefile.at91
> @@ -4,12 +4,18 @@
>
> pblb-$(CONFIG_MACH_AT91SAM9X5EK) += start_at91sam9x5ek
> FILE_barebox-at91sam9x5ek.img = start_at91sam9x5ek.pblb
> -image-$(CONFIG_MACH_AT91SAM9X5EK) += barebox-at91sam9x5ek.img
> +at91-barebox-$(CONFIG_MACH_AT91SAM9X5EK) += barebox-at91sam9x5ek.img
>
> pblb-$(CONFIG_MACH_AT91SAM9263EK) += start_at91sam9263ek
> FILE_barebox-at91sam9263ek.img = start_at91sam9263ek.pblb
> -image-$(CONFIG_MACH_AT91SAM9263EK) += barebox-at91sam9263ek.img
> +at91-barebox-$(CONFIG_MACH_AT91SAM9263EK) += barebox-at91sam9263ek.img
>
> pblb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += start_sama5d3_xplained_ung8071
> FILE_barebox-microchip-ksz9477-evb.img = start_sama5d3_xplained_ung8071.pblb
> -image-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += barebox-microchip-ksz9477-evb.img
> +at91-barebox-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += barebox-microchip-ksz9477-evb.img
> +
> +ifdef CONFIG_AT91_LOAD_BAREBOX_SRAM
> +image-y += $(at91-boot-bin-y)
> +else
> +image-y += $(at91-barebox-y)
> +endif
I cannot follow what you do in the line "image-y += $(at91-boot-bin-y)".
Could you try to elaborate.
Sam
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^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 10/15] images: at91: differentiate between first and second stage images
2019-04-02 17:49 ` Sam Ravnborg
@ 2019-04-21 9:21 ` Ahmad Fatoum
0 siblings, 0 replies; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-21 9:21 UTC (permalink / raw)
To: Sam Ravnborg; +Cc: barebox
Hello Sam,
On 2/4/19 19:49, Sam Ravnborg wrote:
> Hi Ahmad.
>
> On Mon, Apr 01, 2019 at 12:18:18PM +0200, Ahmad Fatoum wrote:
>> Incoming microchip-ksz9477-evb first stage will add one more entry point
>> for the first stage. As there is a little reason to use the same piggy
>> data for both images (BOOT.BIN, the first stage, is limited to 64K), have
>> CONFIG_AT91_LOAD_BAREBOX_SRAM decide which stage should be built.
>>
>> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
>> ---
>> arch/arm/mach-at91/Kconfig | 2 +-
>> images/Makefile.at91 | 12 +++++++++---
>> 2 files changed, 10 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
>> index 8e1bf0629ab7..60f427d7d483 100644
>> --- a/arch/arm/mach-at91/Kconfig
>> +++ b/arch/arm/mach-at91/Kconfig
>> @@ -615,7 +615,7 @@ config AT91_BOOTSTRAP
>> select BOOTSTRAP
>>
>> config AT91_LOAD_BAREBOX_SRAM
>> - bool "at91 load barebox in sram"
>> + bool "at91 barebox image will be loaded into SRAM"
>> depends on SHELL_NONE || HAVE_AT91_LOAD_BAREBOX_SRAM
>> default y if SHELL_NONE
>>
>> diff --git a/images/Makefile.at91 b/images/Makefile.at91
>> index acdb591d2452..3f1dd57f6c58 100644
>> --- a/images/Makefile.at91
>> +++ b/images/Makefile.at91
>> @@ -4,12 +4,18 @@
>>
>> pblb-$(CONFIG_MACH_AT91SAM9X5EK) += start_at91sam9x5ek
>> FILE_barebox-at91sam9x5ek.img = start_at91sam9x5ek.pblb
>> -image-$(CONFIG_MACH_AT91SAM9X5EK) += barebox-at91sam9x5ek.img
>> +at91-barebox-$(CONFIG_MACH_AT91SAM9X5EK) += barebox-at91sam9x5ek.img
>>
>> pblb-$(CONFIG_MACH_AT91SAM9263EK) += start_at91sam9263ek
>> FILE_barebox-at91sam9263ek.img = start_at91sam9263ek.pblb
>> -image-$(CONFIG_MACH_AT91SAM9263EK) += barebox-at91sam9263ek.img
>> +at91-barebox-$(CONFIG_MACH_AT91SAM9263EK) += barebox-at91sam9263ek.img
>>
>> pblb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += start_sama5d3_xplained_ung8071
>> FILE_barebox-microchip-ksz9477-evb.img = start_sama5d3_xplained_ung8071.pblb
>> -image-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += barebox-microchip-ksz9477-evb.img
>> +at91-barebox-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += barebox-microchip-ksz9477-evb.img
>> +
>> +ifdef CONFIG_AT91_LOAD_BAREBOX_SRAM
>> +image-y += $(at91-boot-bin-y)
>> +else
>> +image-y += $(at91-barebox-y)
>> +endif
>
> I cannot follow what you do in the line "image-y += $(at91-boot-bin-y)".
> Could you try to elaborate.
I got the idea from images/Makefile.omap3, there multi-images are split
into two, separated by a Kconfig option, so you can either select building
all first stage multi-image bareboxes or build all second stages. This allows
separate entry points for each and enables use of ed04a7c3c ("pbl multiimage:
Allow to check image sizes") Sascha added.
To differentiate between first and second stage I used the
CONFIG_AT91_LOAD_BAREBOX_SRAM macro. Looking at it again, at91sam9x5ek and
at91sam9263ek should've had their entry points split as well for uniformity.
I talked about this with Sascha and his opinion is that we shouldn't have
stages at all. Everything needed for low level bootstrap (SDRAM init and
MMC access) should be made to fit into the PBL instead.
That way we can rename the PBL to BOOT.BIN and use the full barebox as
second stage. This means I'll need to strip down the drivers in v4..
Cheers
Ahmad
>
> Sam
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 11/15] ARM: at91: microchip-ksz9477-evb: use compressed DTB
2019-04-01 10:18 [PATCH v3 00/15] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
` (9 preceding siblings ...)
2019-04-01 10:18 ` [PATCH v3 10/15] images: at91: differentiate between first and second stage images Ahmad Fatoum
@ 2019-04-01 10:18 ` Ahmad Fatoum
2019-04-01 10:18 ` [PATCH v3 12/15] ARM: dts: microchip-ksz9477-evb: add dummy first stage device tree Ahmad Fatoum
` (4 subsequent siblings)
15 siblings, 0 replies; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-01 10:18 UTC (permalink / raw)
To: barebox; +Cc: sam
This saves about 25K, which could be useful to fit
the incoming first stage board support into the SRAM's 64K.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/boards/microchip-ksz9477-evb/lowlevel.c | 4 ++--
arch/arm/mach-at91/Kconfig | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
index 639958a459ad..4293f8aaa57d 100644
--- a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
+++ b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
@@ -12,7 +12,7 @@
#include <mach/hardware.h>
-extern char __dtb_at91_microchip_ksz9477_evb_start[];
+extern char __dtb_z_at91_microchip_ksz9477_evb_start[];
ENTRY_FUNCTION(start_sama5d3_xplained_ung8071, r0, r1, r2)
{
@@ -22,7 +22,7 @@ ENTRY_FUNCTION(start_sama5d3_xplained_ung8071, r0, r1, r2)
arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16);
- fdt = __dtb_at91_microchip_ksz9477_evb_start + get_runtime_offset();
+ fdt = __dtb_z_at91_microchip_ksz9477_evb_start + get_runtime_offset();
barebox_arm_entry(SAMA5_DDRCS, SZ_256M, fdt);
}
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 60f427d7d483..1401b8cfc9bb 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -547,6 +547,7 @@ config MACH_MICROCHIP_KSZ9477_EVB
depends on ARCH_SAMA5D3
select OFDEVICE
select COMMON_CLK_OF_PROVIDER
+ select ARM_USE_COMPRESSED_DTB
help
Select this if you are using Microchip's EVB-KSZ9477 Evaluation Kit.
--
2.20.1
_______________________________________________
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barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v3 12/15] ARM: dts: microchip-ksz9477-evb: add dummy first stage device tree
2019-04-01 10:18 [PATCH v3 00/15] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
` (10 preceding siblings ...)
2019-04-01 10:18 ` [PATCH v3 11/15] ARM: at91: microchip-ksz9477-evb: use compressed DTB Ahmad Fatoum
@ 2019-04-01 10:18 ` Ahmad Fatoum
2019-04-01 10:18 ` [PATCH v3 13/15] ARM: at91: microchip-ksz9477-evb: implement first stage Ahmad Fatoum
` (3 subsequent siblings)
15 siblings, 0 replies; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-01 10:18 UTC (permalink / raw)
To: barebox; +Cc: sam
The existing device tree is too big for the 64K byte constrained
first stage.
Because of the size limitation it might be better to only use
the device tree for the second stage. This increases user-friendliness
by leaving space for PBL_CONSOLE.
For now provide a slightly smaller smaller *-boot-bin.dts device tree
for first stage, which can be further stripped in future commits.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
LICENSES/other/X11 | 28 +++++++++++++++++++
arch/arm/dts/Makefile | 4 ++-
.../at91-microchip-ksz9477-evb-boot-bin.dts | 13 +++++++++
3 files changed, 44 insertions(+), 1 deletion(-)
create mode 100644 LICENSES/other/X11
create mode 100644 arch/arm/dts/at91-microchip-ksz9477-evb-boot-bin.dts
diff --git a/LICENSES/other/X11 b/LICENSES/other/X11
new file mode 100644
index 000000000000..fcbafbf7dc75
--- /dev/null
+++ b/LICENSES/other/X11
@@ -0,0 +1,28 @@
+Valid-License-Identifier: X11
+SPDX-URL: https://spdx.org/licenses/X11.html
+Usage-Guide:
+ To use the X11 put the following SPDX tag/value pair into a comment
+ according to the placement guidelines in the licensing rules
+ documentation:
+ SPDX-License-Identifier: X11
+License-Text:
+
+
+X11 License
+
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the "Software"),
+to deal in the Software without restriction, including without limitation
+the rights to use, copy, modify, merge, publish, distribute, sublicense,
+and/or sell copies of the Software, and to permit persons to whom the
+Software is furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1c6129816daf..64c068334713 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -127,7 +127,9 @@ pbl-dtb-$(CONFIG_MACH_ZII_VF610_DEV) += \
vf610-zii-scu4-aib.dtb.o \
vf610-zii-spb4.dtb.o
pbl-dtb-$(CONFIG_MACH_AT91SAM9263EK_DT) += at91sam9263ek.dtb.o
-pbl-dtb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += at91-microchip-ksz9477-evb.dtb.o
+pbl-dtb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += \
+ at91-microchip-ksz9477-evb.dtb.o \
+ at91-microchip-ksz9477-evb-boot-bin.dtb.o
pbl-dtb-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek.dtb.o
pbl-dtb-$(CONFIG_MACH_XILINX_ZCU104) += zynqmp-zcu104-revA.dtb.o
diff --git a/arch/arm/dts/at91-microchip-ksz9477-evb-boot-bin.dts b/arch/arm/dts/at91-microchip-ksz9477-evb-boot-bin.dts
new file mode 100644
index 000000000000..8823204bcbc7
--- /dev/null
+++ b/arch/arm/dts/at91-microchip-ksz9477-evb-boot-bin.dts
@@ -0,0 +1,13 @@
+/*
+ * at91-microchip-ksz9477-evb-boot-bin.dts - First Stage Device Tree for EVB-KSZ9477
+ *
+ * Copyright (C) 2019 Ahmad Fatoum <a.fatoum@pengutronix.de>
+ *
+ * SPDX-License-Identifier: (GPL-2.0-only OR X11)
+ */
+#include "at91-microchip-ksz9477-evb.dts"
+
+/delete-node/ &spi1;
+/delete-node/ &macb0;
+/delete-node/ &macb1;
+/delete-node/ &pinctrl_spi_ksz;
--
2.20.1
_______________________________________________
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barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v3 13/15] ARM: at91: microchip-ksz9477-evb: implement first stage
2019-04-01 10:18 [PATCH v3 00/15] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
` (11 preceding siblings ...)
2019-04-01 10:18 ` [PATCH v3 12/15] ARM: dts: microchip-ksz9477-evb: add dummy first stage device tree Ahmad Fatoum
@ 2019-04-01 10:18 ` Ahmad Fatoum
2019-04-01 12:37 ` Roland Hieber
2019-04-03 7:58 ` Sascha Hauer
2019-04-01 10:18 ` [PATCH v3 14/15] ARM: at91: microchip-ksz9477: provide board code fallback Ahmad Fatoum
` (2 subsequent siblings)
15 siblings, 2 replies; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-01 10:18 UTC (permalink / raw)
To: barebox; +Cc: sam
This imports the low level init code from at91bootstrap
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/board/sama5d3_xplained/sama5d3_xplained.c
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
.../boards/microchip-ksz9477-evb/lowlevel.c | 208 +++++++++++++++++-
arch/arm/mach-at91/Kconfig | 2 +
arch/arm/mach-at91/include/mach/at91_pmc.h | 8 +
arch/arm/mach-at91/include/mach/sama5d3.h | 1 +
images/Makefile.at91 | 5 +
5 files changed, 220 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
index 4293f8aaa57d..cf44021bdfb7 100644
--- a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
+++ b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
@@ -1,7 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-only AND BSD-1-Clause
/*
+ * Copyright (c) 2014, Atmel Corporation
* Copyright (C) 2018 Ahmad Fatoum, Pengutronix
*
- * Under GPLv2
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <common.h>
@@ -10,18 +22,206 @@
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
-#include <mach/hardware.h>
+#include <debug_ll.h>
+#include <linux/kconfig.h>
+#include <mach/at91_dbgu.h>
+#include <mach/at91_ddrsdrc.h>
+#include <mach/at91_pmc_ll.h>
+#include <mach/at91_pio.h>
+#include <mach/at91_wdt.h>
+#include <mach/ddramc.h>
+#include <mach/early_udelay.h>
+#include <mach/gpio.h>
+#include <mach/iomux.h>
+
+/* PCK = 528MHz, MCK = 132MHz */
+#define MASTER_CLOCK 132000000
+
+#define PMC_BASE IOMEM(SAMA5D3_BASE_PMC)
+#define sama5d3_pmc_enable_periph_clock(clk) \
+ at91_pmc_enable_periph_clock(PMC_BASE, clk)
+
+#define BAUDRATE(mck, baud) \
+ ((((((mck) * 10) / ((baud) * 16)) % 10) >= 5) ? \
+ (mck / (baud * 16) + 1) : ((mck) / (baud * 16)))
+
+
+static void configure_periph_a_piob_pin(unsigned int pin)
+{
+ void __iomem *pio = IOMEM(SAMA5D3_BASE_PIOB);
+ u32 mask = pin_to_mask(pin);
+
+ at91_mux_disable_interrupt(pio, mask);
+ at91_mux_set_pullup(pio, mask, 0);
+ at91_mux_pio3_set_pulldown(pio, mask, 0);
+
+ at91_mux_pio3_set_A_periph(pio, mask);
+
+ at91_mux_gpio_disable(pio, mask);
+}
+
+static noinline void dbgu_init(void)
+{
+ sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_PIOB);
+
+ configure_periph_a_piob_pin(AT91_PIN_PB30);
+ configure_periph_a_piob_pin(AT91_PIN_PB31);
+
+ sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_DBGU);
+ at91_dbgu_setup_ll(AT91_BASE_DBGU1, BAUDRATE(MASTER_CLOCK, 115200));
+
+ putc_ll('>');
+}
+
+static void ddramc_reg_config(struct at91_ddramc_register *ddramc_config)
+{
+ ddramc_config->mdr = (AT91C_DDRC2_DBW_32_BITS
+ | AT91C_DDRC2_MD_DDR2_SDRAM);
+
+ ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9
+ | AT91C_DDRC2_NR_13
+ | AT91C_DDRC2_CAS_3
+ | AT91C_DDRC2_DISABLE_RESET_DLL
+ | AT91C_DDRC2_ENABLE_DLL
+ | AT91C_DDRC2_ENRDM_ENABLE
+ | AT91C_DDRC2_NB_BANKS_8
+ | AT91C_DDRC2_NDQS_DISABLED
+ | AT91C_DDRC2_DECOD_INTERLEAVED
+ | AT91C_DDRC2_UNAL_SUPPORTED);
+
+ /*
+ * The DDR2-SDRAM device requires a refresh every 15.625 us or 7.81 us.
+ * With a 133 MHz frequency, the refresh timer count register must to be
+ * set with (15.625 x 133 MHz) ~ 2084 i.e. 0x824
+ * or (7.81 x 133 MHz) ~ 1039 i.e. 0x40F.
+ */
+ ddramc_config->rtr = 0x40F; /* Refresh timer: 7.812us */
+
+ /* One clock cycle @ 133 MHz = 7.5 ns */
+ ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6) /* 6 * 7.5 = 45 ns */
+ | AT91C_DDRC2_TRCD_(2) /* 2 * 7.5 = 22.5 ns */
+ | AT91C_DDRC2_TWR_(2) /* 2 * 7.5 = 15 ns */
+ | AT91C_DDRC2_TRC_(8) /* 8 * 7.5 = 75 ns */
+ | AT91C_DDRC2_TRP_(2) /* 2 * 7.5 = 15 ns */
+ | AT91C_DDRC2_TRRD_(2) /* 2 * 7.5 = 15 ns */
+ | AT91C_DDRC2_TWTR_(2) /* 2 clock cycles min */
+ | AT91C_DDRC2_TMRD_(2)); /* 2 clock cycles */
+
+ ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2) /* 2 clock cycles */
+ | AT91C_DDRC2_TXSRD_(200) /* 200 clock cycles */
+ | AT91C_DDRC2_TXSNR_(19) /* 19 * 7.5 = 142.5 ns */
+ | AT91C_DDRC2_TRFC_(17)); /* 17 * 7.5 = 127.5 ns */
+
+ ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(6) /* 6 * 7.5 = 45 ns */
+ | AT91C_DDRC2_TRTP_(2) /* 2 clock cycles min */
+ | AT91C_DDRC2_TRPA_(2) /* 2 * 7.5 = 15 ns */
+ | AT91C_DDRC2_TXARDS_(8) /* = TXARD */
+ | AT91C_DDRC2_TXARD_(8)); /* MR12 = 1 */
+}
+
+static void sama5d3_ddramc_init(void)
+{
+ struct at91_ddramc_register ddramc_reg;
+ u32 reg;
+
+ ddramc_reg_config(&ddramc_reg);
+
+ /* enable ddr2 clock */
+ sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_MPDDRC);
+ at91_pmc_enable_system_clock(PMC_BASE, AT91CAP9_PMC_DDR);
+
+
+ /* Init the special register for sama5d3x */
+ /* MPDDRC DLL Slave Offset Register: DDR2 configuration */
+ reg = AT91C_MPDDRC_S0OFF_1
+ | AT91C_MPDDRC_S2OFF_1
+ | AT91C_MPDDRC_S3OFF_1;
+ writel(reg, SAMA5D3_BASE_MPDDRC + AT91C_MPDDRC_DLL_SOR);
+ /* MPDDRC DLL Master Offset Register */
+ /* write master + clk90 offset */
+ reg = AT91C_MPDDRC_MOFF_7
+ | AT91C_MPDDRC_CLK90OFF_31
+ | AT91C_MPDDRC_SELOFF_ENABLED | AT91C_MPDDRC_KEY;
+ writel(reg, SAMA5D3_BASE_MPDDRC + AT91C_MPDDRC_DLL_MOR);
+
+ /* MPDDRC I/O Calibration Register */
+ /* DDR2 RZQ = 50 Ohm */
+ /* TZQIO = 4 */
+ reg = AT91C_MPDDRC_RDIV_DDR2_RZQ_50
+ | AT91C_MPDDRC_TZQIO_4;
+ writel(reg, SAMA5D3_BASE_MPDDRC + AT91C_MPDDRC_IO_CALIBR);
+
+ /* DDRAM2 Controller initialize */
+ at91_ddram_initialize(SAMA5D3_BASE_MPDDRC, SAMA5_DDRCS, &ddramc_reg);
+}
+
+extern char __dtb_z_at91_microchip_ksz9477_evb_boot_bin_start[];
extern char __dtb_z_at91_microchip_ksz9477_evb_start[];
-ENTRY_FUNCTION(start_sama5d3_xplained_ung8071, r0, r1, r2)
+static noinline void board_init(void)
{
- void *fdt;
+ void *fdt = NULL;
+
+ at91_wdt_disable(IOMEM(SAMA5D3_BASE_WDT));
+ at91_pmc_init(PMC_BASE, AT91_PMC_LL_SAMA5D3);
+
+ /* At this stage the main oscillator
+ * is supposed to be enabled PCK = MCK = MOSC
+ */
+
+ /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
+ at91_pmc_cfg_plla(PMC_BASE, AT91_PMC3_MUL_(43) | AT91_PMC_OUT_0
+ | AT91_PMC_PLLCOUNT
+ | AT91_PMC_DIV_BYPASS,
+ AT91_PMC_LL_SAMA5D3);
+
+ /* Initialize PLLA charge pump */
+ at91_pmc_init_pll(PMC_BASE, AT91_PMC_IPLLA_3);
+
+ /* Switch PCK/MCK on Main clock output */
+ at91_pmc_cfg_mck(PMC_BASE, AT91SAM9_PMC_MDIV_4 | AT91_PMC_CSS_MAIN,
+ AT91_PMC_LL_SAMA5D3);
+
+ /* Switch PCK/MCK on PLLA output */
+ at91_pmc_cfg_mck(PMC_BASE, AT91SAM9_PMC_MDIV_4 | AT91_PMC_CSS_PLLA,
+ AT91_PMC_LL_SAMA5D3);
+
+ if (IS_ENABLED(CONFIG_DEBUG_LL))
+ dbgu_init();
+
+ early_udelay_init(PMC_BASE, IOMEM(SAMA5D3_BASE_PIT),
+ SAMA5D3_ID_PIT, MASTER_CLOCK, AT91_PMC_LL_SAMA5D3);
+
+ sama5d3_ddramc_init();
+ fdt = __dtb_z_at91_microchip_ksz9477_evb_boot_bin_start + get_runtime_offset();
+
+ barebox_arm_entry(SAMA5_DDRCS, SZ_256M, fdt);
+}
+
+ENTRY_FUNCTION(start_sama5d3_xplained_ung8071_boot_bin, r0, r1, r2)
+{
arm_cpu_lowlevel_init();
arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16);
+ relocate_to_current_adr();
+ setup_c();
+ barrier();
+
+ board_init();
+}
+
+ENTRY_FUNCTION(start_sama5d3_xplained_ung8071, r0, r1, r2)
+{
+ void *fdt;
+
+ arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16);
+
+ if (IS_ENABLED(CONFIG_DEBUG_LL))
+ dbgu_init();
+
fdt = __dtb_z_at91_microchip_ksz9477_evb_start + get_runtime_offset();
barebox_arm_entry(SAMA5_DDRCS, SZ_256M, fdt);
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 1401b8cfc9bb..e72e37c2bf9e 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -200,6 +200,7 @@ config ARCH_SAMA5D3
select SOC_SAMA5D3
select HAS_MACB
select HAVE_MACH_ARM_HEAD
+ select HAVE_AT91_LOAD_BAREBOX_SRAM
config ARCH_SAMA5D4
bool "SAMA5D4"
@@ -548,6 +549,7 @@ config MACH_MICROCHIP_KSZ9477_EVB
select OFDEVICE
select COMMON_CLK_OF_PROVIDER
select ARM_USE_COMPRESSED_DTB
+ select HAVE_AT91_BOOTSTRAP
help
Select this if you are using Microchip's EVB-KSZ9477 Evaluation Kit.
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 4d60becefbab..dfc0fa63017f 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -66,9 +66,17 @@
#define AT91_CKGR_PLLAR 0x28 /* PLL A Register */
#define AT91_CKGR_PLLBR 0x2c /* PLL B Register */
#define AT91_PMC_DIV (0xff << 0) /* Divider */
+#define AT91_PMC_DIV_BYPASS (1 << 0) /* Divider bypass */
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
+#define AT91_PMC_OUT_0 (0 << 14)
+#define AT91_PMC_OUT_1 (1 << 14)
+#define AT91_PMC_OUT_2 (2 << 14)
+#define AT91_PMC_OUT_3 (3 << 14)
#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
+#define AT91_PMC_MUL_(n) (((n) << 16) & AT91_PMC_MUL)
+#define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only]*/
+#define AT91_PMC3_MUL_(n) (((n) << 18) & AT91_PMC3_MUL)
#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
#define AT91_PMC_USBDIV_1 (0 << 28)
#define AT91_PMC_USBDIV_2 (1 << 28)
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
index f0e53610c6c0..da6e825593e6 100644
--- a/arch/arm/mach-at91/include/mach/sama5d3.h
+++ b/arch/arm/mach-at91/include/mach/sama5d3.h
@@ -87,6 +87,7 @@
#define SAMA5D3_BASE_PIOC 0xfffff600
#define SAMA5D3_BASE_PIOD 0xfffff800
#define SAMA5D3_BASE_PIOE 0xfffffa00
+#define SAMA5D3_BASE_PMC 0xfffffc00
#define SAMA5D3_BASE_MPDDRC 0xffffea00
#define SAMA5D3_BASE_HSMC 0xffffc000
#define SAMA5D3_BASE_RSTC 0xfffffe00
diff --git a/images/Makefile.at91 b/images/Makefile.at91
index 3f1dd57f6c58..3c3be0a30f66 100644
--- a/images/Makefile.at91
+++ b/images/Makefile.at91
@@ -14,6 +14,11 @@ pblb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += start_sama5d3_xplained_ung8071
FILE_barebox-microchip-ksz9477-evb.img = start_sama5d3_xplained_ung8071.pblb
at91-barebox-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += barebox-microchip-ksz9477-evb.img
+pblb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += start_sama5d3_xplained_ung8071_boot_bin
+MAX_PBL_IMAGE_SIZE_start_sama5d3_xplained_ung8071_boot_bin = 0x10000
+FILE_barebox-microchip-ksz9477-evb-boot.bin.img = start_sama5d3_xplained_ung8071_boot_bin.pblb
+at91-boot-bin-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += barebox-microchip-ksz9477-evb-boot.bin.img
+
ifdef CONFIG_AT91_LOAD_BAREBOX_SRAM
image-y += $(at91-boot-bin-y)
else
--
2.20.1
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^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH v3 13/15] ARM: at91: microchip-ksz9477-evb: implement first stage
2019-04-01 10:18 ` [PATCH v3 13/15] ARM: at91: microchip-ksz9477-evb: implement first stage Ahmad Fatoum
@ 2019-04-01 12:37 ` Roland Hieber
2019-04-01 13:37 ` Ahmad Fatoum
2019-04-03 7:58 ` Sascha Hauer
1 sibling, 1 reply; 43+ messages in thread
From: Roland Hieber @ 2019-04-01 12:37 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox, sam
On Mon, Apr 01, 2019 at 12:18:21PM +0200, Ahmad Fatoum wrote:
> This imports the low level init code from at91bootstrap
> https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/board/sama5d3_xplained/sama5d3_xplained.c
>
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> .../boards/microchip-ksz9477-evb/lowlevel.c | 208 +++++++++++++++++-
> arch/arm/mach-at91/Kconfig | 2 +
> arch/arm/mach-at91/include/mach/at91_pmc.h | 8 +
> arch/arm/mach-at91/include/mach/sama5d3.h | 1 +
> images/Makefile.at91 | 5 +
> 5 files changed, 220 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
> index 4293f8aaa57d..cf44021bdfb7 100644
> --- a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
> +++ b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
> @@ -1,7 +1,19 @@
> +// SPDX-License-Identifier: GPL-2.0-only AND BSD-1-Clause
> /*
> + * Copyright (c) 2014, Atmel Corporation
> * Copyright (C) 2018 Ahmad Fatoum, Pengutronix
> *
> - * Under GPLv2
> + *
> + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
> + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
> + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
> + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
> + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
> + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
> + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
> + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
> + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> */
Here you included the original disclaimer? For what reason? :)
- Roland
>
> #include <common.h>
> @@ -10,18 +22,206 @@
> #include <asm/barebox-arm-head.h>
> #include <asm/barebox-arm.h>
>
> -#include <mach/hardware.h>
> +#include <debug_ll.h>
> +#include <linux/kconfig.h>
> +#include <mach/at91_dbgu.h>
> +#include <mach/at91_ddrsdrc.h>
> +#include <mach/at91_pmc_ll.h>
> +#include <mach/at91_pio.h>
> +#include <mach/at91_wdt.h>
> +#include <mach/ddramc.h>
> +#include <mach/early_udelay.h>
> +#include <mach/gpio.h>
> +#include <mach/iomux.h>
> +
> +/* PCK = 528MHz, MCK = 132MHz */
> +#define MASTER_CLOCK 132000000
> +
> +#define PMC_BASE IOMEM(SAMA5D3_BASE_PMC)
> +#define sama5d3_pmc_enable_periph_clock(clk) \
> + at91_pmc_enable_periph_clock(PMC_BASE, clk)
> +
> +#define BAUDRATE(mck, baud) \
> + ((((((mck) * 10) / ((baud) * 16)) % 10) >= 5) ? \
> + (mck / (baud * 16) + 1) : ((mck) / (baud * 16)))
> +
> +
> +static void configure_periph_a_piob_pin(unsigned int pin)
> +{
> + void __iomem *pio = IOMEM(SAMA5D3_BASE_PIOB);
> + u32 mask = pin_to_mask(pin);
> +
> + at91_mux_disable_interrupt(pio, mask);
> + at91_mux_set_pullup(pio, mask, 0);
> + at91_mux_pio3_set_pulldown(pio, mask, 0);
> +
> + at91_mux_pio3_set_A_periph(pio, mask);
> +
> + at91_mux_gpio_disable(pio, mask);
> +}
> +
> +static noinline void dbgu_init(void)
> +{
> + sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_PIOB);
> +
> + configure_periph_a_piob_pin(AT91_PIN_PB30);
> + configure_periph_a_piob_pin(AT91_PIN_PB31);
> +
> + sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_DBGU);
> + at91_dbgu_setup_ll(AT91_BASE_DBGU1, BAUDRATE(MASTER_CLOCK, 115200));
> +
> + putc_ll('>');
> +}
> +
> +static void ddramc_reg_config(struct at91_ddramc_register *ddramc_config)
> +{
> + ddramc_config->mdr = (AT91C_DDRC2_DBW_32_BITS
> + | AT91C_DDRC2_MD_DDR2_SDRAM);
> +
> + ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9
> + | AT91C_DDRC2_NR_13
> + | AT91C_DDRC2_CAS_3
> + | AT91C_DDRC2_DISABLE_RESET_DLL
> + | AT91C_DDRC2_ENABLE_DLL
> + | AT91C_DDRC2_ENRDM_ENABLE
> + | AT91C_DDRC2_NB_BANKS_8
> + | AT91C_DDRC2_NDQS_DISABLED
> + | AT91C_DDRC2_DECOD_INTERLEAVED
> + | AT91C_DDRC2_UNAL_SUPPORTED);
> +
> + /*
> + * The DDR2-SDRAM device requires a refresh every 15.625 us or 7.81 us.
> + * With a 133 MHz frequency, the refresh timer count register must to be
> + * set with (15.625 x 133 MHz) ~ 2084 i.e. 0x824
> + * or (7.81 x 133 MHz) ~ 1039 i.e. 0x40F.
> + */
> + ddramc_config->rtr = 0x40F; /* Refresh timer: 7.812us */
> +
> + /* One clock cycle @ 133 MHz = 7.5 ns */
> + ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6) /* 6 * 7.5 = 45 ns */
> + | AT91C_DDRC2_TRCD_(2) /* 2 * 7.5 = 22.5 ns */
> + | AT91C_DDRC2_TWR_(2) /* 2 * 7.5 = 15 ns */
> + | AT91C_DDRC2_TRC_(8) /* 8 * 7.5 = 75 ns */
> + | AT91C_DDRC2_TRP_(2) /* 2 * 7.5 = 15 ns */
> + | AT91C_DDRC2_TRRD_(2) /* 2 * 7.5 = 15 ns */
> + | AT91C_DDRC2_TWTR_(2) /* 2 clock cycles min */
> + | AT91C_DDRC2_TMRD_(2)); /* 2 clock cycles */
> +
> + ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2) /* 2 clock cycles */
> + | AT91C_DDRC2_TXSRD_(200) /* 200 clock cycles */
> + | AT91C_DDRC2_TXSNR_(19) /* 19 * 7.5 = 142.5 ns */
> + | AT91C_DDRC2_TRFC_(17)); /* 17 * 7.5 = 127.5 ns */
> +
> + ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(6) /* 6 * 7.5 = 45 ns */
> + | AT91C_DDRC2_TRTP_(2) /* 2 clock cycles min */
> + | AT91C_DDRC2_TRPA_(2) /* 2 * 7.5 = 15 ns */
> + | AT91C_DDRC2_TXARDS_(8) /* = TXARD */
> + | AT91C_DDRC2_TXARD_(8)); /* MR12 = 1 */
> +}
> +
> +static void sama5d3_ddramc_init(void)
> +{
> + struct at91_ddramc_register ddramc_reg;
> + u32 reg;
> +
> + ddramc_reg_config(&ddramc_reg);
> +
> + /* enable ddr2 clock */
> + sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_MPDDRC);
> + at91_pmc_enable_system_clock(PMC_BASE, AT91CAP9_PMC_DDR);
> +
> +
> + /* Init the special register for sama5d3x */
> + /* MPDDRC DLL Slave Offset Register: DDR2 configuration */
> + reg = AT91C_MPDDRC_S0OFF_1
> + | AT91C_MPDDRC_S2OFF_1
> + | AT91C_MPDDRC_S3OFF_1;
> + writel(reg, SAMA5D3_BASE_MPDDRC + AT91C_MPDDRC_DLL_SOR);
>
> + /* MPDDRC DLL Master Offset Register */
> + /* write master + clk90 offset */
> + reg = AT91C_MPDDRC_MOFF_7
> + | AT91C_MPDDRC_CLK90OFF_31
> + | AT91C_MPDDRC_SELOFF_ENABLED | AT91C_MPDDRC_KEY;
> + writel(reg, SAMA5D3_BASE_MPDDRC + AT91C_MPDDRC_DLL_MOR);
> +
> + /* MPDDRC I/O Calibration Register */
> + /* DDR2 RZQ = 50 Ohm */
> + /* TZQIO = 4 */
> + reg = AT91C_MPDDRC_RDIV_DDR2_RZQ_50
> + | AT91C_MPDDRC_TZQIO_4;
> + writel(reg, SAMA5D3_BASE_MPDDRC + AT91C_MPDDRC_IO_CALIBR);
> +
> + /* DDRAM2 Controller initialize */
> + at91_ddram_initialize(SAMA5D3_BASE_MPDDRC, SAMA5_DDRCS, &ddramc_reg);
> +}
> +
> +extern char __dtb_z_at91_microchip_ksz9477_evb_boot_bin_start[];
> extern char __dtb_z_at91_microchip_ksz9477_evb_start[];
>
> -ENTRY_FUNCTION(start_sama5d3_xplained_ung8071, r0, r1, r2)
> +static noinline void board_init(void)
> {
> - void *fdt;
> + void *fdt = NULL;
> +
> + at91_wdt_disable(IOMEM(SAMA5D3_BASE_WDT));
> + at91_pmc_init(PMC_BASE, AT91_PMC_LL_SAMA5D3);
> +
> + /* At this stage the main oscillator
> + * is supposed to be enabled PCK = MCK = MOSC
> + */
> +
> + /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
> + at91_pmc_cfg_plla(PMC_BASE, AT91_PMC3_MUL_(43) | AT91_PMC_OUT_0
> + | AT91_PMC_PLLCOUNT
> + | AT91_PMC_DIV_BYPASS,
> + AT91_PMC_LL_SAMA5D3);
> +
> + /* Initialize PLLA charge pump */
> + at91_pmc_init_pll(PMC_BASE, AT91_PMC_IPLLA_3);
> +
> + /* Switch PCK/MCK on Main clock output */
> + at91_pmc_cfg_mck(PMC_BASE, AT91SAM9_PMC_MDIV_4 | AT91_PMC_CSS_MAIN,
> + AT91_PMC_LL_SAMA5D3);
> +
> + /* Switch PCK/MCK on PLLA output */
> + at91_pmc_cfg_mck(PMC_BASE, AT91SAM9_PMC_MDIV_4 | AT91_PMC_CSS_PLLA,
> + AT91_PMC_LL_SAMA5D3);
> +
> + if (IS_ENABLED(CONFIG_DEBUG_LL))
> + dbgu_init();
> +
> + early_udelay_init(PMC_BASE, IOMEM(SAMA5D3_BASE_PIT),
> + SAMA5D3_ID_PIT, MASTER_CLOCK, AT91_PMC_LL_SAMA5D3);
> +
> + sama5d3_ddramc_init();
>
> + fdt = __dtb_z_at91_microchip_ksz9477_evb_boot_bin_start + get_runtime_offset();
> +
> + barebox_arm_entry(SAMA5_DDRCS, SZ_256M, fdt);
> +}
> +
> +ENTRY_FUNCTION(start_sama5d3_xplained_ung8071_boot_bin, r0, r1, r2)
> +{
> arm_cpu_lowlevel_init();
>
> arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16);
>
> + relocate_to_current_adr();
> + setup_c();
> + barrier();
> +
> + board_init();
> +}
> +
> +ENTRY_FUNCTION(start_sama5d3_xplained_ung8071, r0, r1, r2)
> +{
> + void *fdt;
> +
> + arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16);
> +
> + if (IS_ENABLED(CONFIG_DEBUG_LL))
> + dbgu_init();
> +
> fdt = __dtb_z_at91_microchip_ksz9477_evb_start + get_runtime_offset();
>
> barebox_arm_entry(SAMA5_DDRCS, SZ_256M, fdt);
> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
> index 1401b8cfc9bb..e72e37c2bf9e 100644
> --- a/arch/arm/mach-at91/Kconfig
> +++ b/arch/arm/mach-at91/Kconfig
> @@ -200,6 +200,7 @@ config ARCH_SAMA5D3
> select SOC_SAMA5D3
> select HAS_MACB
> select HAVE_MACH_ARM_HEAD
> + select HAVE_AT91_LOAD_BAREBOX_SRAM
>
> config ARCH_SAMA5D4
> bool "SAMA5D4"
> @@ -548,6 +549,7 @@ config MACH_MICROCHIP_KSZ9477_EVB
> select OFDEVICE
> select COMMON_CLK_OF_PROVIDER
> select ARM_USE_COMPRESSED_DTB
> + select HAVE_AT91_BOOTSTRAP
> help
> Select this if you are using Microchip's EVB-KSZ9477 Evaluation Kit.
>
> diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
> index 4d60becefbab..dfc0fa63017f 100644
> --- a/arch/arm/mach-at91/include/mach/at91_pmc.h
> +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
> @@ -66,9 +66,17 @@
> #define AT91_CKGR_PLLAR 0x28 /* PLL A Register */
> #define AT91_CKGR_PLLBR 0x2c /* PLL B Register */
> #define AT91_PMC_DIV (0xff << 0) /* Divider */
> +#define AT91_PMC_DIV_BYPASS (1 << 0) /* Divider bypass */
> #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
> #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
> +#define AT91_PMC_OUT_0 (0 << 14)
> +#define AT91_PMC_OUT_1 (1 << 14)
> +#define AT91_PMC_OUT_2 (2 << 14)
> +#define AT91_PMC_OUT_3 (3 << 14)
> #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
> +#define AT91_PMC_MUL_(n) (((n) << 16) & AT91_PMC_MUL)
> +#define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only]*/
> +#define AT91_PMC3_MUL_(n) (((n) << 18) & AT91_PMC3_MUL)
> #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
> #define AT91_PMC_USBDIV_1 (0 << 28)
> #define AT91_PMC_USBDIV_2 (1 << 28)
> diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
> index f0e53610c6c0..da6e825593e6 100644
> --- a/arch/arm/mach-at91/include/mach/sama5d3.h
> +++ b/arch/arm/mach-at91/include/mach/sama5d3.h
> @@ -87,6 +87,7 @@
> #define SAMA5D3_BASE_PIOC 0xfffff600
> #define SAMA5D3_BASE_PIOD 0xfffff800
> #define SAMA5D3_BASE_PIOE 0xfffffa00
> +#define SAMA5D3_BASE_PMC 0xfffffc00
> #define SAMA5D3_BASE_MPDDRC 0xffffea00
> #define SAMA5D3_BASE_HSMC 0xffffc000
> #define SAMA5D3_BASE_RSTC 0xfffffe00
> diff --git a/images/Makefile.at91 b/images/Makefile.at91
> index 3f1dd57f6c58..3c3be0a30f66 100644
> --- a/images/Makefile.at91
> +++ b/images/Makefile.at91
> @@ -14,6 +14,11 @@ pblb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += start_sama5d3_xplained_ung8071
> FILE_barebox-microchip-ksz9477-evb.img = start_sama5d3_xplained_ung8071.pblb
> at91-barebox-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += barebox-microchip-ksz9477-evb.img
>
> +pblb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += start_sama5d3_xplained_ung8071_boot_bin
> +MAX_PBL_IMAGE_SIZE_start_sama5d3_xplained_ung8071_boot_bin = 0x10000
> +FILE_barebox-microchip-ksz9477-evb-boot.bin.img = start_sama5d3_xplained_ung8071_boot_bin.pblb
> +at91-boot-bin-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += barebox-microchip-ksz9477-evb-boot.bin.img
> +
> ifdef CONFIG_AT91_LOAD_BAREBOX_SRAM
> image-y += $(at91-boot-bin-y)
> else
> --
> 2.20.1
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
--
Roland Hieber | r.hieber@pengutronix.de |
Pengutronix e.K. | https://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim | Phone: +49-5121-206917-5086 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH v3 13/15] ARM: at91: microchip-ksz9477-evb: implement first stage
2019-04-01 12:37 ` Roland Hieber
@ 2019-04-01 13:37 ` Ahmad Fatoum
0 siblings, 0 replies; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-01 13:37 UTC (permalink / raw)
To: Roland Hieber; +Cc: barebox, sam
On 4/1/19 2:37 PM, Roland Hieber wrote:
> On Mon, Apr 01, 2019 at 12:18:21PM +0200, Ahmad Fatoum wrote:
>> This imports the low level init code from at91bootstrap
>> https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/board/sama5d3_xplained/sama5d3_xplained.c
>>
>> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
>> ---
>> .../boards/microchip-ksz9477-evb/lowlevel.c | 208 +++++++++++++++++-
>> arch/arm/mach-at91/Kconfig | 2 +
>> arch/arm/mach-at91/include/mach/at91_pmc.h | 8 +
>> arch/arm/mach-at91/include/mach/sama5d3.h | 1 +
>> images/Makefile.at91 | 5 +
>> 5 files changed, 220 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
>> index 4293f8aaa57d..cf44021bdfb7 100644
>> --- a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
>> +++ b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
>> @@ -1,7 +1,19 @@
>> +// SPDX-License-Identifier: GPL-2.0-only AND BSD-1-Clause
>> /*
>> + * Copyright (c) 2014, Atmel Corporation
>> * Copyright (C) 2018 Ahmad Fatoum, Pengutronix
>> *
>> - * Under GPLv2
>> + *
>> + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
>> + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
>> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
>> + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
>> + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
>> + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
>> + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
>> + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
>> + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
>> + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>> */
>
> Here you included the original disclaimer? For what reason? :)
Was already writing the cover letter and was too lazy to do the
git send-email spiel again.
>
> - Roland
>
>>
>> #include <common.h>
>> @@ -10,18 +22,206 @@
>> #include <asm/barebox-arm-head.h>
>> #include <asm/barebox-arm.h>
>>
>> -#include <mach/hardware.h>
>> +#include <debug_ll.h>
>> +#include <linux/kconfig.h>
>> +#include <mach/at91_dbgu.h>
>> +#include <mach/at91_ddrsdrc.h>
>> +#include <mach/at91_pmc_ll.h>
>> +#include <mach/at91_pio.h>
>> +#include <mach/at91_wdt.h>
>> +#include <mach/ddramc.h>
>> +#include <mach/early_udelay.h>
>> +#include <mach/gpio.h>
>> +#include <mach/iomux.h>
>> +
>> +/* PCK = 528MHz, MCK = 132MHz */
>> +#define MASTER_CLOCK 132000000
>> +
>> +#define PMC_BASE IOMEM(SAMA5D3_BASE_PMC)
>> +#define sama5d3_pmc_enable_periph_clock(clk) \
>> + at91_pmc_enable_periph_clock(PMC_BASE, clk)
>> +
>> +#define BAUDRATE(mck, baud) \
>> + ((((((mck) * 10) / ((baud) * 16)) % 10) >= 5) ? \
>> + (mck / (baud * 16) + 1) : ((mck) / (baud * 16)))
>> +
>> +
>> +static void configure_periph_a_piob_pin(unsigned int pin)
>> +{
>> + void __iomem *pio = IOMEM(SAMA5D3_BASE_PIOB);
>> + u32 mask = pin_to_mask(pin);
>> +
>> + at91_mux_disable_interrupt(pio, mask);
>> + at91_mux_set_pullup(pio, mask, 0);
>> + at91_mux_pio3_set_pulldown(pio, mask, 0);
>> +
>> + at91_mux_pio3_set_A_periph(pio, mask);
>> +
>> + at91_mux_gpio_disable(pio, mask);
>> +}
>> +
>> +static noinline void dbgu_init(void)
>> +{
>> + sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_PIOB);
>> +
>> + configure_periph_a_piob_pin(AT91_PIN_PB30);
>> + configure_periph_a_piob_pin(AT91_PIN_PB31);
>> +
>> + sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_DBGU);
>> + at91_dbgu_setup_ll(AT91_BASE_DBGU1, BAUDRATE(MASTER_CLOCK, 115200));
>> +
>> + putc_ll('>');
>> +}
>> +
>> +static void ddramc_reg_config(struct at91_ddramc_register *ddramc_config)
>> +{
>> + ddramc_config->mdr = (AT91C_DDRC2_DBW_32_BITS
>> + | AT91C_DDRC2_MD_DDR2_SDRAM);
>> +
>> + ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9
>> + | AT91C_DDRC2_NR_13
>> + | AT91C_DDRC2_CAS_3
>> + | AT91C_DDRC2_DISABLE_RESET_DLL
>> + | AT91C_DDRC2_ENABLE_DLL
>> + | AT91C_DDRC2_ENRDM_ENABLE
>> + | AT91C_DDRC2_NB_BANKS_8
>> + | AT91C_DDRC2_NDQS_DISABLED
>> + | AT91C_DDRC2_DECOD_INTERLEAVED
>> + | AT91C_DDRC2_UNAL_SUPPORTED);
>> +
>> + /*
>> + * The DDR2-SDRAM device requires a refresh every 15.625 us or 7.81 us.
>> + * With a 133 MHz frequency, the refresh timer count register must to be
>> + * set with (15.625 x 133 MHz) ~ 2084 i.e. 0x824
>> + * or (7.81 x 133 MHz) ~ 1039 i.e. 0x40F.
>> + */
>> + ddramc_config->rtr = 0x40F; /* Refresh timer: 7.812us */
>> +
>> + /* One clock cycle @ 133 MHz = 7.5 ns */
>> + ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6) /* 6 * 7.5 = 45 ns */
>> + | AT91C_DDRC2_TRCD_(2) /* 2 * 7.5 = 22.5 ns */
>> + | AT91C_DDRC2_TWR_(2) /* 2 * 7.5 = 15 ns */
>> + | AT91C_DDRC2_TRC_(8) /* 8 * 7.5 = 75 ns */
>> + | AT91C_DDRC2_TRP_(2) /* 2 * 7.5 = 15 ns */
>> + | AT91C_DDRC2_TRRD_(2) /* 2 * 7.5 = 15 ns */
>> + | AT91C_DDRC2_TWTR_(2) /* 2 clock cycles min */
>> + | AT91C_DDRC2_TMRD_(2)); /* 2 clock cycles */
>> +
>> + ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2) /* 2 clock cycles */
>> + | AT91C_DDRC2_TXSRD_(200) /* 200 clock cycles */
>> + | AT91C_DDRC2_TXSNR_(19) /* 19 * 7.5 = 142.5 ns */
>> + | AT91C_DDRC2_TRFC_(17)); /* 17 * 7.5 = 127.5 ns */
>> +
>> + ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(6) /* 6 * 7.5 = 45 ns */
>> + | AT91C_DDRC2_TRTP_(2) /* 2 clock cycles min */
>> + | AT91C_DDRC2_TRPA_(2) /* 2 * 7.5 = 15 ns */
>> + | AT91C_DDRC2_TXARDS_(8) /* = TXARD */
>> + | AT91C_DDRC2_TXARD_(8)); /* MR12 = 1 */
>> +}
>> +
>> +static void sama5d3_ddramc_init(void)
>> +{
>> + struct at91_ddramc_register ddramc_reg;
>> + u32 reg;
>> +
>> + ddramc_reg_config(&ddramc_reg);
>> +
>> + /* enable ddr2 clock */
>> + sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_MPDDRC);
>> + at91_pmc_enable_system_clock(PMC_BASE, AT91CAP9_PMC_DDR);
>> +
>> +
>> + /* Init the special register for sama5d3x */
>> + /* MPDDRC DLL Slave Offset Register: DDR2 configuration */
>> + reg = AT91C_MPDDRC_S0OFF_1
>> + | AT91C_MPDDRC_S2OFF_1
>> + | AT91C_MPDDRC_S3OFF_1;
>> + writel(reg, SAMA5D3_BASE_MPDDRC + AT91C_MPDDRC_DLL_SOR);
>>
>> + /* MPDDRC DLL Master Offset Register */
>> + /* write master + clk90 offset */
>> + reg = AT91C_MPDDRC_MOFF_7
>> + | AT91C_MPDDRC_CLK90OFF_31
>> + | AT91C_MPDDRC_SELOFF_ENABLED | AT91C_MPDDRC_KEY;
>> + writel(reg, SAMA5D3_BASE_MPDDRC + AT91C_MPDDRC_DLL_MOR);
>> +
>> + /* MPDDRC I/O Calibration Register */
>> + /* DDR2 RZQ = 50 Ohm */
>> + /* TZQIO = 4 */
>> + reg = AT91C_MPDDRC_RDIV_DDR2_RZQ_50
>> + | AT91C_MPDDRC_TZQIO_4;
>> + writel(reg, SAMA5D3_BASE_MPDDRC + AT91C_MPDDRC_IO_CALIBR);
>> +
>> + /* DDRAM2 Controller initialize */
>> + at91_ddram_initialize(SAMA5D3_BASE_MPDDRC, SAMA5_DDRCS, &ddramc_reg);
>> +}
>> +
>> +extern char __dtb_z_at91_microchip_ksz9477_evb_boot_bin_start[];
>> extern char __dtb_z_at91_microchip_ksz9477_evb_start[];
>>
>> -ENTRY_FUNCTION(start_sama5d3_xplained_ung8071, r0, r1, r2)
>> +static noinline void board_init(void)
>> {
>> - void *fdt;
>> + void *fdt = NULL;
>> +
>> + at91_wdt_disable(IOMEM(SAMA5D3_BASE_WDT));
>> + at91_pmc_init(PMC_BASE, AT91_PMC_LL_SAMA5D3);
>> +
>> + /* At this stage the main oscillator
>> + * is supposed to be enabled PCK = MCK = MOSC
>> + */
>> +
>> + /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
>> + at91_pmc_cfg_plla(PMC_BASE, AT91_PMC3_MUL_(43) | AT91_PMC_OUT_0
>> + | AT91_PMC_PLLCOUNT
>> + | AT91_PMC_DIV_BYPASS,
>> + AT91_PMC_LL_SAMA5D3);
>> +
>> + /* Initialize PLLA charge pump */
>> + at91_pmc_init_pll(PMC_BASE, AT91_PMC_IPLLA_3);
>> +
>> + /* Switch PCK/MCK on Main clock output */
>> + at91_pmc_cfg_mck(PMC_BASE, AT91SAM9_PMC_MDIV_4 | AT91_PMC_CSS_MAIN,
>> + AT91_PMC_LL_SAMA5D3);
>> +
>> + /* Switch PCK/MCK on PLLA output */
>> + at91_pmc_cfg_mck(PMC_BASE, AT91SAM9_PMC_MDIV_4 | AT91_PMC_CSS_PLLA,
>> + AT91_PMC_LL_SAMA5D3);
>> +
>> + if (IS_ENABLED(CONFIG_DEBUG_LL))
>> + dbgu_init();
>> +
>> + early_udelay_init(PMC_BASE, IOMEM(SAMA5D3_BASE_PIT),
>> + SAMA5D3_ID_PIT, MASTER_CLOCK, AT91_PMC_LL_SAMA5D3);
>> +
>> + sama5d3_ddramc_init();
>>
>> + fdt = __dtb_z_at91_microchip_ksz9477_evb_boot_bin_start + get_runtime_offset();
>> +
>> + barebox_arm_entry(SAMA5_DDRCS, SZ_256M, fdt);
>> +}
>> +
>> +ENTRY_FUNCTION(start_sama5d3_xplained_ung8071_boot_bin, r0, r1, r2)
>> +{
>> arm_cpu_lowlevel_init();
>>
>> arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16);
>>
>> + relocate_to_current_adr();
>> + setup_c();
>> + barrier();
>> +
>> + board_init();
>> +}
>> +
>> +ENTRY_FUNCTION(start_sama5d3_xplained_ung8071, r0, r1, r2)
>> +{
>> + void *fdt;
>> +
>> + arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16);
>> +
>> + if (IS_ENABLED(CONFIG_DEBUG_LL))
>> + dbgu_init();
>> +
>> fdt = __dtb_z_at91_microchip_ksz9477_evb_start + get_runtime_offset();
>>
>> barebox_arm_entry(SAMA5_DDRCS, SZ_256M, fdt);
>> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
>> index 1401b8cfc9bb..e72e37c2bf9e 100644
>> --- a/arch/arm/mach-at91/Kconfig
>> +++ b/arch/arm/mach-at91/Kconfig
>> @@ -200,6 +200,7 @@ config ARCH_SAMA5D3
>> select SOC_SAMA5D3
>> select HAS_MACB
>> select HAVE_MACH_ARM_HEAD
>> + select HAVE_AT91_LOAD_BAREBOX_SRAM
>>
>> config ARCH_SAMA5D4
>> bool "SAMA5D4"
>> @@ -548,6 +549,7 @@ config MACH_MICROCHIP_KSZ9477_EVB
>> select OFDEVICE
>> select COMMON_CLK_OF_PROVIDER
>> select ARM_USE_COMPRESSED_DTB
>> + select HAVE_AT91_BOOTSTRAP
>> help
>> Select this if you are using Microchip's EVB-KSZ9477 Evaluation Kit.
>>
>> diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
>> index 4d60becefbab..dfc0fa63017f 100644
>> --- a/arch/arm/mach-at91/include/mach/at91_pmc.h
>> +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
>> @@ -66,9 +66,17 @@
>> #define AT91_CKGR_PLLAR 0x28 /* PLL A Register */
>> #define AT91_CKGR_PLLBR 0x2c /* PLL B Register */
>> #define AT91_PMC_DIV (0xff << 0) /* Divider */
>> +#define AT91_PMC_DIV_BYPASS (1 << 0) /* Divider bypass */
>> #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
>> #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
>> +#define AT91_PMC_OUT_0 (0 << 14)
>> +#define AT91_PMC_OUT_1 (1 << 14)
>> +#define AT91_PMC_OUT_2 (2 << 14)
>> +#define AT91_PMC_OUT_3 (3 << 14)
>> #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
>> +#define AT91_PMC_MUL_(n) (((n) << 16) & AT91_PMC_MUL)
>> +#define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only]*/
>> +#define AT91_PMC3_MUL_(n) (((n) << 18) & AT91_PMC3_MUL)
>> #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
>> #define AT91_PMC_USBDIV_1 (0 << 28)
>> #define AT91_PMC_USBDIV_2 (1 << 28)
>> diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
>> index f0e53610c6c0..da6e825593e6 100644
>> --- a/arch/arm/mach-at91/include/mach/sama5d3.h
>> +++ b/arch/arm/mach-at91/include/mach/sama5d3.h
>> @@ -87,6 +87,7 @@
>> #define SAMA5D3_BASE_PIOC 0xfffff600
>> #define SAMA5D3_BASE_PIOD 0xfffff800
>> #define SAMA5D3_BASE_PIOE 0xfffffa00
>> +#define SAMA5D3_BASE_PMC 0xfffffc00
>> #define SAMA5D3_BASE_MPDDRC 0xffffea00
>> #define SAMA5D3_BASE_HSMC 0xffffc000
>> #define SAMA5D3_BASE_RSTC 0xfffffe00
>> diff --git a/images/Makefile.at91 b/images/Makefile.at91
>> index 3f1dd57f6c58..3c3be0a30f66 100644
>> --- a/images/Makefile.at91
>> +++ b/images/Makefile.at91
>> @@ -14,6 +14,11 @@ pblb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += start_sama5d3_xplained_ung8071
>> FILE_barebox-microchip-ksz9477-evb.img = start_sama5d3_xplained_ung8071.pblb
>> at91-barebox-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += barebox-microchip-ksz9477-evb.img
>>
>> +pblb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += start_sama5d3_xplained_ung8071_boot_bin
>> +MAX_PBL_IMAGE_SIZE_start_sama5d3_xplained_ung8071_boot_bin = 0x10000
>> +FILE_barebox-microchip-ksz9477-evb-boot.bin.img = start_sama5d3_xplained_ung8071_boot_bin.pblb
>> +at91-boot-bin-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += barebox-microchip-ksz9477-evb-boot.bin.img
>> +
>> ifdef CONFIG_AT91_LOAD_BAREBOX_SRAM
>> image-y += $(at91-boot-bin-y)
>> else
>> --
>> 2.20.1
>>
>>
>> _______________________________________________
>> barebox mailing list
>> barebox@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/barebox
>>
>
--
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Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 13/15] ARM: at91: microchip-ksz9477-evb: implement first stage
2019-04-01 10:18 ` [PATCH v3 13/15] ARM: at91: microchip-ksz9477-evb: implement first stage Ahmad Fatoum
2019-04-01 12:37 ` Roland Hieber
@ 2019-04-03 7:58 ` Sascha Hauer
1 sibling, 0 replies; 43+ messages in thread
From: Sascha Hauer @ 2019-04-03 7:58 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox, sam
On Mon, Apr 01, 2019 at 12:18:21PM +0200, Ahmad Fatoum wrote:
> This imports the low level init code from at91bootstrap
> https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/board/sama5d3_xplained/sama5d3_xplained.c
>
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> .../boards/microchip-ksz9477-evb/lowlevel.c | 208 +++++++++++++++++-
> arch/arm/mach-at91/Kconfig | 2 +
> arch/arm/mach-at91/include/mach/at91_pmc.h | 8 +
> arch/arm/mach-at91/include/mach/sama5d3.h | 1 +
> images/Makefile.at91 | 5 +
> 5 files changed, 220 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
> index 4293f8aaa57d..cf44021bdfb7 100644
> --- a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
> +++ b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
> @@ -1,7 +1,19 @@
> +// SPDX-License-Identifier: GPL-2.0-only AND BSD-1-Clause
> /*
> + * Copyright (c) 2014, Atmel Corporation
> * Copyright (C) 2018 Ahmad Fatoum, Pengutronix
> *
> - * Under GPLv2
> + *
> + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
> + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
> + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
> + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
> + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
> + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
> + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
> + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
> + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> */
>
> #include <common.h>
> @@ -10,18 +22,206 @@
> #include <asm/barebox-arm-head.h>
> #include <asm/barebox-arm.h>
>
> -#include <mach/hardware.h>
> +#include <debug_ll.h>
> +#include <linux/kconfig.h>
> +#include <mach/at91_dbgu.h>
> +#include <mach/at91_ddrsdrc.h>
> +#include <mach/at91_pmc_ll.h>
> +#include <mach/at91_pio.h>
> +#include <mach/at91_wdt.h>
> +#include <mach/ddramc.h>
> +#include <mach/early_udelay.h>
> +#include <mach/gpio.h>
> +#include <mach/iomux.h>
> +
> +/* PCK = 528MHz, MCK = 132MHz */
> +#define MASTER_CLOCK 132000000
> +
> +#define PMC_BASE IOMEM(SAMA5D3_BASE_PMC)
> +#define sama5d3_pmc_enable_periph_clock(clk) \
> + at91_pmc_enable_periph_clock(PMC_BASE, clk)
> +
> +#define BAUDRATE(mck, baud) \
> + ((((((mck) * 10) / ((baud) * 16)) % 10) >= 5) ? \
> + (mck / (baud * 16) + 1) : ((mck) / (baud * 16)))
This looks useful for others aswell. Please create a static inline function
in mach/at91_dbgu.h.h for this. While at it you could untangle the code
a little.
> +
> +
> +static void configure_periph_a_piob_pin(unsigned int pin)
> +{
> + void __iomem *pio = IOMEM(SAMA5D3_BASE_PIOB);
> + u32 mask = pin_to_mask(pin);
> +
> + at91_mux_disable_interrupt(pio, mask);
> + at91_mux_set_pullup(pio, mask, 0);
> + at91_mux_pio3_set_pulldown(pio, mask, 0);
> +
> + at91_mux_pio3_set_A_periph(pio, mask);
> +
> + at91_mux_gpio_disable(pio, mask);
> +}
Not sure where this leads, but we alredy have at91_mux_pin which could
be used for this. Would it be an option to make this available to the
pbl?
> +static void ddramc_reg_config(struct at91_ddramc_register *ddramc_config)
> +{
> + ddramc_config->mdr = (AT91C_DDRC2_DBW_32_BITS
> + | AT91C_DDRC2_MD_DDR2_SDRAM);
> +
> + ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9
> + | AT91C_DDRC2_NR_13
> + | AT91C_DDRC2_CAS_3
> + | AT91C_DDRC2_DISABLE_RESET_DLL
> + | AT91C_DDRC2_ENABLE_DLL
> + | AT91C_DDRC2_ENRDM_ENABLE
> + | AT91C_DDRC2_NB_BANKS_8
> + | AT91C_DDRC2_NDQS_DISABLED
> + | AT91C_DDRC2_DECOD_INTERLEAVED
> + | AT91C_DDRC2_UNAL_SUPPORTED);
> +
> + /*
> + * The DDR2-SDRAM device requires a refresh every 15.625 us or 7.81 us.
> + * With a 133 MHz frequency, the refresh timer count register must to be
> + * set with (15.625 x 133 MHz) ~ 2084 i.e. 0x824
> + * or (7.81 x 133 MHz) ~ 1039 i.e. 0x40F.
> + */
> + ddramc_config->rtr = 0x40F; /* Refresh timer: 7.812us */
> +
> + /* One clock cycle @ 133 MHz = 7.5 ns */
> + ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6) /* 6 * 7.5 = 45 ns */
> + | AT91C_DDRC2_TRCD_(2) /* 2 * 7.5 = 22.5 ns */
> + | AT91C_DDRC2_TWR_(2) /* 2 * 7.5 = 15 ns */
> + | AT91C_DDRC2_TRC_(8) /* 8 * 7.5 = 75 ns */
> + | AT91C_DDRC2_TRP_(2) /* 2 * 7.5 = 15 ns */
> + | AT91C_DDRC2_TRRD_(2) /* 2 * 7.5 = 15 ns */
> + | AT91C_DDRC2_TWTR_(2) /* 2 clock cycles min */
> + | AT91C_DDRC2_TMRD_(2)); /* 2 clock cycles */
> +
> + ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2) /* 2 clock cycles */
> + | AT91C_DDRC2_TXSRD_(200) /* 200 clock cycles */
> + | AT91C_DDRC2_TXSNR_(19) /* 19 * 7.5 = 142.5 ns */
> + | AT91C_DDRC2_TRFC_(17)); /* 17 * 7.5 = 127.5 ns */
> +
> + ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(6) /* 6 * 7.5 = 45 ns */
> + | AT91C_DDRC2_TRTP_(2) /* 2 clock cycles min */
> + | AT91C_DDRC2_TRPA_(2) /* 2 * 7.5 = 15 ns */
> + | AT91C_DDRC2_TXARDS_(8) /* = TXARD */
> + | AT91C_DDRC2_TXARD_(8)); /* MR12 = 1 */
> +}
Why not a static initializer?
> +
> +static void sama5d3_ddramc_init(void)
> +{
> + struct at91_ddramc_register ddramc_reg;
> + u32 reg;
> +
> + ddramc_reg_config(&ddramc_reg);
> +
> + /* enable ddr2 clock */
> + sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_MPDDRC);
> + at91_pmc_enable_system_clock(PMC_BASE, AT91CAP9_PMC_DDR);
> +
> +
> + /* Init the special register for sama5d3x */
> + /* MPDDRC DLL Slave Offset Register: DDR2 configuration */
> + reg = AT91C_MPDDRC_S0OFF_1
> + | AT91C_MPDDRC_S2OFF_1
> + | AT91C_MPDDRC_S3OFF_1;
> + writel(reg, SAMA5D3_BASE_MPDDRC + AT91C_MPDDRC_DLL_SOR);
>
> + /* MPDDRC DLL Master Offset Register */
> + /* write master + clk90 offset */
> + reg = AT91C_MPDDRC_MOFF_7
> + | AT91C_MPDDRC_CLK90OFF_31
> + | AT91C_MPDDRC_SELOFF_ENABLED | AT91C_MPDDRC_KEY;
> + writel(reg, SAMA5D3_BASE_MPDDRC + AT91C_MPDDRC_DLL_MOR);
> +
> + /* MPDDRC I/O Calibration Register */
> + /* DDR2 RZQ = 50 Ohm */
> + /* TZQIO = 4 */
> + reg = AT91C_MPDDRC_RDIV_DDR2_RZQ_50
> + | AT91C_MPDDRC_TZQIO_4;
> + writel(reg, SAMA5D3_BASE_MPDDRC + AT91C_MPDDRC_IO_CALIBR);
> +
> + /* DDRAM2 Controller initialize */
> + at91_ddram_initialize(SAMA5D3_BASE_MPDDRC, SAMA5_DDRCS, &ddramc_reg);
> +}
> +
> +extern char __dtb_z_at91_microchip_ksz9477_evb_boot_bin_start[];
> extern char __dtb_z_at91_microchip_ksz9477_evb_start[];
>
> -ENTRY_FUNCTION(start_sama5d3_xplained_ung8071, r0, r1, r2)
> +static noinline void board_init(void)
> {
> - void *fdt;
> + void *fdt = NULL;
This change looks unnecessary.
> +
> + at91_wdt_disable(IOMEM(SAMA5D3_BASE_WDT));
> + at91_pmc_init(PMC_BASE, AT91_PMC_LL_SAMA5D3);
> +
> + /* At this stage the main oscillator
> + * is supposed to be enabled PCK = MCK = MOSC
> + */
> +
> + /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
> + at91_pmc_cfg_plla(PMC_BASE, AT91_PMC3_MUL_(43) | AT91_PMC_OUT_0
> + | AT91_PMC_PLLCOUNT
> + | AT91_PMC_DIV_BYPASS,
> + AT91_PMC_LL_SAMA5D3);
> +
> + /* Initialize PLLA charge pump */
> + at91_pmc_init_pll(PMC_BASE, AT91_PMC_IPLLA_3);
> +
> + /* Switch PCK/MCK on Main clock output */
> + at91_pmc_cfg_mck(PMC_BASE, AT91SAM9_PMC_MDIV_4 | AT91_PMC_CSS_MAIN,
> + AT91_PMC_LL_SAMA5D3);
> +
> + /* Switch PCK/MCK on PLLA output */
> + at91_pmc_cfg_mck(PMC_BASE, AT91SAM9_PMC_MDIV_4 | AT91_PMC_CSS_PLLA,
> + AT91_PMC_LL_SAMA5D3);
> +
> + if (IS_ENABLED(CONFIG_DEBUG_LL))
> + dbgu_init();
> +
> + early_udelay_init(PMC_BASE, IOMEM(SAMA5D3_BASE_PIT),
> + SAMA5D3_ID_PIT, MASTER_CLOCK, AT91_PMC_LL_SAMA5D3);
> +
> + sama5d3_ddramc_init();
>
> + fdt = __dtb_z_at91_microchip_ksz9477_evb_boot_bin_start + get_runtime_offset();
You don't need get_runtime_offset() here as you already called
relocate_to_current_adr/setup_c.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 14/15] ARM: at91: microchip-ksz9477: provide board code fallback
2019-04-01 10:18 [PATCH v3 00/15] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
` (12 preceding siblings ...)
2019-04-01 10:18 ` [PATCH v3 13/15] ARM: at91: microchip-ksz9477-evb: implement first stage Ahmad Fatoum
@ 2019-04-01 10:18 ` Ahmad Fatoum
2019-04-02 18:01 ` Sam Ravnborg
2019-04-03 8:15 ` Sascha Hauer
2019-04-01 10:18 ` [PATCH v3 15/15] doc: microchip-ksz9477-evb: add documentation Ahmad Fatoum
2019-04-02 18:06 ` [PATCH v3 00/15] ARM: at91: microchip-kz9477-evb: support first stage boot Sam Ravnborg
15 siblings, 2 replies; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-01 10:18 UTC (permalink / raw)
To: barebox; +Cc: sam
The newly added device tree based first stage fails to load the second
stage from MMC, which might be in relation to a preceding atmel_mci
"command/data timeout" message.
Due to this and because it's not clear yet how viable it's to use the device
tree for the size-constrained first stage anyway, make CONFIG_OFDEVICE
configurable and provide a legacy board code based fallback whenever it's
unselected. The resulting image is 48K big with PBL_CONSOLE compared to
72K for the device tree based version without PBL_CONSOLE.
If barebox can be shrunk further and the device tree support in the
first stage was fixed, this commit could be reverted for full device
tree goodness.
The board code is a stripped down version of the sama5d3_xplained board's.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
.../arm/boards/microchip-ksz9477-evb/Makefile | 3 +
arch/arm/boards/microchip-ksz9477-evb/board.c | 127 ++++++++++++++++++
.../boards/microchip-ksz9477-evb/lowlevel.c | 3 +-
...rochip_ksz9477_evb_bootstrap_mmc_defconfig | 24 ++++
arch/arm/mach-at91/Kconfig | 14 +-
5 files changed, 167 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/boards/microchip-ksz9477-evb/board.c
create mode 100644 arch/arm/configs/microchip_ksz9477_evb_bootstrap_mmc_defconfig
diff --git a/arch/arm/boards/microchip-ksz9477-evb/Makefile b/arch/arm/boards/microchip-ksz9477-evb/Makefile
index b08c4a93ca27..8d0379a3f59f 100644
--- a/arch/arm/boards/microchip-ksz9477-evb/Makefile
+++ b/arch/arm/boards/microchip-ksz9477-evb/Makefile
@@ -1 +1,4 @@
lwl-y += lowlevel.o
+ifeq ($(CONFIG_MACH_MICROCHIP_KSZ9477_EVB_DT),)
+obj-y += board.o
+endif
diff --git a/arch/arm/boards/microchip-ksz9477-evb/board.c b/arch/arm/boards/microchip-ksz9477-evb/board.c
new file mode 100644
index 000000000000..455b9aca3ab0
--- /dev/null
+++ b/arch/arm/boards/microchip-ksz9477-evb/board.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2014 Bo Shen <voice.shen@gmail.com>
+ */
+
+#include <init.h>
+#include <mach/board.h>
+#include <mach/iomux.h>
+
+#if defined(CONFIG_NAND_ATMEL)
+static struct atmel_nand_data nand_pdata = {
+ .ale = 21,
+ .cle = 22,
+ .det_pin = -EINVAL,
+ .rdy_pin = -EINVAL,
+ .enable_pin = -EINVAL,
+ .ecc_mode = NAND_ECC_HW,
+ .has_pmecc = 1,
+ .pmecc_sector_size = 512,
+ .pmecc_corr_cap = 4,
+ .bus_width_16 = 1,
+ .on_flash_bbt = 1,
+};
+
+static struct sam9_smc_config sama5d3_xplained_nand_smc_config = {
+ .ncs_read_setup = 1,
+ .nrd_setup = 2,
+ .ncs_write_setup = 1,
+ .nwe_setup = 2,
+
+ .ncs_read_pulse = 5,
+ .nrd_pulse = 3,
+ .ncs_write_pulse = 5,
+ .nwe_pulse = 3,
+
+ .read_cycle = 8,
+ .write_cycle = 8,
+
+ .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
+ .tdf_cycles = 3,
+
+ .tclr = 3,
+ .tadl = 10,
+ .tar = 3,
+ .ocms = 0,
+ .trr = 4,
+ .twb = 5,
+ .rbnsel = 3,
+ .nfsel = 1
+};
+
+static void ek_add_device_nand(void)
+{
+ struct clk *clk = clk_get(NULL, "smc_clk");
+
+ clk_enable(clk);
+
+ /* setup bus-width (8 or 16) */
+ if (nand_pdata.bus_width_16)
+ sama5d3_xplained_nand_smc_config.mode |= AT91_SMC_DBW_16;
+ else
+ sama5d3_xplained_nand_smc_config.mode |= AT91_SMC_DBW_8;
+
+ /* configure chip-select 3 (NAND) */
+ sama5_smc_configure(0, 3, &sama5d3_xplained_nand_smc_config);
+
+ at91_add_device_nand(&nand_pdata);
+}
+#else
+static void ek_add_device_nand(void) {}
+#endif
+
+#if defined(CONFIG_MCI_ATMEL)
+/*
+ * MCI (SD/MMC)
+ */
+static struct atmel_mci_platform_data mci0_data = {
+ .bus_width = 8,
+ .detect_pin = AT91_PIN_PE0,
+ .wp_pin = -EINVAL,
+};
+
+static void ek_add_device_mci(void)
+{
+ /* MMC0 */
+ at91_add_device_mci(0, &mci0_data);
+}
+#else
+static void ek_add_device_mci(void) {}
+#endif
+
+static int sama5d3_xplained_mem_init(void)
+{
+ at91_add_device_sdram(0);
+
+ return 0;
+}
+mem_initcall(sama5d3_xplained_mem_init);
+
+static const struct devfs_partition sama5d3_xplained_nand0_partitions[] = {
+ {
+ .offset = 0x00000,
+ .size = SZ_256K,
+ .flags = DEVFS_PARTITION_FIXED,
+ .name = "at91bootstrap_raw",
+ .bbname = "at91bootstrap",
+ }, {
+ .offset = DEVFS_PARTITION_APPEND, /* 256 KiB */
+ .size = SZ_1M,
+ .flags = DEVFS_PARTITION_FIXED,
+ .name = "self_raw",
+ .bbname = "self0",
+ }, {
+ /* sentinel */
+ }
+};
+
+static int sama5d3_xplained_devices_init(void)
+{
+ ek_add_device_nand();
+ ek_add_device_mci();
+
+ devfs_create_partitions("nand0", sama5d3_xplained_nand0_partitions);
+
+ return 0;
+}
+device_initcall(sama5d3_xplained_devices_init);
diff --git a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
index cf44021bdfb7..bf9a4aed6183 100644
--- a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
+++ b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
@@ -195,7 +195,8 @@ static noinline void board_init(void)
sama5d3_ddramc_init();
- fdt = __dtb_z_at91_microchip_ksz9477_evb_boot_bin_start + get_runtime_offset();
+ if (IS_ENABLED(CONFIG_MACH_MICROCHIP_KSZ9477_EVB_DT))
+ fdt = __dtb_z_at91_microchip_ksz9477_evb_boot_bin_start + get_runtime_offset();
barebox_arm_entry(SAMA5_DDRCS, SZ_256M, fdt);
}
diff --git a/arch/arm/configs/microchip_ksz9477_evb_bootstrap_mmc_defconfig b/arch/arm/configs/microchip_ksz9477_evb_bootstrap_mmc_defconfig
new file mode 100644
index 000000000000..8af85bc10613
--- /dev/null
+++ b/arch/arm/configs/microchip_ksz9477_evb_bootstrap_mmc_defconfig
@@ -0,0 +1,24 @@
+CONFIG_ARCH_SAMA5D3=y
+CONFIG_AT91_MULTI_BOARDS=y
+CONFIG_MACH_MICROCHIP_KSZ9477_EVB=y
+CONFIG_AT91_BOOTSTRAP=y
+CONFIG_MALLOC_TLSF=y
+CONFIG_RELOCATABLE=y
+CONFIG_PROMPT="BOOT.BIN:"
+CONFIG_SHELL_NONE=y
+# CONFIG_TIMESTAMP is not set
+CONFIG_CONSOLE_SIMPLE=y
+CONFIG_PBL_CONSOLE=y
+CONFIG_DEFAULT_LOGLEVEL=6
+CONFIG_DEBUG_LL=y
+# CONFIG_SPI is not set
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+# CONFIG_MCI_WRITE is not set
+CONFIG_MCI_ATMEL=y
+CONFIG_MFD_SYSCON=y
+# CONFIG_FS_RAMFS is not set
+# CONFIG_FS_DEVFS is not set
+CONFIG_FS_FAT=y
+CONFIG_BOOTSTRAP_DEVFS=y
+CONFIG_BOOTSTRAP_DISK=y
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index e72e37c2bf9e..827b05a23496 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -18,6 +18,15 @@ config MACH_AT91SAM9263EK_DT
Enabled for at91sam9263ek - evaluation kit.
But only if we need the device tree (bootstrap do not use DT)
+config MACH_MICROCHIP_KSZ9477_EVB_DT
+ def_bool y
+ depends on MACH_MICROCHIP_KSZ9477_EVB && OFDEVICE
+ select ARM_USE_COMPRESSED_DTB
+ help
+ Enabled for Microchip KSZ9477 - evaluation kit.
+ But only if we need the device tree (bootstrap doesn't yet work with
+ DT)
+
config HAVE_AT91_SMD
bool
@@ -546,9 +555,8 @@ config MACH_AT91SAM9X5EK
config MACH_MICROCHIP_KSZ9477_EVB
bool "Microchip EVB-KSZ9477 Evaluation Kit"
depends on ARCH_SAMA5D3
- select OFDEVICE
- select COMMON_CLK_OF_PROVIDER
- select ARM_USE_COMPRESSED_DTB
+ select OFDEVICE if !AT91_LOAD_BAREBOX_SRAM
+ select COMMON_CLK_OF_PROVIDER if OFDEVICE
select HAVE_AT91_BOOTSTRAP
help
Select this if you are using Microchip's EVB-KSZ9477 Evaluation Kit.
--
2.20.1
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^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH v3 14/15] ARM: at91: microchip-ksz9477: provide board code fallback
2019-04-01 10:18 ` [PATCH v3 14/15] ARM: at91: microchip-ksz9477: provide board code fallback Ahmad Fatoum
@ 2019-04-02 18:01 ` Sam Ravnborg
2019-04-21 9:42 ` Ahmad Fatoum
2019-04-03 8:15 ` Sascha Hauer
1 sibling, 1 reply; 43+ messages in thread
From: Sam Ravnborg @ 2019-04-02 18:01 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
Hi Ahmad.
On Mon, Apr 01, 2019 at 12:18:22PM +0200, Ahmad Fatoum wrote:
> The newly added device tree based first stage fails to load the second
> stage from MMC, which might be in relation to a preceding atmel_mci
> "command/data timeout" message.
I had similar troubles with MMC on at91sam9263.
After some digging the fix was simple:
See 5feabc1e6737742f1cf6a1c41921f68b4dbb5c10 ("arm: at91: fix clock to mci1 for at91sam9263")
Maybe you are hit by something as simple as this?
> +
> +static const struct devfs_partition sama5d3_xplained_nand0_partitions[] = {
> + {
> + .offset = 0x00000,
> + .size = SZ_256K,
> + .flags = DEVFS_PARTITION_FIXED,
> + .name = "at91bootstrap_raw",
> + .bbname = "at91bootstrap",
> + },
Strange partition name now we use barebox as first stage.
> +++ b/arch/arm/configs/microchip_ksz9477_evb_bootstrap_mmc_defconfig
Naming confuses me.
Do we stick to the name "first stage" or do we use "bootstrap"?
For me they are the same, but I get confused when we use both.
Sam
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^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH v3 14/15] ARM: at91: microchip-ksz9477: provide board code fallback
2019-04-02 18:01 ` Sam Ravnborg
@ 2019-04-21 9:42 ` Ahmad Fatoum
0 siblings, 0 replies; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-21 9:42 UTC (permalink / raw)
To: Sam Ravnborg; +Cc: barebox
Hello Sam,
On 2/4/19 20:01, Sam Ravnborg wrote:
> Hi Ahmad.
>
> On Mon, Apr 01, 2019 at 12:18:22PM +0200, Ahmad Fatoum wrote:
>> The newly added device tree based first stage fails to load the second
>> stage from MMC, which might be in relation to a preceding atmel_mci
>> "command/data timeout" message.
>
> I had similar troubles with MMC on at91sam9263.
> After some digging the fix was simple:
> See 5feabc1e6737742f1cf6a1c41921f68b4dbb5c10 ("arm: at91: fix clock to mci1 for at91sam9263")
Might be clock related. But if I need to fit drivers into the PBL
as well, device tree in first-stage won't be viable anyway,
so I probably won't look further into this.
>
> Maybe you are hit by something as simple as this?
>
>> +
>> +static const struct devfs_partition sama5d3_xplained_nand0_partitions[] = {
>> + {
>> + .offset = 0x00000,
>> + .size = SZ_256K,
>> + .flags = DEVFS_PARTITION_FIXED,
>> + .name = "at91bootstrap_raw",
>> + .bbname = "at91bootstrap",
>> + },
> Strange partition name now we use barebox as first stage.
Indeed.
>
>
>> +++ b/arch/arm/configs/microchip_ksz9477_evb_bootstrap_mmc_defconfig
>
> Naming confuses me.
> Do we stick to the name "first stage" or do we use "bootstrap"?
> For me they are the same, but I get confused when we use both.
For the at91sam9261ek the bootstrap defconfig is the one defining
AT91_BOOTSTRAP, so I figured I should follow suit..
>
>
> Sam
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 14/15] ARM: at91: microchip-ksz9477: provide board code fallback
2019-04-01 10:18 ` [PATCH v3 14/15] ARM: at91: microchip-ksz9477: provide board code fallback Ahmad Fatoum
2019-04-02 18:01 ` Sam Ravnborg
@ 2019-04-03 8:15 ` Sascha Hauer
1 sibling, 0 replies; 43+ messages in thread
From: Sascha Hauer @ 2019-04-03 8:15 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox, sam
On Mon, Apr 01, 2019 at 12:18:22PM +0200, Ahmad Fatoum wrote:
> The newly added device tree based first stage fails to load the second
> stage from MMC, which might be in relation to a preceding atmel_mci
> "command/data timeout" message.
>
> Due to this and because it's not clear yet how viable it's to use the device
> tree for the size-constrained first stage anyway, make CONFIG_OFDEVICE
> configurable and provide a legacy board code based fallback whenever it's
> unselected. The resulting image is 48K big with PBL_CONSOLE compared to
> 72K for the device tree based version without PBL_CONSOLE.
So where is the size limit for this SoC?
>
> If barebox can be shrunk further and the device tree support in the
> first stage was fixed, this commit could be reverted for full device
> tree goodness.
>
> The board code is a stripped down version of the sama5d3_xplained board's.
>
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> .../arm/boards/microchip-ksz9477-evb/Makefile | 3 +
> arch/arm/boards/microchip-ksz9477-evb/board.c | 127 ++++++++++++++++++
> .../boards/microchip-ksz9477-evb/lowlevel.c | 3 +-
> ...rochip_ksz9477_evb_bootstrap_mmc_defconfig | 24 ++++
> arch/arm/mach-at91/Kconfig | 14 +-
> 5 files changed, 167 insertions(+), 4 deletions(-)
> create mode 100644 arch/arm/boards/microchip-ksz9477-evb/board.c
> create mode 100644 arch/arm/configs/microchip_ksz9477_evb_bootstrap_mmc_defconfig
I'd like to keep the number of defconfigs small, I'm not keen on adding
such a specialized defconfig.
Do we need a full barebox as first stage anyway? I made good experience
on i.MX with adding specialized lowlevel drivers for MMC and NAND.
> + .ocms = 0,
> + .trr = 4,
> + .twb = 5,
> + .rbnsel = 3,
> + .nfsel = 1
> +};
> +
> +static void ek_add_device_nand(void)
ek_?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 15/15] doc: microchip-ksz9477-evb: add documentation
2019-04-01 10:18 [PATCH v3 00/15] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
` (13 preceding siblings ...)
2019-04-01 10:18 ` [PATCH v3 14/15] ARM: at91: microchip-ksz9477: provide board code fallback Ahmad Fatoum
@ 2019-04-01 10:18 ` Ahmad Fatoum
2019-04-02 18:03 ` Sam Ravnborg
2019-04-02 18:06 ` [PATCH v3 00/15] ARM: at91: microchip-kz9477-evb: support first stage boot Sam Ravnborg
15 siblings, 1 reply; 43+ messages in thread
From: Ahmad Fatoum @ 2019-04-01 10:18 UTC (permalink / raw)
To: barebox; +Cc: sam
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
.../boards/at91/microchip-ksz9477-evb.rst | 38 ++++++++++++++++++-
1 file changed, 36 insertions(+), 2 deletions(-)
diff --git a/Documentation/boards/at91/microchip-ksz9477-evb.rst b/Documentation/boards/at91/microchip-ksz9477-evb.rst
index 4c4c4aecbfb3..2a68c2a552cd 100644
--- a/Documentation/boards/at91/microchip-ksz9477-evb.rst
+++ b/Documentation/boards/at91/microchip-ksz9477-evb.rst
@@ -1,11 +1,45 @@
Microchip KSZ 9477 Evaluation board
===================================
-This is an evaluation board for a switch that uses the at91sam9x5 CPU.
+This is an evaluation board for the KSZ9477 switch that uses the sama5d36 CPU.
The board uses Device Tree and supports multi image.
-Building barebox:
+Building barebox as second stage bootloader:
.. code-block:: sh
make ARCH=arm microchip_ksz9477_evb_defconfig
+
+There are also a separate defconfig for operating barebox as first stage
+bootloader originating from SD Card.
+This configuration doesn't yet support device-tree use as the NVM bootloader
+(SoC ROM code) requires the first stage bootloader to fit into 64K.
+
+Generally, the first stage may comes from any of the following boot
+sources (in that order):
+
+* SPI0 CS0 Flash
+* SD Card
+* NAND Flash
+* SPI0 CS1 Flash
+* I2C EEPROM
+
+After being loaded into SRAM by the NVM bootloader, the first stage does low
+level clock initialization, configuration of the DDRAM controller and
+bootstraps the second stage boot loader.
+
+SD Card Bootstrap
+-----------------
+
+For boot from SD card, barebox additionally needs to be configured as
+first stage bootloader:
+
+.. code-block:: sh
+
+ make ARCH=arm microchip_ksz9477_evb_bootstrap_mmc_defconfig
+
+The resulting barebox image must be renamed to ``BOOT.BIN``
+and located in the root directory of the first FAT16/32 partition
+on the SD Card/eMMC. After initialization, ``BOOT.BIN`` will look
+for a ``barebox.bin`` in the same directory and load and execute it
+from SDRAM.
--
2.20.1
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^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH v3 15/15] doc: microchip-ksz9477-evb: add documentation
2019-04-01 10:18 ` [PATCH v3 15/15] doc: microchip-ksz9477-evb: add documentation Ahmad Fatoum
@ 2019-04-02 18:03 ` Sam Ravnborg
0 siblings, 0 replies; 43+ messages in thread
From: Sam Ravnborg @ 2019-04-02 18:03 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
Hi Ahmad.
Thanks for adding the docs.
On Mon, Apr 01, 2019 at 12:18:23PM +0200, Ahmad Fatoum wrote:
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> .../boards/at91/microchip-ksz9477-evb.rst | 38 ++++++++++++++++++-
> 1 file changed, 36 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/boards/at91/microchip-ksz9477-evb.rst b/Documentation/boards/at91/microchip-ksz9477-evb.rst
> index 4c4c4aecbfb3..2a68c2a552cd 100644
> --- a/Documentation/boards/at91/microchip-ksz9477-evb.rst
> +++ b/Documentation/boards/at91/microchip-ksz9477-evb.rst
> @@ -1,11 +1,45 @@
> Microchip KSZ 9477 Evaluation board
> ===================================
>
> -This is an evaluation board for a switch that uses the at91sam9x5 CPU.
> +This is an evaluation board for the KSZ9477 switch that uses the sama5d36 CPU.
> The board uses Device Tree and supports multi image.
>
> -Building barebox:
> +Building barebox as second stage bootloader:
>
> .. code-block:: sh
>
> make ARCH=arm microchip_ksz9477_evb_defconfig
> +
> +There are also a separate defconfig for operating barebox as first stage
> +bootloader originating from SD Card.
> +This configuration doesn't yet support device-tree use as the NVM bootloader
> +(SoC ROM code) requires the first stage bootloader to fit into 64K.
> +
> +Generally, the first stage may comes from any of the following boot
> +sources (in that order):
> +
> +* SPI0 CS0 Flash
> +* SD Card
> +* NAND Flash
> +* SPI0 CS1 Flash
> +* I2C EEPROM
> +
> +After being loaded into SRAM by the NVM bootloader, the first stage does low
> +level clock initialization, configuration of the DDRAM controller and
> +bootstraps the second stage boot loader.
> +
> +SD Card Bootstrap
> +-----------------
> +
> +For boot from SD card, barebox additionally needs to be configured as
> +first stage bootloader:
> +
> +.. code-block:: sh
> +
> + make ARCH=arm microchip_ksz9477_evb_bootstrap_mmc_defconfig
> +
> +The resulting barebox image must be renamed to ``BOOT.BIN``
When I am away from barebox development for some weeks I always
have troubles what it the right file to use.
I suggest to use specific filename rather than the vauge "resulting
barebox image".
Sam
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^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 00/15] ARM: at91: microchip-kz9477-evb: support first stage boot
2019-04-01 10:18 [PATCH v3 00/15] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
` (14 preceding siblings ...)
2019-04-01 10:18 ` [PATCH v3 15/15] doc: microchip-ksz9477-evb: add documentation Ahmad Fatoum
@ 2019-04-02 18:06 ` Sam Ravnborg
15 siblings, 0 replies; 43+ messages in thread
From: Sam Ravnborg @ 2019-04-02 18:06 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
Hi Ahmad.
It is super that you are working on this and I hope we can have bootstrap
support for more at91 variants in the near future.
> This is (the hopefully final and bestest) v3 of a series that pulls in
> enough of at91bootstrap to make barebox usable as first stage bootloader
> for the SAMA5 family of AT91 SoCs.
Sorry for gettting back to this patch set only now.
I have been through all patches and there was a few minor
comments here and there.
Let me know if this triggers any questions.
Sam
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