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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Uma Shankar <uma.shankar@intel.com>
Cc: ville.syrjala@intel.com, intel-gfx@lists.freedesktop.org,
	dri-devel@lists.freedesktop.org, seanpaul@chromium.org,
	dcastagna@chromium.org, harry.wentland@amd.com,
	maarten.lankhorst@intel.com
Subject: Re: [v2 2/7] drm/i915: Define color lut range structure
Date: Mon, 8 Apr 2019 13:09:27 +0300	[thread overview]
Message-ID: <20190408100927.GY3888@intel.com> (raw)
In-Reply-To: <1554139811-13280-3-git-send-email-uma.shankar@intel.com>

On Mon, Apr 01, 2019 at 11:00:06PM +0530, Uma Shankar wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> This defines the color lut ranges for 10bit and multi
> segmented gamma range for ICL.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_color.c | 301 ++++++++++++++++++++++++++++++++++++-
>  1 file changed, 297 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index f2907cf..84d93ec 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -1083,9 +1083,279 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
>  	return 0;
>  }
>  
> +enum {
> +	I9XX_LUT_SIZE_8BIT = 256,
> +	I9XX_LUT_SIZE_10BIT = 129,
> +
> +	ILK_LUT_SIZE_10BIT = 1024,
> +	ILK_LUT_SIZE_12BIT = 513,
> +
> +	IVB_LUT_SIZE_SPLIT = 512,
> +
> +	CHV_LUT_SIZE_CGM_DEGAMMA = 65,
> +	CHV_LUT_SIZE_CGM_GAMMA = 257,
> +};
> +
> +#define I9XX_GAMMA_8 \
> +	{ \
> +		.flags = DRM_MODE_LUT_GAMMA, \
> +		.count = 256, \
> +		.input_bpc = 8, .output_bpc = 8, \
> +		.start = 0, .end = (1 << 8) - 1, \
> +		.min = 0, .max = (1 << 8) - 1, \
> +	}
> +
> +static const struct drm_color_lut_range i9xx_gamma_8[] = {
> +	I9XX_GAMMA_8,
> +};
> +
> +static const struct drm_color_lut_range i9xx_gamma_10_slope[] = {
> +	{
> +		.flags = (DRM_MODE_LUT_GAMMA |
> +			  DRM_MODE_LUT_INTERPOLATE |
> +			  DRM_MODE_LUT_NON_DECREASING),
> +		.count = 129,
> +		.input_bpc = 10, .output_bpc = 10,
> +		.start = 0, .end = 1 << 10,
> +		.min = 0, .max = (1 << 10) - 1,
> +	},
> +};

Step 1 should probably be to advertise these for the gamma modes we
currently have, on every platform.

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2019-04-08 10:09 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-01 17:30 [v2 0/7] Add Multi Segment Gamma Support Uma Shankar
2019-04-01 17:30 ` [v2 1/7] drm: Add gamma mode caps property Uma Shankar
2019-04-01 18:33   ` Sam Ravnborg
2019-04-08 14:45     ` Shankar, Uma
2019-04-01 17:30 ` [v2 2/7] drm/i915: Define color lut range structure Uma Shankar
2019-04-08 10:09   ` Ville Syrjälä [this message]
2019-04-08 12:28     ` Shankar, Uma
2019-04-01 17:30 ` [v2 3/7] drm: Add gamma mode property Uma Shankar
2019-04-01 18:37   ` Sam Ravnborg
2019-04-08 14:49     ` Shankar, Uma
2019-04-01 17:30 ` [v2 4/7] drm/i915/icl: Add register definitions for Multi Segmented gamma Uma Shankar
2019-04-01 17:30 ` [v2 5/7] drm/i915/icl: Add support for multi segmented gamma mode Uma Shankar
2019-04-08 10:19   ` Ville Syrjälä
2019-04-08 12:51     ` Shankar, Uma
2019-04-01 17:30 ` [v2 6/7] drm/i915: Add gamma mode caps property Uma Shankar
2019-04-01 17:30 ` [v2 7/7] drm/i915: Attach gamma mode property Uma Shankar
2019-04-02 12:44 ` ✗ Fi.CI.CHECKPATCH: warning for Add Multi Segment Gamma Support (rev2) Patchwork
2019-04-02 13:14 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-04-05 16:12 ` [Intel-gfx] [v2 0/7] Add Multi Segment Gamma Support Ville Syrjälä
2019-04-08 12:26   ` Shankar, Uma
2019-04-08 12:31     ` Ville Syrjälä
2019-04-08 14:40       ` Shankar, Uma
2019-04-08 14:57         ` [Intel-gfx] " Ville Syrjälä
2019-04-08 15:40           ` Shankar, Uma
2019-04-08 15:45             ` Ville Syrjälä
2019-04-08 15:59               ` Shankar, Uma
2019-04-08 16:07                 ` [Intel-gfx] " Ville Syrjälä
2019-04-10 13:20                   ` Shankar, Uma
2019-04-10 15:38                     ` Ville Syrjälä
2019-04-11  7:59                       ` [Intel-gfx] " Shankar, Uma

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