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From: Tony Lindgren <tony@atomide.com>
To: Dave Gerlach <d-gerlach@ti.com>
Cc: Keerthy J <j-keerthy@ti.com>,
	linux-omap@vger.kernel.org, Brad Griffis <bgriffis@ti.com>,
	linux-arm-kernel@lists.infradead.org,
	Santosh Shilimkar <ssantosh@kernel.org>
Subject: Re: [PATCH 1/2] memory: ti-emif-sram: Add ti_emif_run_hw_leveling for DDR3 hardware leveling
Date: Mon, 8 Apr 2019 12:34:00 -0700	[thread overview]
Message-ID: <20190408193400.GO49658@atomide.com> (raw)
In-Reply-To: <60a33620-0f27-37d8-5d29-dc83ab410274@ti.com>

* Dave Gerlach <d-gerlach@ti.com> [190408 18:31]:
> Tony,
> On 4/2/19 12:24 PM, Tony Lindgren wrote:
> > * Dave Gerlach <d-gerlach@ti.com> [190402 16:57]:
> > > In certain situations, such as when returning from low power modes, the
> > > EMIF must re-run hardware leveling to properly restore DDR3 access.
> > > 
> > > This is accomplished by introducing a new ti-emif-sram-pm call,
> > > ti_emif_run_hw_leveling, to check if DDR3 is in use and if so, trigger
> > > the full write and read leveling processes.
> > 
> > OK nice that you also consider devices with LPDDR2 then in case we
> > start seeing those.
> 
> Yes, LPDDR2 will work fine with these. Any thoughts on if this series should
> come through you or Santosh?

Probably best that I queue these since there's also
arch/arm/mach-omap2 code related changes.

Regards,

Tony

WARNING: multiple messages have this Message-ID (diff)
From: Tony Lindgren <tony@atomide.com>
To: Dave Gerlach <d-gerlach@ti.com>
Cc: Keerthy J <j-keerthy@ti.com>,
	linux-omap@vger.kernel.org, Brad Griffis <bgriffis@ti.com>,
	linux-arm-kernel@lists.infradead.org,
	Santosh Shilimkar <ssantosh@kernel.org>
Subject: Re: [PATCH 1/2] memory: ti-emif-sram: Add ti_emif_run_hw_leveling for DDR3 hardware leveling
Date: Mon, 8 Apr 2019 12:34:00 -0700	[thread overview]
Message-ID: <20190408193400.GO49658@atomide.com> (raw)
In-Reply-To: <60a33620-0f27-37d8-5d29-dc83ab410274@ti.com>

* Dave Gerlach <d-gerlach@ti.com> [190408 18:31]:
> Tony,
> On 4/2/19 12:24 PM, Tony Lindgren wrote:
> > * Dave Gerlach <d-gerlach@ti.com> [190402 16:57]:
> > > In certain situations, such as when returning from low power modes, the
> > > EMIF must re-run hardware leveling to properly restore DDR3 access.
> > > 
> > > This is accomplished by introducing a new ti-emif-sram-pm call,
> > > ti_emif_run_hw_leveling, to check if DDR3 is in use and if so, trigger
> > > the full write and read leveling processes.
> > 
> > OK nice that you also consider devices with LPDDR2 then in case we
> > start seeing those.
> 
> Yes, LPDDR2 will work fine with these. Any thoughts on if this series should
> come through you or Santosh?

Probably best that I queue these since there's also
arch/arm/mach-omap2 code related changes.

Regards,

Tony

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  reply	other threads:[~2019-04-08 19:34 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-02 16:57 [PATCH 0/2] ARM: OMAP2+: AM43x: Support DDR HW leveling suspend/resume Dave Gerlach
2019-04-02 16:57 ` Dave Gerlach
2019-04-02 16:57 ` [PATCH 1/2] memory: ti-emif-sram: Add ti_emif_run_hw_leveling for DDR3 hardware leveling Dave Gerlach
2019-04-02 16:57   ` Dave Gerlach
2019-04-02 17:24   ` Tony Lindgren
2019-04-02 17:24     ` Tony Lindgren
2019-04-08 18:32     ` Dave Gerlach
2019-04-08 18:32       ` Dave Gerlach
2019-04-08 19:34       ` Tony Lindgren [this message]
2019-04-08 19:34         ` Tony Lindgren
2019-04-09 15:19         ` Tony Lindgren
2019-04-09 15:19           ` Tony Lindgren
2019-04-09 15:26           ` santosh.shilimkar
2019-04-09 15:26             ` santosh.shilimkar
2019-04-09 15:33             ` Tony Lindgren
2019-04-09 15:33               ` Tony Lindgren
2019-04-02 16:57 ` [PATCH 2/2] ARM: OMAP2+: sleep43xx: Run EMIF HW leveling on resume path Dave Gerlach
2019-04-02 16:57   ` Dave Gerlach

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