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From: Bjorn Helgaas <helgaas@kernel.org>
To: "Z.q. Hou" <zhiqiang.hou@nxp.com>
Cc: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	"l.subrahmanya@mobiveil.co.in" <l.subrahmanya@mobiveil.co.in>,
	"shawnguo@kernel.org" <shawnguo@kernel.org>,
	Leo Li <leoyang.li@nxp.com>,
	"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
	"will.deacon@arm.com" <will.deacon@arm.com>,
	Mingkai Hu <mingkai.hu@nxp.com>,
	"M.h. Lian" <minghuan.lian@nxp.com>,
	Xiaowei Bao <xiaowei.bao@nxp.com>
Subject: Re: [PATCHv5 4/6] PCI: mobiveil: Add PCIe Gen4 RC driver for NXP Layerscape SoCs
Date: Fri, 12 Apr 2019 09:00:41 -0500	[thread overview]
Message-ID: <20190412140041.GA141472@google.com> (raw)
In-Reply-To: <20190412095332.41370-5-Zhiqiang.Hou@nxp.com>

On Fri, Apr 12, 2019 at 09:52:50AM +0000, Z.q. Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> This PCIe controller is based on the Mobiveil GPEX IP, which is
> compatible with the PCI Express™ Base Specification, Revision 4.0.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> ---
> V5:
>  - Corrected the subject.
>  - Corrected 2 typos.
>  - Updated the Copyright and driver description.
>  - Changed to use BIT(x) to define verious functions of register's bits.
>  - Unified the capitalization of error info.
>  - Changed the IRQ handler name to ls_pcie_g4_isr().
>  - Change 'irq' to 'IRQ' in error info.
>  - Trimmed some functions without functionality change.
> 
>  drivers/pci/controller/mobiveil/Kconfig       |  10 +
>  drivers/pci/controller/mobiveil/Makefile      |   1 +

>  .../controller/mobiveil/pci-layerscape-gen4.c | 256 ++++++++++++++++++

I would probably name this "pcie-layerscape-gen4.c" ("pcie" instead of
"pci"), since that's more typical and this really is PCIe-specific.

> +#define PCIE_PF_DBG			0x7fc
> +#define PF_DBG_LTSSM_MASK		0x3f
> +#define PF_DBG_WE			BIT(31)
> +#define PF_DBG_PABR			BIT(27)
> +
> +#define LS_PCIE_G4_LTSSM_L0		0x2d /* L0 state */

Maybe rename this and move it to make it obvious that it's related to
PF_DBG_LTSSM_MASK?

> +		dev_err(dev, "Poll PABRST&PABACT timeout.\n");

No need for punctuation at end of messages.

WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Helgaas <helgaas@kernel.org>
To: "Z.q. Hou" <zhiqiang.hou@nxp.com>
Cc: "mark.rutland@arm.com" <mark.rutland@arm.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	Xiaowei Bao <xiaowei.bao@nxp.com>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"l.subrahmanya@mobiveil.co.in" <l.subrahmanya@mobiveil.co.in>,
	"will.deacon@arm.com" <will.deacon@arm.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Leo Li <leoyang.li@nxp.com>, "M.h. Lian" <minghuan.lian@nxp.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	Mingkai Hu <mingkai.hu@nxp.com>,
	"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
	"shawnguo@kernel.org" <shawnguo@kernel.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCHv5 4/6] PCI: mobiveil: Add PCIe Gen4 RC driver for NXP Layerscape SoCs
Date: Fri, 12 Apr 2019 09:00:41 -0500	[thread overview]
Message-ID: <20190412140041.GA141472@google.com> (raw)
In-Reply-To: <20190412095332.41370-5-Zhiqiang.Hou@nxp.com>

On Fri, Apr 12, 2019 at 09:52:50AM +0000, Z.q. Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> This PCIe controller is based on the Mobiveil GPEX IP, which is
> compatible with the PCI Express™ Base Specification, Revision 4.0.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> ---
> V5:
>  - Corrected the subject.
>  - Corrected 2 typos.
>  - Updated the Copyright and driver description.
>  - Changed to use BIT(x) to define verious functions of register's bits.
>  - Unified the capitalization of error info.
>  - Changed the IRQ handler name to ls_pcie_g4_isr().
>  - Change 'irq' to 'IRQ' in error info.
>  - Trimmed some functions without functionality change.
> 
>  drivers/pci/controller/mobiveil/Kconfig       |  10 +
>  drivers/pci/controller/mobiveil/Makefile      |   1 +

>  .../controller/mobiveil/pci-layerscape-gen4.c | 256 ++++++++++++++++++

I would probably name this "pcie-layerscape-gen4.c" ("pcie" instead of
"pci"), since that's more typical and this really is PCIe-specific.

> +#define PCIE_PF_DBG			0x7fc
> +#define PF_DBG_LTSSM_MASK		0x3f
> +#define PF_DBG_WE			BIT(31)
> +#define PF_DBG_PABR			BIT(27)
> +
> +#define LS_PCIE_G4_LTSSM_L0		0x2d /* L0 state */

Maybe rename this and move it to make it obvious that it's related to
PF_DBG_LTSSM_MASK?

> +		dev_err(dev, "Poll PABRST&PABACT timeout.\n");

No need for punctuation at end of messages.

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  reply	other threads:[~2019-04-12 14:00 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-12  9:52 [PATCHv5 0/6] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Z.q. Hou
2019-04-12  9:52 ` Z.q. Hou
2019-04-12  9:52 ` [PATCHv5 1/6] PCI: mobiveil: Refactor Mobiveil PCIe Host Bridge IP driver Z.q. Hou
2019-04-12  9:52   ` Z.q. Hou
2019-04-12 14:39   ` Arnd Bergmann
2019-04-12 14:39     ` Arnd Bergmann
2019-04-12 14:39     ` Arnd Bergmann
2019-04-30  0:23     ` [EXT] " Z.q. Hou
2019-04-30  0:23       ` Z.q. Hou
2019-04-30  0:23       ` Z.q. Hou
2019-04-24  5:35   ` Subrahmanya Lingappa
2019-04-24  5:35     ` Subrahmanya Lingappa
2019-04-30  1:12     ` [EXT] " Z.q. Hou
2019-04-30  1:12       ` Z.q. Hou
2019-04-12  9:52 ` [PATCHv5 2/6] PCI: mobiveil: Make mobiveil_host_init() can be used to re-init host Z.q. Hou
2019-04-12  9:52   ` Z.q. Hou
2019-04-12  9:52 ` [PATCHv5 3/6] dt-bindings: PCI: Add NXP Layerscape SoCs PCIe Gen4 controller Z.q. Hou
2019-04-12  9:52   ` Z.q. Hou
2019-04-12  9:52 ` [PATCHv5 4/6] PCI: mobiveil: Add PCIe Gen4 RC driver for NXP Layerscape SoCs Z.q. Hou
2019-04-12  9:52   ` Z.q. Hou
2019-04-12 14:00   ` Bjorn Helgaas [this message]
2019-04-12 14:00     ` Bjorn Helgaas
2019-04-14 11:16     ` [EXT] " Z.q. Hou
2019-04-14 11:16       ` Z.q. Hou
2019-04-12 14:41   ` Arnd Bergmann
2019-04-12 14:41     ` Arnd Bergmann
2019-04-12 14:41     ` Arnd Bergmann
2019-04-30  0:26     ` [EXT] " Z.q. Hou
2019-04-30  0:26       ` Z.q. Hou
2019-04-12  9:52 ` [PATCHv5 5/6] arm64: dts: lx2160a: Add PCIe controller DT nodes Z.q. Hou
2019-04-12  9:52   ` Z.q. Hou
2019-04-12  9:53 ` [PATCHv5 6/6] arm64: defconfig: Enable CONFIG_PCI_LAYERSCAPE_GEN4 Z.q. Hou
2019-04-12  9:53   ` Z.q. Hou

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