From: Peter Zijlstra <peterz@infradead.org>
To: Nadav Amit <namit@vmware.com>
Cc: kernel test robot <lkp@intel.com>, LKP <lkp@01.org>,
Linux List Kernel Mailing <linux-kernel@vger.kernel.org>,
Linux-MM <linux-mm@kvack.org>,
linux-arch <linux-arch@vger.kernel.org>,
Ingo Molnar <mingo@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Will Deacon <will.deacon@arm.com>,
Andy Lutomirski <luto@kernel.org>,
Linus Torvalds <torvalds@linux-foundation.org>,
Dave Hansen <dave.hansen@intel.com>
Subject: Re: 1808d65b55 ("asm-generic/tlb: Remove arch_tlb*_mmu()"): BUG: KASAN: stack-out-of-bounds in __change_page_attr_set_clr
Date: Fri, 12 Apr 2019 20:19:30 +0200 [thread overview]
Message-ID: <20190412181930.GD12232@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <F18AF0D5-D8B4-4F4B-8469-F9DEC49683C7@vmware.com>
On Fri, Apr 12, 2019 at 03:11:22PM +0000, Nadav Amit wrote:
> > On Apr 12, 2019, at 4:17 AM, Peter Zijlstra <peterz@infradead.org> wrote:
> > To clarify, 'that' is Nadav's patch:
> >
> > 515ab7c41306 ("x86/mm: Align TLB invalidation info")
> >
> > which turns out to be the real problem.
>
> Sorry for that. I still think it should be aligned, especially with all the
> effort the Intel puts around to avoid bus-locking on unaligned atomic
> operations.
No atomics anywhere in sight, so that's not a concern.
> So the right solution seems to me as putting this data structure off stack.
> It would prevent flush_tlb_mm_range() from being reentrant, so we can keep a
> few entries for this matter and atomically increase the entry number every
> time we enter flush_tlb_mm_range().
>
> But my question is - should flush_tlb_mm_range() be reentrant, or can we
> assume no TLB shootdowns are initiated in interrupt handlers and #MC
> handlers?
There _should_ not be, but then don't look at those XPFO patches that
were posted (they're broken anyway).
WARNING: multiple messages have this Message-ID (diff)
From: Peter Zijlstra <peterz@infradead.org>
To: lkp@lists.01.org
Subject: Re: 1808d65b55 ("asm-generic/tlb: Remove arch_tlb*_mmu()"): BUG: KASAN: stack-out-of-bounds in __change_page_attr_set_clr
Date: Fri, 12 Apr 2019 20:19:30 +0200 [thread overview]
Message-ID: <20190412181930.GD12232@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <F18AF0D5-D8B4-4F4B-8469-F9DEC49683C7@vmware.com>
[-- Attachment #1: Type: text/plain, Size: 1085 bytes --]
On Fri, Apr 12, 2019 at 03:11:22PM +0000, Nadav Amit wrote:
> > On Apr 12, 2019, at 4:17 AM, Peter Zijlstra <peterz@infradead.org> wrote:
> > To clarify, 'that' is Nadav's patch:
> >
> > 515ab7c41306 ("x86/mm: Align TLB invalidation info")
> >
> > which turns out to be the real problem.
>
> Sorry for that. I still think it should be aligned, especially with all the
> effort the Intel puts around to avoid bus-locking on unaligned atomic
> operations.
No atomics anywhere in sight, so that's not a concern.
> So the right solution seems to me as putting this data structure off stack.
> It would prevent flush_tlb_mm_range() from being reentrant, so we can keep a
> few entries for this matter and atomically increase the entry number every
> time we enter flush_tlb_mm_range().
>
> But my question is - should flush_tlb_mm_range() be reentrant, or can we
> assume no TLB shootdowns are initiated in interrupt handlers and #MC
> handlers?
There _should_ not be, but then don't look at those XPFO patches that
were posted (they're broken anyway).
next prev parent reply other threads:[~2019-04-12 18:19 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-10 14:55 1808d65b55 ("asm-generic/tlb: Remove arch_tlb*_mmu()"): BUG: KASAN: stack-out-of-bounds in __change_page_attr_set_clr kernel test robot
2019-04-10 14:55 ` kernel test robot
2019-04-11 19:39 ` Peter Zijlstra
2019-04-11 19:39 ` Peter Zijlstra
2019-04-11 19:54 ` Peter Zijlstra
2019-04-11 19:54 ` Peter Zijlstra
2019-04-11 21:13 ` Peter Zijlstra
2019-04-11 21:13 ` Peter Zijlstra
2019-04-12 10:56 ` Peter Zijlstra
2019-04-12 10:56 ` Peter Zijlstra
2019-04-12 11:17 ` Peter Zijlstra
2019-04-12 11:17 ` Peter Zijlstra
2019-04-12 15:11 ` Nadav Amit
2019-04-12 15:11 ` Nadav Amit
2019-04-12 15:18 ` Nadav Amit
2019-04-12 15:18 ` Nadav Amit
2019-04-12 17:05 ` Nadav Amit
2019-04-12 17:05 ` Nadav Amit
2019-04-12 17:14 ` Andy Lutomirski
2019-04-12 17:14 ` Andy Lutomirski
2019-04-12 17:49 ` Nadav Amit
2019-04-12 17:49 ` Nadav Amit
2019-04-12 18:13 ` Peter Zijlstra
2019-04-12 18:13 ` Peter Zijlstra
2019-04-12 18:19 ` Peter Zijlstra [this message]
2019-04-12 18:19 ` Peter Zijlstra
2019-04-12 19:42 ` Nadav Amit
2019-04-12 19:42 ` Nadav Amit
2019-04-12 15:32 ` Linus Torvalds
2019-04-12 15:32 ` Linus Torvalds
2019-04-12 16:50 ` David Howells
2019-04-12 16:50 ` David Howells
2019-04-12 18:15 ` Peter Zijlstra
2019-04-12 18:15 ` Peter Zijlstra
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