All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org,
	Eero Tamminen <eero.t.tamminen@intel.com>
Subject: Re: [PATCH] drm/i915: Enable eLLC caching of display buffers for SKL+
Date: Wed, 17 Apr 2019 20:15:43 +0300	[thread overview]
Message-ID: <20190417171543.GC1747@intel.com> (raw)
In-Reply-To: <155548494737.2264.4147744577196100660@skylake-alporthouse-com>

On Wed, Apr 17, 2019 at 08:09:07AM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-04-15 15:16:41)
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Since SKL the eLLC has been sitting on the far side of the system
> > agent, meaning the display engine can utilize it. Let's enable that.
> > 
> > I chose WB for the caching mode, because my numbers are indicating
> > that WT might actually be WB and WC might actually be UC. I'm not
> > 100% sure that is indeed the case but at least my simple rendercopy
> > based benchmark didn't see any difference in performance.
> > 
> > Also if I configure things to do LLCeLLC+WT I still get cache dirt
> > on my screen, suggesting that is in fact operating in WB mode
> > anyway. This is also the reason I had to fix the MOCS target cache
> > to really say PTE rather than LLC+eLLC.
> 
> We also need to check with hybrid setups that supply buffers via prime,
> and we may need to end up marking those as explicitly uncached.

I think all memory access should be able to snoop the eLLC. But yeah,
this should be confirmed on actual hardware. Anyone have a prime setup
handy?

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2019-04-17 17:15 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-15 14:16 [PATCH] drm/i915: Enable eLLC caching of display buffers for SKL+ Ville Syrjala
2019-04-15 15:02 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2019-04-15 15:03 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-04-15 15:21 ` ✓ Fi.CI.BAT: success " Patchwork
2019-04-15 16:03   ` Chris Wilson
2019-04-15 16:20     ` Ville Syrjälä
2019-04-15 17:38 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-04-16 14:28 ` [PATCH] " Eero Tamminen
2019-04-16 14:37   ` Ville Syrjälä
2019-04-17  7:09 ` Chris Wilson
2019-04-17 17:15   ` Ville Syrjälä [this message]
2019-04-26 14:54     ` Ville Syrjälä
2019-04-26 15:01       ` Chris Wilson
2019-04-26 15:13         ` Ville Syrjälä
2019-05-24 20:19 ` Chris Wilson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20190417171543.GC1747@intel.com \
    --to=ville.syrjala@linux.intel.com \
    --cc=chris@chris-wilson.co.uk \
    --cc=eero.t.tamminen@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.