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From: Will Deacon <will.deacon@arm.com>
To: Kristina Martsenko <kristina.martsenko@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	kvmarm@lists.cs.columbia.edu, Amit Kachhap <amit.kachhap@arm.com>,
	Dave P Martin <dave.martin@arm.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] KVM: arm64: fix ptrauth ID register masking logic
Date: Wed, 1 May 2019 17:16:57 +0100	[thread overview]
Message-ID: <20190501161657.GD28109@fuggles.cambridge.arm.com> (raw)
In-Reply-To: <20190501161008.31498-1-kristina.martsenko@arm.com>

On Wed, May 01, 2019 at 05:10:08PM +0100, Kristina Martsenko wrote:
> When a VCPU doesn't have pointer auth, we want to hide all four pointer
> auth ID register fields from the guest, not just one of them.
> 
> Fixes: 384b40caa8af ("KVM: arm/arm64: Context-switch ptrauth registers")
> Reported-by: Andrew Murray <andrew.murray@arm.com>
> Fsck-up-by: Marc Zyngier <marc.zyngier@arm.com>

Past tense is "fscked" ;)

With that:

Acked-by: Will Deacon <will.deacon@arm.com>

Will

> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 9d02643bc601..857b226bcdde 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -1088,10 +1088,10 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
>  	if (id == SYS_ID_AA64PFR0_EL1 && !vcpu_has_sve(vcpu)) {
>  		val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
>  	} else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) {
> -		val &= ~(0xfUL << ID_AA64ISAR1_APA_SHIFT) |
> -			(0xfUL << ID_AA64ISAR1_API_SHIFT) |
> -			(0xfUL << ID_AA64ISAR1_GPA_SHIFT) |
> -			(0xfUL << ID_AA64ISAR1_GPI_SHIFT);
> +		val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) |
> +			 (0xfUL << ID_AA64ISAR1_API_SHIFT) |
> +			 (0xfUL << ID_AA64ISAR1_GPA_SHIFT) |
> +			 (0xfUL << ID_AA64ISAR1_GPI_SHIFT));
>  	}
>  
>  	return val;
> -- 
> 2.11.0
> 

WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will.deacon@arm.com>
To: Kristina Martsenko <kristina.martsenko@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	kvmarm@lists.cs.columbia.edu, Amit Kachhap <amit.kachhap@arm.com>,
	Dave P Martin <dave.martin@arm.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] KVM: arm64: fix ptrauth ID register masking logic
Date: Wed, 1 May 2019 17:16:57 +0100	[thread overview]
Message-ID: <20190501161657.GD28109@fuggles.cambridge.arm.com> (raw)
Message-ID: <20190501161657.vYLykG_iPA0BX7oAKG2TBqqxReDPk8MOpIk7qijAuv8@z> (raw)
In-Reply-To: <20190501161008.31498-1-kristina.martsenko@arm.com>

On Wed, May 01, 2019 at 05:10:08PM +0100, Kristina Martsenko wrote:
> When a VCPU doesn't have pointer auth, we want to hide all four pointer
> auth ID register fields from the guest, not just one of them.
> 
> Fixes: 384b40caa8af ("KVM: arm/arm64: Context-switch ptrauth registers")
> Reported-by: Andrew Murray <andrew.murray@arm.com>
> Fsck-up-by: Marc Zyngier <marc.zyngier@arm.com>

Past tense is "fscked" ;)

With that:

Acked-by: Will Deacon <will.deacon@arm.com>

Will

> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 9d02643bc601..857b226bcdde 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -1088,10 +1088,10 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
>  	if (id == SYS_ID_AA64PFR0_EL1 && !vcpu_has_sve(vcpu)) {
>  		val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
>  	} else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) {
> -		val &= ~(0xfUL << ID_AA64ISAR1_APA_SHIFT) |
> -			(0xfUL << ID_AA64ISAR1_API_SHIFT) |
> -			(0xfUL << ID_AA64ISAR1_GPA_SHIFT) |
> -			(0xfUL << ID_AA64ISAR1_GPI_SHIFT);
> +		val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) |
> +			 (0xfUL << ID_AA64ISAR1_API_SHIFT) |
> +			 (0xfUL << ID_AA64ISAR1_GPA_SHIFT) |
> +			 (0xfUL << ID_AA64ISAR1_GPI_SHIFT));
>  	}
>  
>  	return val;
> -- 
> 2.11.0
> 
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will.deacon@arm.com>
To: Kristina Martsenko <kristina.martsenko@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
	Julien Thierry <julien.thierry@arm.com>,
	Marc Zyngier <marc.zyngier@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Christoffer Dall <christoffer.dall@arm.com>,
	kvmarm@lists.cs.columbia.edu, James Morse <james.morse@arm.com>,
	Amit Kachhap <amit.kachhap@arm.com>,
	Andrew Murray <andrew.murray@arm.com>,
	Dave P Martin <dave.martin@arm.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] KVM: arm64: fix ptrauth ID register masking logic
Date: Wed, 1 May 2019 17:16:57 +0100	[thread overview]
Message-ID: <20190501161657.GD28109@fuggles.cambridge.arm.com> (raw)
In-Reply-To: <20190501161008.31498-1-kristina.martsenko@arm.com>

On Wed, May 01, 2019 at 05:10:08PM +0100, Kristina Martsenko wrote:
> When a VCPU doesn't have pointer auth, we want to hide all four pointer
> auth ID register fields from the guest, not just one of them.
> 
> Fixes: 384b40caa8af ("KVM: arm/arm64: Context-switch ptrauth registers")
> Reported-by: Andrew Murray <andrew.murray@arm.com>
> Fsck-up-by: Marc Zyngier <marc.zyngier@arm.com>

Past tense is "fscked" ;)

With that:

Acked-by: Will Deacon <will.deacon@arm.com>

Will

> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 9d02643bc601..857b226bcdde 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -1088,10 +1088,10 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
>  	if (id == SYS_ID_AA64PFR0_EL1 && !vcpu_has_sve(vcpu)) {
>  		val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
>  	} else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) {
> -		val &= ~(0xfUL << ID_AA64ISAR1_APA_SHIFT) |
> -			(0xfUL << ID_AA64ISAR1_API_SHIFT) |
> -			(0xfUL << ID_AA64ISAR1_GPA_SHIFT) |
> -			(0xfUL << ID_AA64ISAR1_GPI_SHIFT);
> +		val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) |
> +			 (0xfUL << ID_AA64ISAR1_API_SHIFT) |
> +			 (0xfUL << ID_AA64ISAR1_GPA_SHIFT) |
> +			 (0xfUL << ID_AA64ISAR1_GPI_SHIFT));
>  	}
>  
>  	return val;
> -- 
> 2.11.0
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2019-05-01 16:17 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-01 16:10 [PATCH] KVM: arm64: fix ptrauth ID register masking logic Kristina Martsenko
2019-05-01 16:10 ` Kristina Martsenko
2019-05-01 16:10 ` Kristina Martsenko
2019-05-01 16:16 ` Will Deacon [this message]
2019-05-01 16:16   ` Will Deacon
2019-05-01 16:16   ` Will Deacon
2019-05-01 16:20   ` Andrew Murray
2019-05-01 16:20     ` Andrew Murray
2019-05-01 16:20     ` Andrew Murray
2019-05-01 16:20 ` Marc Zyngier
2019-05-01 16:20   ` Marc Zyngier
2019-05-01 16:20   ` Marc Zyngier
2019-05-02  8:53   ` Dave Martin
2019-05-02  8:53     ` Dave Martin
2019-05-02  8:53     ` Dave Martin

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