[PATCH v2 0/3] Add struct esdhc_soc_data for i.MX7ULP

[PATCH v2 0/3] Add struct esdhc_soc_data for i.MX7ULP

[BOUGH CHEN]

---
Changes for V2:
-remove the request on the subsequent error paths in pm_runtime_resume

Haibo Chen (3):
  dt-bindings: mmc: fsl-imx-esdhc: add imx7ulp compatible string
  mmc: sdhci-esdhc-imx: add pm_qos to interact with cpuidle
  mmc: add HS400 support for iMX7ULP

 .../devicetree/bindings/mmc/fsl-imx-esdhc.txt |  1 +
 drivers/mmc/host/sdhci-esdhc-imx.c            | 41 +++++++++++++++++--
 2 files changed, 39 insertions(+), 3 deletions(-)

-- 
2.17.1

[PATCH v2 1/3] dt-bindings: mmc: fsl-imx-esdhc: add imx7ulp compatible string

[BOUGH CHEN]

Add imx7ulp compatible string.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
---
 Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
index 540c65ed9cba..f707b8bee304 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
+++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
@@ -17,6 +17,7 @@ Required properties:
 	       "fsl,imx6sx-usdhc"
 	       "fsl,imx6ull-usdhc"
 	       "fsl,imx7d-usdhc"
+	       "fsl,imx7ulp-usdhc"
 	       "fsl,imx8qxp-usdhc"
 
 Optional properties:
-- 
2.17.1

Re: [PATCH v2 1/3] dt-bindings: mmc: fsl-imx-esdhc: add imx7ulp compatible string

[Rob Herring]

On Mon, 29 Apr 2019 08:55:32 +0000, BOUGH CHEN wrote:
> Add imx7ulp compatible string.
> 
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
>  Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt | 1 +
>  1 file changed, 1 insertion(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

[PATCH v2 2/3] mmc: sdhci-esdhc-imx: add pm_qos to interact with cpuidle

[BOUGH CHEN]

On some SoCs such as i.MX7ULP, there is no busfreq
driver, but cpuidle has some levels which may disable
system/bus clocks, so need to add pm_qos to prevent
cpuidle from entering low level idles and make sure
system/bus clocks are enabled when usdhc is active.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
 drivers/mmc/host/sdhci-esdhc-imx.c | 32 +++++++++++++++++++++++++++++-
 1 file changed, 31 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 8dbbc1f62b70..053e8586d557 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -14,6 +14,7 @@
 #include <linux/clk.h>
 #include <linux/module.h>
 #include <linux/slab.h>
+#include <linux/pm_qos.h>
 #include <linux/mmc/host.h>
 #include <linux/mmc/mmc.h>
 #include <linux/mmc/sdio.h>
@@ -156,6 +157,8 @@
 #define ESDHC_FLAG_HS400_ES		BIT(11)
 /* The IP has Host Controller Interface for Command Queuing */
 #define ESDHC_FLAG_CQHCI		BIT(12)
+/* need request pmqos during low power */
+#define ESDHC_FLAG_PMQOS		BIT(13)
 
 struct esdhc_soc_data {
 	u32 flags;
@@ -204,6 +207,12 @@ static const struct esdhc_soc_data usdhc_imx7d_data = {
 			| ESDHC_FLAG_HS400,
 };
 
+static struct esdhc_soc_data usdhc_imx7ulp_data = {
+	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
+			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
+			| ESDHC_FLAG_PMQOS,
+};
+
 static struct esdhc_soc_data usdhc_imx8qxp_data = {
 	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
@@ -229,6 +238,7 @@ struct pltfm_imx_data {
 		WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
 	} multiblock_status;
 	u32 is_ddr;
+	struct pm_qos_request pm_qos_req;
 };
 
 static const struct platform_device_id imx_esdhc_devtype[] = {
@@ -257,6 +267,7 @@ static const struct of_device_id imx_esdhc_dt_ids[] = {
 	{ .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
 	{ .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
 	{ .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
+	{ .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
 	{ .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
 	{ /* sentinel */ }
 };
@@ -1436,6 +1447,10 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
 	imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
 						  pdev->id_entry->driver_data;
 
+	if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
+		pm_qos_add_request(&imx_data->pm_qos_req,
+			PM_QOS_CPU_DMA_LATENCY, 0);
+
 	imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
 	if (IS_ERR(imx_data->clk_ipg)) {
 		err = PTR_ERR(imx_data->clk_ipg);
@@ -1557,6 +1572,8 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
 disable_per_clk:
 	clk_disable_unprepare(imx_data->clk_per);
 free_sdhci:
+	if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
+		pm_qos_remove_request(&imx_data->pm_qos_req);
 	sdhci_pltfm_free(pdev);
 	return err;
 }
@@ -1578,6 +1595,9 @@ static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
 	clk_disable_unprepare(imx_data->clk_ipg);
 	clk_disable_unprepare(imx_data->clk_ahb);
 
+	if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
+		pm_qos_remove_request(&imx_data->pm_qos_req);
+
 	sdhci_pltfm_free(pdev);
 
 	return 0;
@@ -1649,6 +1669,9 @@ static int sdhci_esdhc_runtime_suspend(struct device *dev)
 	}
 	clk_disable_unprepare(imx_data->clk_ahb);
 
+	if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
+		pm_qos_remove_request(&imx_data->pm_qos_req);
+
 	return ret;
 }
 
@@ -1659,9 +1682,13 @@ static int sdhci_esdhc_runtime_resume(struct device *dev)
 	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 	int err;
 
+	if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
+		pm_qos_add_request(&imx_data->pm_qos_req,
+			PM_QOS_CPU_DMA_LATENCY, 0);
+
 	err = clk_prepare_enable(imx_data->clk_ahb);
 	if (err)
-		return err;
+		goto remove_pm_qos_request;
 
 	if (!sdhci_sdio_irq_enabled(host)) {
 		err = clk_prepare_enable(imx_data->clk_per);
@@ -1690,6 +1717,9 @@ static int sdhci_esdhc_runtime_resume(struct device *dev)
 		clk_disable_unprepare(imx_data->clk_per);
 disable_ahb_clk:
 	clk_disable_unprepare(imx_data->clk_ahb);
+remove_pm_qos_request:
+	if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
+		pm_qos_remove_request(&imx_data->pm_qos_req);
 	return err;
 }
 #endif
-- 
2.17.1

RE: [PATCH v2 2/3] mmc: sdhci-esdhc-imx: add pm_qos to interact with cpuidle

[Aisheng Dong]

> From: BOUGH CHEN
> Sent: Monday, April 29, 2019 4:56 PM
> 
> On some SoCs such as i.MX7ULP, there is no busfreq driver, but cpuidle has
> some levels which may disable system/bus clocks, so need to add pm_qos to
> prevent cpuidle from entering low level idles and make sure system/bus clocks
> are enabled when usdhc is active.
> 
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Dong Aisheng

Re: [PATCH v2 2/3] mmc: sdhci-esdhc-imx: add pm_qos to interact with cpuidle

[Adrian Hunter]

On 29/04/19 11:55 AM, BOUGH CHEN wrote:
> On some SoCs such as i.MX7ULP, there is no busfreq
> driver, but cpuidle has some levels which may disable
> system/bus clocks, so need to add pm_qos to prevent
> cpuidle from entering low level idles and make sure
> system/bus clocks are enabled when usdhc is active.
> 
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci-esdhc-imx.c | 32 +++++++++++++++++++++++++++++-
>  1 file changed, 31 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
> index 8dbbc1f62b70..053e8586d557 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -14,6 +14,7 @@
>  #include <linux/clk.h>
>  #include <linux/module.h>
>  #include <linux/slab.h>
> +#include <linux/pm_qos.h>
>  #include <linux/mmc/host.h>
>  #include <linux/mmc/mmc.h>
>  #include <linux/mmc/sdio.h>
> @@ -156,6 +157,8 @@
>  #define ESDHC_FLAG_HS400_ES		BIT(11)
>  /* The IP has Host Controller Interface for Command Queuing */
>  #define ESDHC_FLAG_CQHCI		BIT(12)
> +/* need request pmqos during low power */
> +#define ESDHC_FLAG_PMQOS		BIT(13)
>  
>  struct esdhc_soc_data {
>  	u32 flags;
> @@ -204,6 +207,12 @@ static const struct esdhc_soc_data usdhc_imx7d_data = {
>  			| ESDHC_FLAG_HS400,
>  };
>  
> +static struct esdhc_soc_data usdhc_imx7ulp_data = {
> +	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
> +			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
> +			| ESDHC_FLAG_PMQOS,
> +};
> +
>  static struct esdhc_soc_data usdhc_imx8qxp_data = {
>  	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
>  			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
> @@ -229,6 +238,7 @@ struct pltfm_imx_data {
>  		WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
>  	} multiblock_status;
>  	u32 is_ddr;
> +	struct pm_qos_request pm_qos_req;
>  };
>  
>  static const struct platform_device_id imx_esdhc_devtype[] = {
> @@ -257,6 +267,7 @@ static const struct of_device_id imx_esdhc_dt_ids[] = {
>  	{ .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
>  	{ .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
>  	{ .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
> +	{ .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
>  	{ .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
>  	{ /* sentinel */ }
>  };
> @@ -1436,6 +1447,10 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
>  	imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
>  						  pdev->id_entry->driver_data;
>  
> +	if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
> +		pm_qos_add_request(&imx_data->pm_qos_req,
> +			PM_QOS_CPU_DMA_LATENCY, 0);
> +
>  	imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
>  	if (IS_ERR(imx_data->clk_ipg)) {
>  		err = PTR_ERR(imx_data->clk_ipg);
> @@ -1557,6 +1572,8 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
>  disable_per_clk:
>  	clk_disable_unprepare(imx_data->clk_per);
>  free_sdhci:
> +	if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
> +		pm_qos_remove_request(&imx_data->pm_qos_req);
>  	sdhci_pltfm_free(pdev);
>  	return err;
>  }
> @@ -1578,6 +1595,9 @@ static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
>  	clk_disable_unprepare(imx_data->clk_ipg);
>  	clk_disable_unprepare(imx_data->clk_ahb);
>  
> +	if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
> +		pm_qos_remove_request(&imx_data->pm_qos_req);
> +
>  	sdhci_pltfm_free(pdev);
>  
>  	return 0;
> @@ -1649,6 +1669,9 @@ static int sdhci_esdhc_runtime_suspend(struct device *dev)
>  	}
>  	clk_disable_unprepare(imx_data->clk_ahb);
>  
> +	if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
> +		pm_qos_remove_request(&imx_data->pm_qos_req);
> +
>  	return ret;
>  }
>  
> @@ -1659,9 +1682,13 @@ static int sdhci_esdhc_runtime_resume(struct device *dev)
>  	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
>  	int err;
>  
> +	if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
> +		pm_qos_add_request(&imx_data->pm_qos_req,
> +			PM_QOS_CPU_DMA_LATENCY, 0);
> +
>  	err = clk_prepare_enable(imx_data->clk_ahb);
>  	if (err)
> -		return err;
> +		goto remove_pm_qos_request;
>  
>  	if (!sdhci_sdio_irq_enabled(host)) {
>  		err = clk_prepare_enable(imx_data->clk_per);
> @@ -1690,6 +1717,9 @@ static int sdhci_esdhc_runtime_resume(struct device *dev)
>  		clk_disable_unprepare(imx_data->clk_per);
>  disable_ahb_clk:
>  	clk_disable_unprepare(imx_data->clk_ahb);
> +remove_pm_qos_request:
> +	if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
> +		pm_qos_remove_request(&imx_data->pm_qos_req);
>  	return err;
>  }
>  #endif
> 

[PATCH v2 3/3] mmc: add HS400 support for iMX7ULP

[BOUGH CHEN]

Add HS400 support for iMX7ULP B0.

According to IC suggest, need to clear the STROBE_DLL_CTRL_RESET
before any setting of STROBE_DLL_CTRL register.

USDHC has register bits(bit[27~20] of register STROBE_DLL_CTRL)
for slave sel value. If this register bits value is 0,  it needs
256 ref_clk cycles to update slave sel value. IC suggest to set
bit[27~20] to 0x4, it only need 4 ref_clk cycle to update slave
sel value. This will short the lock time of slave.

i.MX7ULP B0 will need more time to lock the REF and SLV, so change
to add 5us delay.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
 drivers/mmc/host/sdhci-esdhc-imx.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 053e8586d557..c391510e9ef4 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -74,6 +74,7 @@
 #define ESDHC_STROBE_DLL_CTRL_ENABLE	(1 << 0)
 #define ESDHC_STROBE_DLL_CTRL_RESET	(1 << 1)
 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT	3
+#define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT	(4 << 20)
 
 #define ESDHC_STROBE_DLL_STATUS		0x74
 #define ESDHC_STROBE_DLL_STS_REF_LOCK	(1 << 1)
@@ -210,7 +211,7 @@ static const struct esdhc_soc_data usdhc_imx7d_data = {
 static struct esdhc_soc_data usdhc_imx7ulp_data = {
 	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
-			| ESDHC_FLAG_PMQOS,
+			| ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400,
 };
 
 static struct esdhc_soc_data usdhc_imx8qxp_data = {
@@ -994,15 +995,19 @@ static void esdhc_set_strobe_dll(struct sdhci_host *host)
 	/* force a reset on strobe dll */
 	writel(ESDHC_STROBE_DLL_CTRL_RESET,
 		host->ioaddr + ESDHC_STROBE_DLL_CTRL);
+	/* clear the reset bit on strobe dll before any setting */
+	writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
+
 	/*
 	 * enable strobe dll ctrl and adjust the delay target
 	 * for the uSDHC loopback read clock
 	 */
 	v = ESDHC_STROBE_DLL_CTRL_ENABLE |
+		ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
 		(7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
 	writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
-	/* wait 1us to make sure strobe dll status register stable */
-	udelay(1);
+	/* wait 5us to make sure strobe dll status register stable */
+	udelay(5);
 	v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS);
 	if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK))
 		dev_warn(mmc_dev(host->mmc),
-- 
2.17.1

RE: [PATCH v2 3/3] mmc: add HS400 support for iMX7ULP

[Aisheng Dong]

> From: BOUGH CHEN
> Sent: Monday, April 29, 2019 4:56 PM
> Subject: [PATCH v2 3/3] mmc: add HS400 support for iMX7ULP
> 
> Add HS400 support for iMX7ULP B0.
> 
> According to IC suggest, need to clear the STROBE_DLL_CTRL_RESET before any
> setting of STROBE_DLL_CTRL register.
> 
> USDHC has register bits(bit[27~20] of register STROBE_DLL_CTRL) for slave sel
> value. If this register bits value is 0,  it needs
> 256 ref_clk cycles to update slave sel value. IC suggest to set bit[27~20] to 0x4,
> it only need 4 ref_clk cycle to update slave sel value. This will short the lock
> time of slave.
> 
> i.MX7ULP B0 will need more time to lock the REF and SLV, so change to add
> 5us delay.
> 
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

mmc: sdhci-esdhc-imx: add HS400 support for iMX7ULP

otherwise:
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Dong Aisheng

Re: [PATCH v2 3/3] mmc: add HS400 support for iMX7ULP

[Adrian Hunter]

On 29/04/19 11:55 AM, BOUGH CHEN wrote:
> Add HS400 support for iMX7ULP B0.
> 
> According to IC suggest, need to clear the STROBE_DLL_CTRL_RESET
> before any setting of STROBE_DLL_CTRL register.
> 
> USDHC has register bits(bit[27~20] of register STROBE_DLL_CTRL)
> for slave sel value. If this register bits value is 0,  it needs
> 256 ref_clk cycles to update slave sel value. IC suggest to set
> bit[27~20] to 0x4, it only need 4 ref_clk cycle to update slave
> sel value. This will short the lock time of slave.
> 
> i.MX7ULP B0 will need more time to lock the REF and SLV, so change
> to add 5us delay.
> 
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci-esdhc-imx.c | 11 ++++++++---
>  1 file changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
> index 053e8586d557..c391510e9ef4 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -74,6 +74,7 @@
>  #define ESDHC_STROBE_DLL_CTRL_ENABLE	(1 << 0)
>  #define ESDHC_STROBE_DLL_CTRL_RESET	(1 << 1)
>  #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT	3
> +#define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT	(4 << 20)
>  
>  #define ESDHC_STROBE_DLL_STATUS		0x74
>  #define ESDHC_STROBE_DLL_STS_REF_LOCK	(1 << 1)
> @@ -210,7 +211,7 @@ static const struct esdhc_soc_data usdhc_imx7d_data = {
>  static struct esdhc_soc_data usdhc_imx7ulp_data = {
>  	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
>  			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
> -			| ESDHC_FLAG_PMQOS,
> +			| ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400,
>  };
>  
>  static struct esdhc_soc_data usdhc_imx8qxp_data = {
> @@ -994,15 +995,19 @@ static void esdhc_set_strobe_dll(struct sdhci_host *host)
>  	/* force a reset on strobe dll */
>  	writel(ESDHC_STROBE_DLL_CTRL_RESET,
>  		host->ioaddr + ESDHC_STROBE_DLL_CTRL);
> +	/* clear the reset bit on strobe dll before any setting */
> +	writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
> +
>  	/*
>  	 * enable strobe dll ctrl and adjust the delay target
>  	 * for the uSDHC loopback read clock
>  	 */
>  	v = ESDHC_STROBE_DLL_CTRL_ENABLE |
> +		ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
>  		(7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
>  	writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
> -	/* wait 1us to make sure strobe dll status register stable */
> -	udelay(1);
> +	/* wait 5us to make sure strobe dll status register stable */
> +	udelay(5);
>  	v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS);
>  	if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK))
>  		dev_warn(mmc_dev(host->mmc),
> 

Re: [PATCH v2 0/3] Add struct esdhc_soc_data for i.MX7ULP

[Ulf Hansson]

On Mon, 29 Apr 2019 at 10:55, BOUGH CHEN <haibo.chen@nxp.com> wrote:
>
> ---
> Changes for V2:
> -remove the request on the subsequent error paths in pm_runtime_resume
>
> Haibo Chen (3):
>   dt-bindings: mmc: fsl-imx-esdhc: add imx7ulp compatible string
>   mmc: sdhci-esdhc-imx: add pm_qos to interact with cpuidle
>   mmc: add HS400 support for iMX7ULP
>
>  .../devicetree/bindings/mmc/fsl-imx-esdhc.txt |  1 +
>  drivers/mmc/host/sdhci-esdhc-imx.c            | 41 +++++++++++++++++--
>  2 files changed, 39 insertions(+), 3 deletions(-)
>
> --
> 2.17.1
>

Applied for next, thanks!

Kind regards
Uffe