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From: Joseph Lo <josephl@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Rob Herring <robh+dt@kernel.org>, Stephen Boyd <sboyd@kernel.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
	<linux-tegra@vger.kernel.org>, <linux-clk@vger.kernel.org>,
	<devicetree@vger.kernel.org>, Joseph Lo <josephl@nvidia.com>
Subject: [PATCH V4 8/8] arm64: tegra: Add external memory controller node for Tegra210
Date: Wed, 29 May 2019 16:21:39 +0800	[thread overview]
Message-ID: <20190529082139.5581-9-josephl@nvidia.com> (raw)
In-Reply-To: <20190529082139.5581-1-josephl@nvidia.com>

Add external memory controller (EMC) node for Tegra210

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
v4:
- no change.
v3:
- apply memory-region for emc_table. And add reserved-memory node with
  it.
---
 arch/arm64/boot/dts/nvidia/tegra210.dtsi | 33 ++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index bc71ef8f9a09..b9ccfee39ed2 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -872,6 +872,27 @@
 		#iommu-cells = <1>;
 	};
 
+	external-memory-controller@7001b000 {
+		compatible = "nvidia,tegra210-emc";
+		reg = <0x0 0x7001b000 0x0 0x1000>,
+		      <0x0 0x7001e000 0x0 0x1000>,
+		      <0x0 0x7001f000 0x0 0x1000>;
+		clocks = <&tegra_car TEGRA210_CLK_EMC>,
+			 <&tegra_car TEGRA210_CLK_PLL_M>,
+			 <&tegra_car TEGRA210_CLK_PLL_C>,
+			 <&tegra_car TEGRA210_CLK_PLL_P>,
+			 <&tegra_car TEGRA210_CLK_CLK_M>,
+			 <&tegra_car TEGRA210_CLK_PLL_M_UD>,
+			 <&tegra_car TEGRA210_CLK_PLL_MB_UD>,
+			 <&tegra_car TEGRA210_CLK_PLL_MB>,
+			 <&tegra_car TEGRA210_CLK_PLL_P_UD>;
+		clock-names = "emc", "pll_m", "pll_c", "pll_p", "clk_m",
+			      "pll_m_ud", "pll_mb_ud", "pll_mb", "pll_p_ud";
+		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+		memory-region = <&emc_table>;
+		nvidia,memory-controller = <&mc>;
+	};
+
 	sata@70020000 {
 		compatible = "nvidia,tegra210-ahci";
 		reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
@@ -1431,6 +1452,18 @@
 		};
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		emc_table: emc-table@8be00000 {
+			compatible = "nvidia,tegra210-emc-table";
+			reg = <0x0 0x8be00000 0x0 0x10000>;
+			status = "disabled";
+		};
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13
-- 
2.21.0


WARNING: multiple messages have this Message-ID (diff)
From: Joseph Lo <josephl@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Rob Herring <robh+dt@kernel.org>, Stephen Boyd <sboyd@kernel.org>
Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	Joseph Lo <josephl@nvidia.com>
Subject: [PATCH V4 8/8] arm64: tegra: Add external memory controller node for Tegra210
Date: Wed, 29 May 2019 16:21:39 +0800	[thread overview]
Message-ID: <20190529082139.5581-9-josephl@nvidia.com> (raw)
In-Reply-To: <20190529082139.5581-1-josephl@nvidia.com>

Add external memory controller (EMC) node for Tegra210

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
v4:
- no change.
v3:
- apply memory-region for emc_table. And add reserved-memory node with
  it.
---
 arch/arm64/boot/dts/nvidia/tegra210.dtsi | 33 ++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index bc71ef8f9a09..b9ccfee39ed2 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -872,6 +872,27 @@
 		#iommu-cells = <1>;
 	};
 
+	external-memory-controller@7001b000 {
+		compatible = "nvidia,tegra210-emc";
+		reg = <0x0 0x7001b000 0x0 0x1000>,
+		      <0x0 0x7001e000 0x0 0x1000>,
+		      <0x0 0x7001f000 0x0 0x1000>;
+		clocks = <&tegra_car TEGRA210_CLK_EMC>,
+			 <&tegra_car TEGRA210_CLK_PLL_M>,
+			 <&tegra_car TEGRA210_CLK_PLL_C>,
+			 <&tegra_car TEGRA210_CLK_PLL_P>,
+			 <&tegra_car TEGRA210_CLK_CLK_M>,
+			 <&tegra_car TEGRA210_CLK_PLL_M_UD>,
+			 <&tegra_car TEGRA210_CLK_PLL_MB_UD>,
+			 <&tegra_car TEGRA210_CLK_PLL_MB>,
+			 <&tegra_car TEGRA210_CLK_PLL_P_UD>;
+		clock-names = "emc", "pll_m", "pll_c", "pll_p", "clk_m",
+			      "pll_m_ud", "pll_mb_ud", "pll_mb", "pll_p_ud";
+		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+		memory-region = <&emc_table>;
+		nvidia,memory-controller = <&mc>;
+	};
+
 	sata@70020000 {
 		compatible = "nvidia,tegra210-ahci";
 		reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
@@ -1431,6 +1452,18 @@
 		};
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		emc_table: emc-table@8be00000 {
+			compatible = "nvidia,tegra210-emc-table";
+			reg = <0x0 0x8be00000 0x0 0x10000>;
+			status = "disabled";
+		};
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13
-- 
2.21.0

WARNING: multiple messages have this Message-ID (diff)
From: Joseph Lo <josephl@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Rob Herring <robh+dt@kernel.org>, Stephen Boyd <sboyd@kernel.org>
Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	Joseph Lo <josephl@nvidia.com>
Subject: [PATCH V4 8/8] arm64: tegra: Add external memory controller node for Tegra210
Date: Wed, 29 May 2019 16:21:39 +0800	[thread overview]
Message-ID: <20190529082139.5581-9-josephl@nvidia.com> (raw)
In-Reply-To: <20190529082139.5581-1-josephl@nvidia.com>

Add external memory controller (EMC) node for Tegra210

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
v4:
- no change.
v3:
- apply memory-region for emc_table. And add reserved-memory node with
  it.
---
 arch/arm64/boot/dts/nvidia/tegra210.dtsi | 33 ++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index bc71ef8f9a09..b9ccfee39ed2 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -872,6 +872,27 @@
 		#iommu-cells = <1>;
 	};
 
+	external-memory-controller@7001b000 {
+		compatible = "nvidia,tegra210-emc";
+		reg = <0x0 0x7001b000 0x0 0x1000>,
+		      <0x0 0x7001e000 0x0 0x1000>,
+		      <0x0 0x7001f000 0x0 0x1000>;
+		clocks = <&tegra_car TEGRA210_CLK_EMC>,
+			 <&tegra_car TEGRA210_CLK_PLL_M>,
+			 <&tegra_car TEGRA210_CLK_PLL_C>,
+			 <&tegra_car TEGRA210_CLK_PLL_P>,
+			 <&tegra_car TEGRA210_CLK_CLK_M>,
+			 <&tegra_car TEGRA210_CLK_PLL_M_UD>,
+			 <&tegra_car TEGRA210_CLK_PLL_MB_UD>,
+			 <&tegra_car TEGRA210_CLK_PLL_MB>,
+			 <&tegra_car TEGRA210_CLK_PLL_P_UD>;
+		clock-names = "emc", "pll_m", "pll_c", "pll_p", "clk_m",
+			      "pll_m_ud", "pll_mb_ud", "pll_mb", "pll_p_ud";
+		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+		memory-region = <&emc_table>;
+		nvidia,memory-controller = <&mc>;
+	};
+
 	sata@70020000 {
 		compatible = "nvidia,tegra210-ahci";
 		reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
@@ -1431,6 +1452,18 @@
 		};
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		emc_table: emc-table@8be00000 {
+			compatible = "nvidia,tegra210-emc-table";
+			reg = <0x0 0x8be00000 0x0 0x10000>;
+			status = "disabled";
+		};
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13
-- 
2.21.0


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  parent reply	other threads:[~2019-05-29  8:22 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-29  8:21 [PATCH V4 0/8] Add EMC scaling support for Tegra210 Joseph Lo
2019-05-29  8:21 ` Joseph Lo
2019-05-29  8:21 ` Joseph Lo
2019-05-29  8:21 ` [PATCH V4 1/8] dt-bindings: memory: tegra: Add external memory controller binding " Joseph Lo
2019-05-29  8:21   ` Joseph Lo
2019-05-29  8:21   ` Joseph Lo
2019-05-29  8:21 ` [PATCH V4 2/8] clk: tegra: Add PLLP_UD and PLLMB_UD " Joseph Lo
2019-05-29  8:21   ` Joseph Lo
2019-05-29  8:21   ` Joseph Lo
2019-05-29  8:21 ` [PATCH V4 3/8] clk: tegra: Export functions for EMC clock scaling Joseph Lo
2019-05-29  8:21   ` Joseph Lo
2019-05-29  8:21   ` Joseph Lo
2019-05-29  8:21 ` [PATCH V4 4/8] memory: tegra: Add Tegra210 EMC clock driver Joseph Lo
2019-05-29  8:21   ` Joseph Lo
2019-05-29  8:21   ` Joseph Lo
2019-05-29 13:26   ` Dmitry Osipenko
2019-05-29 13:26     ` Dmitry Osipenko
2019-05-30  2:45     ` Joseph Lo
2019-05-30  2:45       ` Joseph Lo
2020-02-26 16:57       ` Thierry Reding
2020-02-26 16:57         ` Thierry Reding
2020-02-26 16:57         ` Thierry Reding
2020-02-27 15:18         ` Dmitry Osipenko
2020-02-27 15:18           ` Dmitry Osipenko
2020-02-27 15:18           ` Dmitry Osipenko
2019-05-29  8:21 ` [PATCH V4 5/8] memory: tegra: Add EMC scaling support code for Tegra210 Joseph Lo
2019-05-29  8:21   ` Joseph Lo
2019-05-29  8:21   ` Joseph Lo
2019-05-29 13:37   ` Dmitry Osipenko
2019-05-29 13:37     ` Dmitry Osipenko
2019-05-30  2:45     ` Joseph Lo
2019-05-30  2:45       ` Joseph Lo
2019-05-30 11:20   ` Dmitry Osipenko
2019-05-30 11:20     ` Dmitry Osipenko
2019-05-30 16:14   ` Dmitry Osipenko
2019-05-30 16:14     ` Dmitry Osipenko
2019-05-29  8:21 ` [PATCH V4 6/8] memory: tegra: Add EMC scaling sequence " Joseph Lo
2019-05-29  8:21   ` Joseph Lo
2019-05-29  8:21   ` Joseph Lo
2019-05-30 13:16   ` Dmitry Osipenko
2019-05-30 13:16     ` Dmitry Osipenko
2019-05-29  8:21 ` [PATCH V4 7/8] clk: tegra: Remove the old emc_mux clock " Joseph Lo
2019-05-29  8:21   ` Joseph Lo
2019-05-29  8:21   ` Joseph Lo
2019-05-29 12:49   ` Dmitry Osipenko
2019-05-29 12:49     ` Dmitry Osipenko
2019-05-30  2:06     ` Joseph Lo
2019-05-30  2:06       ` Joseph Lo
2019-05-29  8:21 ` Joseph Lo [this message]
2019-05-29  8:21   ` [PATCH V4 8/8] arm64: tegra: Add external memory controller node " Joseph Lo
2019-05-29  8:21   ` Joseph Lo

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