[PATCH 1/3] drm/i915/dsi: Move logging of DSI VBT parameters to a helper function

[PATCH 1/3] drm/i915/dsi: Move logging of DSI VBT parameters to a helper function

[Hans de Goede]

This is a preparation patch for moving the calling of *_dphy_param_init()
out of intel_dsi_vbt_init.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 drivers/gpu/drm/i915/intel_dsi_vbt.c | 77 +++++++++++++++-------------
 1 file changed, 42 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 4b8e48db1843..3a187ffabfbd 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -532,6 +532,44 @@ void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
 	msleep(msec);
 }
 
+static void intel_dsi_log_params(struct intel_dsi *intel_dsi)
+{
+	DRM_DEBUG_KMS("Pclk %d\n", intel_dsi->pclk);
+	DRM_DEBUG_KMS("Pixel overlap %d\n", intel_dsi->pixel_overlap);
+	DRM_DEBUG_KMS("Lane count %d\n", intel_dsi->lane_count);
+	DRM_DEBUG_KMS("DPHY param reg 0x%x\n", intel_dsi->dphy_reg);
+	DRM_DEBUG_KMS("Video mode format %s\n",
+		      intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ?
+		      "non-burst with sync pulse" :
+		      intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ?
+		      "non-burst with sync events" :
+		      intel_dsi->video_mode_format == VIDEO_MODE_BURST ?
+		      "burst" : "<unknown>");
+	DRM_DEBUG_KMS("Burst mode ratio %d\n", intel_dsi->burst_mode_ratio);
+	DRM_DEBUG_KMS("Reset timer %d\n", intel_dsi->rst_timer_val);
+	DRM_DEBUG_KMS("Eot %s\n", enableddisabled(intel_dsi->eotp_pkt));
+	DRM_DEBUG_KMS("Clockstop %s\n", enableddisabled(!intel_dsi->clock_stop));
+	DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
+	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
+		DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
+	else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
+		DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
+	else
+		DRM_DEBUG_KMS("Dual link: NONE\n");
+	DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
+	DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
+	DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
+	DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
+	DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count);
+	DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
+	DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
+	DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
+	DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count);
+	DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count);
+	DRM_DEBUG_KMS("BTA %s\n",
+			enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
+}
+
 #define ICL_PREPARE_CNT_MAX	0x7
 #define ICL_CLK_ZERO_CNT_MAX	0xf
 #define ICL_TRAIL_CNT_MAX	0x7
@@ -635,6 +673,8 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
 					 HS_TRAIL(trail_cnt) |
 					 HS_EXIT_OVERRIDE |
 					 HS_EXIT(exit_zero_cnt));
+
+	intel_dsi_log_params(intel_dsi);
 }
 
 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
@@ -794,6 +834,8 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
 		DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
 			8);
 	intel_dsi->clk_hs_to_lp_count += extra_byte_count;
+
+	intel_dsi_log_params(intel_dsi);
 }
 
 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
@@ -888,41 +930,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	else
 		vlv_dphy_param_init(intel_dsi);
 
-	DRM_DEBUG_KMS("Pclk %d\n", intel_dsi->pclk);
-	DRM_DEBUG_KMS("Pixel overlap %d\n", intel_dsi->pixel_overlap);
-	DRM_DEBUG_KMS("Lane count %d\n", intel_dsi->lane_count);
-	DRM_DEBUG_KMS("DPHY param reg 0x%x\n", intel_dsi->dphy_reg);
-	DRM_DEBUG_KMS("Video mode format %s\n",
-		      intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ?
-		      "non-burst with sync pulse" :
-		      intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ?
-		      "non-burst with sync events" :
-		      intel_dsi->video_mode_format == VIDEO_MODE_BURST ?
-		      "burst" : "<unknown>");
-	DRM_DEBUG_KMS("Burst mode ratio %d\n", intel_dsi->burst_mode_ratio);
-	DRM_DEBUG_KMS("Reset timer %d\n", intel_dsi->rst_timer_val);
-	DRM_DEBUG_KMS("Eot %s\n", enableddisabled(intel_dsi->eotp_pkt));
-	DRM_DEBUG_KMS("Clockstop %s\n", enableddisabled(!intel_dsi->clock_stop));
-	DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
-	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
-		DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
-	else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
-		DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
-	else
-		DRM_DEBUG_KMS("Dual link: NONE\n");
-	DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
-	DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
-	DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
-	DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
-	DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count);
-	DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
-	DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
-	DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
-	DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count);
-	DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count);
-	DRM_DEBUG_KMS("BTA %s\n",
-			enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
-
 	/* delays in VBT are in unit of 100us, so need to convert
 	 * here in ms
 	 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 2/3] drm/i915/dsi: Move vlv/icl_dphy_param_init call out of intel_dsi_vbt_init (v2)

[Hans de Goede]

The vlv/icl_dphy_param_init calls do various calculations to set dphy
parameters based on the pclk.

Move the calling of vlv/icl_dphy_param_init to vlv_dsi_init to give
vlv_dsi_init a chance to tweak the pclk before these calculations are done.

Changes in v2:
-Also moves the icl and vlv specific dphy_param_init functions from the
 generic intel_dsi_vbt.c file into the icl_ and vlv_dsi.c specific files.

Note icl_dphy_param_init() and vlv_dphy_param_init() are only moved,
otherwise they are completely unchanged.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 drivers/gpu/drm/i915/icl_dsi.c       | 108 ++++++++++
 drivers/gpu/drm/i915/intel_dsi.h     |   1 +
 drivers/gpu/drm/i915/intel_dsi_vbt.c | 282 +--------------------------
 drivers/gpu/drm/i915/vlv_dsi.c       | 170 ++++++++++++++++
 4 files changed, 280 insertions(+), 281 deletions(-)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 9d962ea1e635..511c76e788ef 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1363,6 +1363,113 @@ static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
 	.transfer = gen11_dsi_host_transfer,
 };
 
+#define ICL_PREPARE_CNT_MAX	0x7
+#define ICL_CLK_ZERO_CNT_MAX	0xf
+#define ICL_TRAIL_CNT_MAX	0x7
+#define ICL_TCLK_PRE_CNT_MAX	0x3
+#define ICL_TCLK_POST_CNT_MAX	0x7
+#define ICL_HS_ZERO_CNT_MAX	0xf
+#define ICL_EXIT_ZERO_CNT_MAX	0x7
+
+static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
+{
+	struct drm_device *dev = intel_dsi->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
+	u32 tlpx_ns;
+	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
+	u32 ths_prepare_ns, tclk_trail_ns;
+	u32 hs_zero_cnt;
+	u32 tclk_pre_cnt, tclk_post_cnt;
+
+	tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
+
+	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
+	ths_prepare_ns = max(mipi_config->ths_prepare,
+			     mipi_config->tclk_prepare);
+
+	/*
+	 * prepare cnt in escape clocks
+	 * this field represents a hexadecimal value with a precision
+	 * of 1.2 – i.e. the most significant bit is the integer
+	 * and the least significant 2 bits are fraction bits.
+	 * so, the field can represent a range of 0.25 to 1.75
+	 */
+	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
+	if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
+		DRM_DEBUG_KMS("prepare_cnt out of range (%d)\n", prepare_cnt);
+		prepare_cnt = ICL_PREPARE_CNT_MAX;
+	}
+
+	/* clk zero count in escape clocks */
+	clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
+				    ths_prepare_ns, tlpx_ns);
+	if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
+		DRM_DEBUG_KMS("clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
+		clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
+	}
+
+	/* trail cnt in escape clocks*/
+	trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
+	if (trail_cnt > ICL_TRAIL_CNT_MAX) {
+		DRM_DEBUG_KMS("trail_cnt out of range (%d)\n", trail_cnt);
+		trail_cnt = ICL_TRAIL_CNT_MAX;
+	}
+
+	/* tclk pre count in escape clocks */
+	tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
+	if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
+		DRM_DEBUG_KMS("tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
+		tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
+	}
+
+	/* tclk post count in escape clocks */
+	tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns);
+	if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) {
+		DRM_DEBUG_KMS("tclk_post_cnt out of range (%d)\n", tclk_post_cnt);
+		tclk_post_cnt = ICL_TCLK_POST_CNT_MAX;
+	}
+
+	/* hs zero cnt in escape clocks */
+	hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
+				   ths_prepare_ns, tlpx_ns);
+	if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
+		DRM_DEBUG_KMS("hs_zero_cnt out of range (%d)\n", hs_zero_cnt);
+		hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
+	}
+
+	/* hs exit zero cnt in escape clocks */
+	exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
+	if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
+		DRM_DEBUG_KMS("exit_zero_cnt out of range (%d)\n", exit_zero_cnt);
+		exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
+	}
+
+	/* clock lane dphy timings */
+	intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
+			       CLK_PREPARE(prepare_cnt) |
+			       CLK_ZERO_OVERRIDE |
+			       CLK_ZERO(clk_zero_cnt) |
+			       CLK_PRE_OVERRIDE |
+			       CLK_PRE(tclk_pre_cnt) |
+			       CLK_POST_OVERRIDE |
+			       CLK_POST(tclk_post_cnt) |
+			       CLK_TRAIL_OVERRIDE |
+			       CLK_TRAIL(trail_cnt));
+
+	/* data lanes dphy timings */
+	intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
+					 HS_PREPARE(prepare_cnt) |
+					 HS_ZERO_OVERRIDE |
+					 HS_ZERO(hs_zero_cnt) |
+					 HS_TRAIL_OVERRIDE |
+					 HS_TRAIL(trail_cnt) |
+					 HS_EXIT_OVERRIDE |
+					 HS_EXIT(exit_zero_cnt));
+
+	intel_dsi_log_params(intel_dsi);
+}
+
 void icl_dsi_init(struct drm_i915_private *dev_priv)
 {
 	struct drm_device *dev = &dev_priv->drm;
@@ -1455,6 +1562,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
 		goto err;
 	}
 
+	icl_dphy_param_init(intel_dsi);
 	return;
 
 err:
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 705a609050c0..2e997187fed5 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -192,5 +192,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
 				 enum mipi_seq seq_id);
 void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec);
+void intel_dsi_log_params(struct intel_dsi *intel_dsi);
 
 #endif /* _INTEL_DSI_H */
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 3a187ffabfbd..26fcb3344ebb 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -41,13 +41,6 @@
 #define MIPI_VIRTUAL_CHANNEL_SHIFT	1
 #define MIPI_PORT_SHIFT			3
 
-#define PREPARE_CNT_MAX		0x3F
-#define EXIT_ZERO_CNT_MAX	0x3F
-#define CLK_ZERO_CNT_MAX	0xFF
-#define TRAIL_CNT_MAX		0x1F
-
-#define NS_KHZ_RATIO 1000000
-
 /* base offsets for gpio pads */
 #define VLV_GPIO_NC_0_HV_DDI0_HPD	0x4130
 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA	0x4120
@@ -532,7 +525,7 @@ void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
 	msleep(msec);
 }
 
-static void intel_dsi_log_params(struct intel_dsi *intel_dsi)
+void intel_dsi_log_params(struct intel_dsi *intel_dsi)
 {
 	DRM_DEBUG_KMS("Pclk %d\n", intel_dsi->pclk);
 	DRM_DEBUG_KMS("Pixel overlap %d\n", intel_dsi->pixel_overlap);
@@ -570,274 +563,6 @@ static void intel_dsi_log_params(struct intel_dsi *intel_dsi)
 			enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
 }
 
-#define ICL_PREPARE_CNT_MAX	0x7
-#define ICL_CLK_ZERO_CNT_MAX	0xf
-#define ICL_TRAIL_CNT_MAX	0x7
-#define ICL_TCLK_PRE_CNT_MAX	0x3
-#define ICL_TCLK_POST_CNT_MAX	0x7
-#define ICL_HS_ZERO_CNT_MAX	0xf
-#define ICL_EXIT_ZERO_CNT_MAX	0x7
-
-static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
-{
-	struct drm_device *dev = intel_dsi->base.base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
-	u32 tlpx_ns;
-	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
-	u32 ths_prepare_ns, tclk_trail_ns;
-	u32 hs_zero_cnt;
-	u32 tclk_pre_cnt, tclk_post_cnt;
-
-	tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
-
-	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
-	ths_prepare_ns = max(mipi_config->ths_prepare,
-			     mipi_config->tclk_prepare);
-
-	/*
-	 * prepare cnt in escape clocks
-	 * this field represents a hexadecimal value with a precision
-	 * of 1.2 – i.e. the most significant bit is the integer
-	 * and the least significant 2 bits are fraction bits.
-	 * so, the field can represent a range of 0.25 to 1.75
-	 */
-	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
-	if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
-		DRM_DEBUG_KMS("prepare_cnt out of range (%d)\n", prepare_cnt);
-		prepare_cnt = ICL_PREPARE_CNT_MAX;
-	}
-
-	/* clk zero count in escape clocks */
-	clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
-				    ths_prepare_ns, tlpx_ns);
-	if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
-		DRM_DEBUG_KMS("clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
-		clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
-	}
-
-	/* trail cnt in escape clocks*/
-	trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
-	if (trail_cnt > ICL_TRAIL_CNT_MAX) {
-		DRM_DEBUG_KMS("trail_cnt out of range (%d)\n", trail_cnt);
-		trail_cnt = ICL_TRAIL_CNT_MAX;
-	}
-
-	/* tclk pre count in escape clocks */
-	tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
-	if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
-		DRM_DEBUG_KMS("tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
-		tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
-	}
-
-	/* tclk post count in escape clocks */
-	tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns);
-	if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) {
-		DRM_DEBUG_KMS("tclk_post_cnt out of range (%d)\n", tclk_post_cnt);
-		tclk_post_cnt = ICL_TCLK_POST_CNT_MAX;
-	}
-
-	/* hs zero cnt in escape clocks */
-	hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
-				   ths_prepare_ns, tlpx_ns);
-	if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
-		DRM_DEBUG_KMS("hs_zero_cnt out of range (%d)\n", hs_zero_cnt);
-		hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
-	}
-
-	/* hs exit zero cnt in escape clocks */
-	exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
-	if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
-		DRM_DEBUG_KMS("exit_zero_cnt out of range (%d)\n", exit_zero_cnt);
-		exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
-	}
-
-	/* clock lane dphy timings */
-	intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
-			       CLK_PREPARE(prepare_cnt) |
-			       CLK_ZERO_OVERRIDE |
-			       CLK_ZERO(clk_zero_cnt) |
-			       CLK_PRE_OVERRIDE |
-			       CLK_PRE(tclk_pre_cnt) |
-			       CLK_POST_OVERRIDE |
-			       CLK_POST(tclk_post_cnt) |
-			       CLK_TRAIL_OVERRIDE |
-			       CLK_TRAIL(trail_cnt));
-
-	/* data lanes dphy timings */
-	intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
-					 HS_PREPARE(prepare_cnt) |
-					 HS_ZERO_OVERRIDE |
-					 HS_ZERO(hs_zero_cnt) |
-					 HS_TRAIL_OVERRIDE |
-					 HS_TRAIL(trail_cnt) |
-					 HS_EXIT_OVERRIDE |
-					 HS_EXIT(exit_zero_cnt));
-
-	intel_dsi_log_params(intel_dsi);
-}
-
-static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
-{
-	struct drm_device *dev = intel_dsi->base.base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
-	u32 tlpx_ns, extra_byte_count, tlpx_ui;
-	u32 ui_num, ui_den;
-	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
-	u32 ths_prepare_ns, tclk_trail_ns;
-	u32 tclk_prepare_clkzero, ths_prepare_hszero;
-	u32 lp_to_hs_switch, hs_to_lp_switch;
-	u32 mul;
-
-	tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
-
-	switch (intel_dsi->lane_count) {
-	case 1:
-	case 2:
-		extra_byte_count = 2;
-		break;
-	case 3:
-		extra_byte_count = 4;
-		break;
-	case 4:
-	default:
-		extra_byte_count = 3;
-		break;
-	}
-
-	/* in Kbps */
-	ui_num = NS_KHZ_RATIO;
-	ui_den = intel_dsi_bitrate(intel_dsi);
-
-	tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
-	ths_prepare_hszero = mipi_config->ths_prepare_hszero;
-
-	/*
-	 * B060
-	 * LP byte clock = TLPX/ (8UI)
-	 */
-	intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
-
-	/* DDR clock period = 2 * UI
-	 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
-	 * UI(nsec) = 10^6 / bitrate
-	 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
-	 * DDR clock count  = ns_value / DDR clock period
-	 *
-	 * For GEMINILAKE dphy_param_reg will be programmed in terms of
-	 * HS byte clock count for other platform in HS ddr clock count
-	 */
-	mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
-	ths_prepare_ns = max(mipi_config->ths_prepare,
-			     mipi_config->tclk_prepare);
-
-	/* prepare count */
-	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
-
-	if (prepare_cnt > PREPARE_CNT_MAX) {
-		DRM_DEBUG_KMS("prepare count too high %u\n", prepare_cnt);
-		prepare_cnt = PREPARE_CNT_MAX;
-	}
-
-	/* exit zero count */
-	exit_zero_cnt = DIV_ROUND_UP(
-				(ths_prepare_hszero - ths_prepare_ns) * ui_den,
-				ui_num * mul
-				);
-
-	/*
-	 * Exit zero is unified val ths_zero and ths_exit
-	 * minimum value for ths_exit = 110ns
-	 * min (exit_zero_cnt * 2) = 110/UI
-	 * exit_zero_cnt = 55/UI
-	 */
-	if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
-		exit_zero_cnt += 1;
-
-	if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
-		DRM_DEBUG_KMS("exit zero count too high %u\n", exit_zero_cnt);
-		exit_zero_cnt = EXIT_ZERO_CNT_MAX;
-	}
-
-	/* clk zero count */
-	clk_zero_cnt = DIV_ROUND_UP(
-				(tclk_prepare_clkzero -	ths_prepare_ns)
-				* ui_den, ui_num * mul);
-
-	if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
-		DRM_DEBUG_KMS("clock zero count too high %u\n", clk_zero_cnt);
-		clk_zero_cnt = CLK_ZERO_CNT_MAX;
-	}
-
-	/* trail count */
-	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
-	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
-
-	if (trail_cnt > TRAIL_CNT_MAX) {
-		DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt);
-		trail_cnt = TRAIL_CNT_MAX;
-	}
-
-	/* B080 */
-	intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
-						clk_zero_cnt << 8 | prepare_cnt;
-
-	/*
-	 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
-	 *					mul + 10UI + Extra Byte Count
-	 *
-	 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
-	 * Extra Byte Count is calculated according to number of lanes.
-	 * High Low Switch Count is the Max of LP to HS and
-	 * HS to LP switch count
-	 *
-	 */
-	tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
-
-	/* B044 */
-	/* FIXME:
-	 * The comment above does not match with the code */
-	lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
-						exit_zero_cnt * mul + 10, 8);
-
-	hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
-
-	intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
-	intel_dsi->hs_to_lp_count += extra_byte_count;
-
-	/* B088 */
-	/* LP -> HS for clock lanes
-	 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
-	 *						extra byte count
-	 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
-	 *					2(in UI) + extra byte count
-	 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
-	 *					8 + extra byte count
-	 */
-	intel_dsi->clk_lp_to_hs_count =
-		DIV_ROUND_UP(
-			4 * tlpx_ui + prepare_cnt * 2 +
-			clk_zero_cnt * 2,
-			8);
-
-	intel_dsi->clk_lp_to_hs_count += extra_byte_count;
-
-	/* HS->LP for Clock Lanes
-	 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
-	 *						Extra byte count
-	 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
-	 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
-	 *						Extra byte count
-	 */
-	intel_dsi->clk_hs_to_lp_count =
-		DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
-			8);
-	intel_dsi->clk_hs_to_lp_count += extra_byte_count;
-
-	intel_dsi_log_params(intel_dsi);
-}
-
 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 {
 	struct drm_device *dev = intel_dsi->base.base.dev;
@@ -925,11 +650,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 
 	intel_dsi->burst_mode_ratio = burst_mode_ratio;
 
-	if (INTEL_GEN(dev_priv) >= 11)
-		icl_dphy_param_init(intel_dsi);
-	else
-		vlv_dphy_param_init(intel_dsi);
-
 	/* delays in VBT are in unit of 100us, so need to convert
 	 * here in ms
 	 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
index 255996a71b91..59500c838b9d 100644
--- a/drivers/gpu/drm/i915/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/vlv_dsi.c
@@ -1689,6 +1689,174 @@ static void intel_dsi_add_properties(struct intel_connector *connector)
 	}
 }
 
+#define NS_KHZ_RATIO		1000000
+
+#define PREPARE_CNT_MAX		0x3F
+#define EXIT_ZERO_CNT_MAX	0x3F
+#define CLK_ZERO_CNT_MAX	0xFF
+#define TRAIL_CNT_MAX		0x1F
+
+static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
+{
+	struct drm_device *dev = intel_dsi->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
+	u32 tlpx_ns, extra_byte_count, tlpx_ui;
+	u32 ui_num, ui_den;
+	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
+	u32 ths_prepare_ns, tclk_trail_ns;
+	u32 tclk_prepare_clkzero, ths_prepare_hszero;
+	u32 lp_to_hs_switch, hs_to_lp_switch;
+	u32 mul;
+
+	tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
+
+	switch (intel_dsi->lane_count) {
+	case 1:
+	case 2:
+		extra_byte_count = 2;
+		break;
+	case 3:
+		extra_byte_count = 4;
+		break;
+	case 4:
+	default:
+		extra_byte_count = 3;
+		break;
+	}
+
+	/* in Kbps */
+	ui_num = NS_KHZ_RATIO;
+	ui_den = intel_dsi_bitrate(intel_dsi);
+
+	tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
+	ths_prepare_hszero = mipi_config->ths_prepare_hszero;
+
+	/*
+	 * B060
+	 * LP byte clock = TLPX/ (8UI)
+	 */
+	intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
+
+	/* DDR clock period = 2 * UI
+	 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
+	 * UI(nsec) = 10^6 / bitrate
+	 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
+	 * DDR clock count  = ns_value / DDR clock period
+	 *
+	 * For GEMINILAKE dphy_param_reg will be programmed in terms of
+	 * HS byte clock count for other platform in HS ddr clock count
+	 */
+	mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
+	ths_prepare_ns = max(mipi_config->ths_prepare,
+			     mipi_config->tclk_prepare);
+
+	/* prepare count */
+	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
+
+	if (prepare_cnt > PREPARE_CNT_MAX) {
+		DRM_DEBUG_KMS("prepare count too high %u\n", prepare_cnt);
+		prepare_cnt = PREPARE_CNT_MAX;
+	}
+
+	/* exit zero count */
+	exit_zero_cnt = DIV_ROUND_UP(
+				(ths_prepare_hszero - ths_prepare_ns) * ui_den,
+				ui_num * mul
+				);
+
+	/*
+	 * Exit zero is unified val ths_zero and ths_exit
+	 * minimum value for ths_exit = 110ns
+	 * min (exit_zero_cnt * 2) = 110/UI
+	 * exit_zero_cnt = 55/UI
+	 */
+	if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
+		exit_zero_cnt += 1;
+
+	if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
+		DRM_DEBUG_KMS("exit zero count too high %u\n", exit_zero_cnt);
+		exit_zero_cnt = EXIT_ZERO_CNT_MAX;
+	}
+
+	/* clk zero count */
+	clk_zero_cnt = DIV_ROUND_UP(
+				(tclk_prepare_clkzero -	ths_prepare_ns)
+				* ui_den, ui_num * mul);
+
+	if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
+		DRM_DEBUG_KMS("clock zero count too high %u\n", clk_zero_cnt);
+		clk_zero_cnt = CLK_ZERO_CNT_MAX;
+	}
+
+	/* trail count */
+	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
+	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
+
+	if (trail_cnt > TRAIL_CNT_MAX) {
+		DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt);
+		trail_cnt = TRAIL_CNT_MAX;
+	}
+
+	/* B080 */
+	intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
+						clk_zero_cnt << 8 | prepare_cnt;
+
+	/*
+	 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
+	 *					mul + 10UI + Extra Byte Count
+	 *
+	 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
+	 * Extra Byte Count is calculated according to number of lanes.
+	 * High Low Switch Count is the Max of LP to HS and
+	 * HS to LP switch count
+	 *
+	 */
+	tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
+
+	/* B044 */
+	/* FIXME:
+	 * The comment above does not match with the code */
+	lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
+						exit_zero_cnt * mul + 10, 8);
+
+	hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
+
+	intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
+	intel_dsi->hs_to_lp_count += extra_byte_count;
+
+	/* B088 */
+	/* LP -> HS for clock lanes
+	 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
+	 *						extra byte count
+	 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
+	 *					2(in UI) + extra byte count
+	 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
+	 *					8 + extra byte count
+	 */
+	intel_dsi->clk_lp_to_hs_count =
+		DIV_ROUND_UP(
+			4 * tlpx_ui + prepare_cnt * 2 +
+			clk_zero_cnt * 2,
+			8);
+
+	intel_dsi->clk_lp_to_hs_count += extra_byte_count;
+
+	/* HS->LP for Clock Lanes
+	 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
+	 *						Extra byte count
+	 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
+	 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
+	 *						Extra byte count
+	 */
+	intel_dsi->clk_hs_to_lp_count =
+		DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
+			8);
+	intel_dsi->clk_hs_to_lp_count += extra_byte_count;
+
+	intel_dsi_log_params(intel_dsi);
+}
+
 void vlv_dsi_init(struct drm_i915_private *dev_priv)
 {
 	struct drm_device *dev = &dev_priv->drm;
@@ -1778,6 +1946,8 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
 		goto err;
 	}
 
+	vlv_dphy_param_init(intel_dsi);
+
 	/*
 	 * In case of BYT with CRC PMIC, we need to use GPIO for
 	 * Panel control.
-- 
2.21.0

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH 2/3] drm/i915/dsi: Move vlv/icl_dphy_param_init call out of intel_dsi_vbt_init (v2)

[Ville Syrjälä]

On Wed, Jun 05, 2019 at 08:17:34PM +0200, Hans de Goede wrote:
> The vlv/icl_dphy_param_init calls do various calculations to set dphy
> parameters based on the pclk.
> 
> Move the calling of vlv/icl_dphy_param_init to vlv_dsi_init to give
> vlv_dsi_init a chance to tweak the pclk before these calculations are done.
> 
> Changes in v2:
> -Also moves the icl and vlv specific dphy_param_init functions from the
>  generic intel_dsi_vbt.c file into the icl_ and vlv_dsi.c specific files.
> 
> Note icl_dphy_param_init() and vlv_dphy_param_init() are only moved,
> otherwise they are completely unchanged.
> 
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/icl_dsi.c       | 108 ++++++++++
>  drivers/gpu/drm/i915/intel_dsi.h     |   1 +
>  drivers/gpu/drm/i915/intel_dsi_vbt.c | 282 +--------------------------
>  drivers/gpu/drm/i915/vlv_dsi.c       | 170 ++++++++++++++++
>  4 files changed, 280 insertions(+), 281 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index 9d962ea1e635..511c76e788ef 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -1363,6 +1363,113 @@ static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
>  	.transfer = gen11_dsi_host_transfer,
>  };
>  
> +#define ICL_PREPARE_CNT_MAX	0x7
> +#define ICL_CLK_ZERO_CNT_MAX	0xf
> +#define ICL_TRAIL_CNT_MAX	0x7
> +#define ICL_TCLK_PRE_CNT_MAX	0x3
> +#define ICL_TCLK_POST_CNT_MAX	0x7
> +#define ICL_HS_ZERO_CNT_MAX	0xf
> +#define ICL_EXIT_ZERO_CNT_MAX	0x7
> +
> +static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
> +{
> +	struct drm_device *dev = intel_dsi->base.base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
> +	u32 tlpx_ns;
> +	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
> +	u32 ths_prepare_ns, tclk_trail_ns;
> +	u32 hs_zero_cnt;
> +	u32 tclk_pre_cnt, tclk_post_cnt;
> +
> +	tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
> +
> +	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
> +	ths_prepare_ns = max(mipi_config->ths_prepare,
> +			     mipi_config->tclk_prepare);
> +
> +	/*
> +	 * prepare cnt in escape clocks
> +	 * this field represents a hexadecimal value with a precision
> +	 * of 1.2 – i.e. the most significant bit is the integer
> +	 * and the least significant 2 bits are fraction bits.
> +	 * so, the field can represent a range of 0.25 to 1.75
> +	 */
> +	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
> +	if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
> +		DRM_DEBUG_KMS("prepare_cnt out of range (%d)\n", prepare_cnt);
> +		prepare_cnt = ICL_PREPARE_CNT_MAX;
> +	}
> +
> +	/* clk zero count in escape clocks */
> +	clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
> +				    ths_prepare_ns, tlpx_ns);
> +	if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
> +		DRM_DEBUG_KMS("clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
> +		clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
> +	}
> +
> +	/* trail cnt in escape clocks*/
> +	trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
> +	if (trail_cnt > ICL_TRAIL_CNT_MAX) {
> +		DRM_DEBUG_KMS("trail_cnt out of range (%d)\n", trail_cnt);
> +		trail_cnt = ICL_TRAIL_CNT_MAX;
> +	}
> +
> +	/* tclk pre count in escape clocks */
> +	tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
> +	if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
> +		DRM_DEBUG_KMS("tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
> +		tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
> +	}
> +
> +	/* tclk post count in escape clocks */
> +	tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns);
> +	if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) {
> +		DRM_DEBUG_KMS("tclk_post_cnt out of range (%d)\n", tclk_post_cnt);
> +		tclk_post_cnt = ICL_TCLK_POST_CNT_MAX;
> +	}
> +
> +	/* hs zero cnt in escape clocks */
> +	hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
> +				   ths_prepare_ns, tlpx_ns);
> +	if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
> +		DRM_DEBUG_KMS("hs_zero_cnt out of range (%d)\n", hs_zero_cnt);
> +		hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
> +	}
> +
> +	/* hs exit zero cnt in escape clocks */
> +	exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
> +	if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
> +		DRM_DEBUG_KMS("exit_zero_cnt out of range (%d)\n", exit_zero_cnt);
> +		exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
> +	}
> +
> +	/* clock lane dphy timings */
> +	intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
> +			       CLK_PREPARE(prepare_cnt) |
> +			       CLK_ZERO_OVERRIDE |
> +			       CLK_ZERO(clk_zero_cnt) |
> +			       CLK_PRE_OVERRIDE |
> +			       CLK_PRE(tclk_pre_cnt) |
> +			       CLK_POST_OVERRIDE |
> +			       CLK_POST(tclk_post_cnt) |
> +			       CLK_TRAIL_OVERRIDE |
> +			       CLK_TRAIL(trail_cnt));
> +
> +	/* data lanes dphy timings */
> +	intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
> +					 HS_PREPARE(prepare_cnt) |
> +					 HS_ZERO_OVERRIDE |
> +					 HS_ZERO(hs_zero_cnt) |
> +					 HS_TRAIL_OVERRIDE |
> +					 HS_TRAIL(trail_cnt) |
> +					 HS_EXIT_OVERRIDE |
> +					 HS_EXIT(exit_zero_cnt));
> +
> +	intel_dsi_log_params(intel_dsi);
> +}
> +
>  void icl_dsi_init(struct drm_i915_private *dev_priv)
>  {
>  	struct drm_device *dev = &dev_priv->drm;
> @@ -1455,6 +1562,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
>  		goto err;
>  	}
>  
> +	icl_dphy_param_init(intel_dsi);
>  	return;
>  
>  err:
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index 705a609050c0..2e997187fed5 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -192,5 +192,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
>  void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
>  				 enum mipi_seq seq_id);
>  void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec);
> +void intel_dsi_log_params(struct intel_dsi *intel_dsi);
>  
>  #endif /* _INTEL_DSI_H */
> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> index 3a187ffabfbd..26fcb3344ebb 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> @@ -41,13 +41,6 @@
>  #define MIPI_VIRTUAL_CHANNEL_SHIFT	1
>  #define MIPI_PORT_SHIFT			3
>  
> -#define PREPARE_CNT_MAX		0x3F
> -#define EXIT_ZERO_CNT_MAX	0x3F
> -#define CLK_ZERO_CNT_MAX	0xFF
> -#define TRAIL_CNT_MAX		0x1F
> -
> -#define NS_KHZ_RATIO 1000000
> -
>  /* base offsets for gpio pads */
>  #define VLV_GPIO_NC_0_HV_DDI0_HPD	0x4130
>  #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA	0x4120
> @@ -532,7 +525,7 @@ void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
>  	msleep(msec);
>  }
>  
> -static void intel_dsi_log_params(struct intel_dsi *intel_dsi)
> +void intel_dsi_log_params(struct intel_dsi *intel_dsi)
>  {
>  	DRM_DEBUG_KMS("Pclk %d\n", intel_dsi->pclk);
>  	DRM_DEBUG_KMS("Pixel overlap %d\n", intel_dsi->pixel_overlap);
> @@ -570,274 +563,6 @@ static void intel_dsi_log_params(struct intel_dsi *intel_dsi)
>  			enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
>  }
>  
> -#define ICL_PREPARE_CNT_MAX	0x7
> -#define ICL_CLK_ZERO_CNT_MAX	0xf
> -#define ICL_TRAIL_CNT_MAX	0x7
> -#define ICL_TCLK_PRE_CNT_MAX	0x3
> -#define ICL_TCLK_POST_CNT_MAX	0x7
> -#define ICL_HS_ZERO_CNT_MAX	0xf
> -#define ICL_EXIT_ZERO_CNT_MAX	0x7
> -
> -static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
> -{
> -	struct drm_device *dev = intel_dsi->base.base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
> -	u32 tlpx_ns;
> -	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
> -	u32 ths_prepare_ns, tclk_trail_ns;
> -	u32 hs_zero_cnt;
> -	u32 tclk_pre_cnt, tclk_post_cnt;
> -
> -	tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
> -
> -	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
> -	ths_prepare_ns = max(mipi_config->ths_prepare,
> -			     mipi_config->tclk_prepare);
> -
> -	/*
> -	 * prepare cnt in escape clocks
> -	 * this field represents a hexadecimal value with a precision
> -	 * of 1.2 – i.e. the most significant bit is the integer
> -	 * and the least significant 2 bits are fraction bits.
> -	 * so, the field can represent a range of 0.25 to 1.75
> -	 */
> -	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
> -	if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
> -		DRM_DEBUG_KMS("prepare_cnt out of range (%d)\n", prepare_cnt);
> -		prepare_cnt = ICL_PREPARE_CNT_MAX;
> -	}
> -
> -	/* clk zero count in escape clocks */
> -	clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
> -				    ths_prepare_ns, tlpx_ns);
> -	if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
> -		DRM_DEBUG_KMS("clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
> -		clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
> -	}
> -
> -	/* trail cnt in escape clocks*/
> -	trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
> -	if (trail_cnt > ICL_TRAIL_CNT_MAX) {
> -		DRM_DEBUG_KMS("trail_cnt out of range (%d)\n", trail_cnt);
> -		trail_cnt = ICL_TRAIL_CNT_MAX;
> -	}
> -
> -	/* tclk pre count in escape clocks */
> -	tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
> -	if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
> -		DRM_DEBUG_KMS("tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
> -		tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
> -	}
> -
> -	/* tclk post count in escape clocks */
> -	tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns);
> -	if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) {
> -		DRM_DEBUG_KMS("tclk_post_cnt out of range (%d)\n", tclk_post_cnt);
> -		tclk_post_cnt = ICL_TCLK_POST_CNT_MAX;
> -	}
> -
> -	/* hs zero cnt in escape clocks */
> -	hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
> -				   ths_prepare_ns, tlpx_ns);
> -	if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
> -		DRM_DEBUG_KMS("hs_zero_cnt out of range (%d)\n", hs_zero_cnt);
> -		hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
> -	}
> -
> -	/* hs exit zero cnt in escape clocks */
> -	exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
> -	if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
> -		DRM_DEBUG_KMS("exit_zero_cnt out of range (%d)\n", exit_zero_cnt);
> -		exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
> -	}
> -
> -	/* clock lane dphy timings */
> -	intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
> -			       CLK_PREPARE(prepare_cnt) |
> -			       CLK_ZERO_OVERRIDE |
> -			       CLK_ZERO(clk_zero_cnt) |
> -			       CLK_PRE_OVERRIDE |
> -			       CLK_PRE(tclk_pre_cnt) |
> -			       CLK_POST_OVERRIDE |
> -			       CLK_POST(tclk_post_cnt) |
> -			       CLK_TRAIL_OVERRIDE |
> -			       CLK_TRAIL(trail_cnt));
> -
> -	/* data lanes dphy timings */
> -	intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
> -					 HS_PREPARE(prepare_cnt) |
> -					 HS_ZERO_OVERRIDE |
> -					 HS_ZERO(hs_zero_cnt) |
> -					 HS_TRAIL_OVERRIDE |
> -					 HS_TRAIL(trail_cnt) |
> -					 HS_EXIT_OVERRIDE |
> -					 HS_EXIT(exit_zero_cnt));
> -
> -	intel_dsi_log_params(intel_dsi);
> -}
> -
> -static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
> -{
> -	struct drm_device *dev = intel_dsi->base.base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
> -	u32 tlpx_ns, extra_byte_count, tlpx_ui;
> -	u32 ui_num, ui_den;
> -	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
> -	u32 ths_prepare_ns, tclk_trail_ns;
> -	u32 tclk_prepare_clkzero, ths_prepare_hszero;
> -	u32 lp_to_hs_switch, hs_to_lp_switch;
> -	u32 mul;
> -
> -	tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
> -
> -	switch (intel_dsi->lane_count) {
> -	case 1:
> -	case 2:
> -		extra_byte_count = 2;
> -		break;
> -	case 3:
> -		extra_byte_count = 4;
> -		break;
> -	case 4:
> -	default:
> -		extra_byte_count = 3;
> -		break;
> -	}
> -
> -	/* in Kbps */
> -	ui_num = NS_KHZ_RATIO;
> -	ui_den = intel_dsi_bitrate(intel_dsi);
> -
> -	tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
> -	ths_prepare_hszero = mipi_config->ths_prepare_hszero;
> -
> -	/*
> -	 * B060
> -	 * LP byte clock = TLPX/ (8UI)
> -	 */
> -	intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
> -
> -	/* DDR clock period = 2 * UI
> -	 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
> -	 * UI(nsec) = 10^6 / bitrate
> -	 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
> -	 * DDR clock count  = ns_value / DDR clock period
> -	 *
> -	 * For GEMINILAKE dphy_param_reg will be programmed in terms of
> -	 * HS byte clock count for other platform in HS ddr clock count
> -	 */
> -	mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
> -	ths_prepare_ns = max(mipi_config->ths_prepare,
> -			     mipi_config->tclk_prepare);
> -
> -	/* prepare count */
> -	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
> -
> -	if (prepare_cnt > PREPARE_CNT_MAX) {
> -		DRM_DEBUG_KMS("prepare count too high %u\n", prepare_cnt);
> -		prepare_cnt = PREPARE_CNT_MAX;
> -	}
> -
> -	/* exit zero count */
> -	exit_zero_cnt = DIV_ROUND_UP(
> -				(ths_prepare_hszero - ths_prepare_ns) * ui_den,
> -				ui_num * mul
> -				);
> -
> -	/*
> -	 * Exit zero is unified val ths_zero and ths_exit
> -	 * minimum value for ths_exit = 110ns
> -	 * min (exit_zero_cnt * 2) = 110/UI
> -	 * exit_zero_cnt = 55/UI
> -	 */
> -	if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
> -		exit_zero_cnt += 1;
> -
> -	if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
> -		DRM_DEBUG_KMS("exit zero count too high %u\n", exit_zero_cnt);
> -		exit_zero_cnt = EXIT_ZERO_CNT_MAX;
> -	}
> -
> -	/* clk zero count */
> -	clk_zero_cnt = DIV_ROUND_UP(
> -				(tclk_prepare_clkzero -	ths_prepare_ns)
> -				* ui_den, ui_num * mul);
> -
> -	if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
> -		DRM_DEBUG_KMS("clock zero count too high %u\n", clk_zero_cnt);
> -		clk_zero_cnt = CLK_ZERO_CNT_MAX;
> -	}
> -
> -	/* trail count */
> -	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
> -	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
> -
> -	if (trail_cnt > TRAIL_CNT_MAX) {
> -		DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt);
> -		trail_cnt = TRAIL_CNT_MAX;
> -	}
> -
> -	/* B080 */
> -	intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
> -						clk_zero_cnt << 8 | prepare_cnt;
> -
> -	/*
> -	 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
> -	 *					mul + 10UI + Extra Byte Count
> -	 *
> -	 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
> -	 * Extra Byte Count is calculated according to number of lanes.
> -	 * High Low Switch Count is the Max of LP to HS and
> -	 * HS to LP switch count
> -	 *
> -	 */
> -	tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
> -
> -	/* B044 */
> -	/* FIXME:
> -	 * The comment above does not match with the code */
> -	lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
> -						exit_zero_cnt * mul + 10, 8);
> -
> -	hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
> -
> -	intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
> -	intel_dsi->hs_to_lp_count += extra_byte_count;
> -
> -	/* B088 */
> -	/* LP -> HS for clock lanes
> -	 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
> -	 *						extra byte count
> -	 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
> -	 *					2(in UI) + extra byte count
> -	 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
> -	 *					8 + extra byte count
> -	 */
> -	intel_dsi->clk_lp_to_hs_count =
> -		DIV_ROUND_UP(
> -			4 * tlpx_ui + prepare_cnt * 2 +
> -			clk_zero_cnt * 2,
> -			8);
> -
> -	intel_dsi->clk_lp_to_hs_count += extra_byte_count;
> -
> -	/* HS->LP for Clock Lanes
> -	 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
> -	 *						Extra byte count
> -	 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
> -	 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
> -	 *						Extra byte count
> -	 */
> -	intel_dsi->clk_hs_to_lp_count =
> -		DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
> -			8);
> -	intel_dsi->clk_hs_to_lp_count += extra_byte_count;
> -
> -	intel_dsi_log_params(intel_dsi);
> -}
> -
>  bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>  {
>  	struct drm_device *dev = intel_dsi->base.base.dev;
> @@ -925,11 +650,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>  
>  	intel_dsi->burst_mode_ratio = burst_mode_ratio;
>  
> -	if (INTEL_GEN(dev_priv) >= 11)
> -		icl_dphy_param_init(intel_dsi);
> -	else
> -		vlv_dphy_param_init(intel_dsi);
> -
>  	/* delays in VBT are in unit of 100us, so need to convert
>  	 * here in ms
>  	 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
> diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
> index 255996a71b91..59500c838b9d 100644
> --- a/drivers/gpu/drm/i915/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/vlv_dsi.c
> @@ -1689,6 +1689,174 @@ static void intel_dsi_add_properties(struct intel_connector *connector)
>  	}
>  }
>  
> +#define NS_KHZ_RATIO		1000000
> +
> +#define PREPARE_CNT_MAX		0x3F
> +#define EXIT_ZERO_CNT_MAX	0x3F
> +#define CLK_ZERO_CNT_MAX	0xFF
> +#define TRAIL_CNT_MAX		0x1F
> +
> +static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
> +{
> +	struct drm_device *dev = intel_dsi->base.base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
> +	u32 tlpx_ns, extra_byte_count, tlpx_ui;
> +	u32 ui_num, ui_den;
> +	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
> +	u32 ths_prepare_ns, tclk_trail_ns;
> +	u32 tclk_prepare_clkzero, ths_prepare_hszero;
> +	u32 lp_to_hs_switch, hs_to_lp_switch;
> +	u32 mul;
> +
> +	tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
> +
> +	switch (intel_dsi->lane_count) {
> +	case 1:
> +	case 2:
> +		extra_byte_count = 2;
> +		break;
> +	case 3:
> +		extra_byte_count = 4;
> +		break;
> +	case 4:
> +	default:
> +		extra_byte_count = 3;
> +		break;
> +	}
> +
> +	/* in Kbps */
> +	ui_num = NS_KHZ_RATIO;
> +	ui_den = intel_dsi_bitrate(intel_dsi);
> +
> +	tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
> +	ths_prepare_hszero = mipi_config->ths_prepare_hszero;
> +
> +	/*
> +	 * B060
> +	 * LP byte clock = TLPX/ (8UI)
> +	 */
> +	intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
> +
> +	/* DDR clock period = 2 * UI
> +	 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
> +	 * UI(nsec) = 10^6 / bitrate
> +	 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
> +	 * DDR clock count  = ns_value / DDR clock period
> +	 *
> +	 * For GEMINILAKE dphy_param_reg will be programmed in terms of
> +	 * HS byte clock count for other platform in HS ddr clock count
> +	 */
> +	mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
> +	ths_prepare_ns = max(mipi_config->ths_prepare,
> +			     mipi_config->tclk_prepare);
> +
> +	/* prepare count */
> +	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
> +
> +	if (prepare_cnt > PREPARE_CNT_MAX) {
> +		DRM_DEBUG_KMS("prepare count too high %u\n", prepare_cnt);
> +		prepare_cnt = PREPARE_CNT_MAX;
> +	}
> +
> +	/* exit zero count */
> +	exit_zero_cnt = DIV_ROUND_UP(
> +				(ths_prepare_hszero - ths_prepare_ns) * ui_den,
> +				ui_num * mul
> +				);
> +
> +	/*
> +	 * Exit zero is unified val ths_zero and ths_exit
> +	 * minimum value for ths_exit = 110ns
> +	 * min (exit_zero_cnt * 2) = 110/UI
> +	 * exit_zero_cnt = 55/UI
> +	 */
> +	if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
> +		exit_zero_cnt += 1;
> +
> +	if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
> +		DRM_DEBUG_KMS("exit zero count too high %u\n", exit_zero_cnt);
> +		exit_zero_cnt = EXIT_ZERO_CNT_MAX;
> +	}
> +
> +	/* clk zero count */
> +	clk_zero_cnt = DIV_ROUND_UP(
> +				(tclk_prepare_clkzero -	ths_prepare_ns)
> +				* ui_den, ui_num * mul);
> +
> +	if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
> +		DRM_DEBUG_KMS("clock zero count too high %u\n", clk_zero_cnt);
> +		clk_zero_cnt = CLK_ZERO_CNT_MAX;
> +	}
> +
> +	/* trail count */
> +	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
> +	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
> +
> +	if (trail_cnt > TRAIL_CNT_MAX) {
> +		DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt);
> +		trail_cnt = TRAIL_CNT_MAX;
> +	}
> +
> +	/* B080 */
> +	intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
> +						clk_zero_cnt << 8 | prepare_cnt;
> +
> +	/*
> +	 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
> +	 *					mul + 10UI + Extra Byte Count
> +	 *
> +	 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
> +	 * Extra Byte Count is calculated according to number of lanes.
> +	 * High Low Switch Count is the Max of LP to HS and
> +	 * HS to LP switch count
> +	 *
> +	 */
> +	tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
> +
> +	/* B044 */
> +	/* FIXME:
> +	 * The comment above does not match with the code */
> +	lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
> +						exit_zero_cnt * mul + 10, 8);
> +
> +	hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
> +
> +	intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
> +	intel_dsi->hs_to_lp_count += extra_byte_count;
> +
> +	/* B088 */
> +	/* LP -> HS for clock lanes
> +	 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
> +	 *						extra byte count
> +	 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
> +	 *					2(in UI) + extra byte count
> +	 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
> +	 *					8 + extra byte count
> +	 */
> +	intel_dsi->clk_lp_to_hs_count =
> +		DIV_ROUND_UP(
> +			4 * tlpx_ui + prepare_cnt * 2 +
> +			clk_zero_cnt * 2,
> +			8);
> +
> +	intel_dsi->clk_lp_to_hs_count += extra_byte_count;
> +
> +	/* HS->LP for Clock Lanes
> +	 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
> +	 *						Extra byte count
> +	 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
> +	 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
> +	 *						Extra byte count
> +	 */
> +	intel_dsi->clk_hs_to_lp_count =
> +		DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
> +			8);
> +	intel_dsi->clk_hs_to_lp_count += extra_byte_count;
> +
> +	intel_dsi_log_params(intel_dsi);
> +}
> +
>  void vlv_dsi_init(struct drm_i915_private *dev_priv)
>  {
>  	struct drm_device *dev = &dev_priv->drm;
> @@ -1778,6 +1946,8 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
>  		goto err;
>  	}
>  
> +	vlv_dphy_param_init(intel_dsi);
> +
>  	/*
>  	 * In case of BYT with CRC PMIC, we need to use GPIO for
>  	 * Panel control.
> -- 
> 2.21.0

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/3] drm/i915/dsi: Move vlv/icl_dphy_param_init call out of intel_dsi_vbt_init (v2)

[Hans de Goede]

Hi all,

On 05-06-19 20:37, Ville Syrjälä wrote:
> On Wed, Jun 05, 2019 at 08:17:34PM +0200, Hans de Goede wrote:
>> The vlv/icl_dphy_param_init calls do various calculations to set dphy
>> parameters based on the pclk.
>>
>> Move the calling of vlv/icl_dphy_param_init to vlv_dsi_init to give
>> vlv_dsi_init a chance to tweak the pclk before these calculations are done.
>>
>> Changes in v2:
>> -Also moves the icl and vlv specific dphy_param_init functions from the
>>   generic intel_dsi_vbt.c file into the icl_ and vlv_dsi.c specific files.
>>
>> Note icl_dphy_param_init() and vlv_dphy_param_init() are only moved,
>> otherwise they are completely unchanged.
>>
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Thanks, I've just  pushed this series to dinq (now that the CI is done and
happy with it).

Regards,

Hans



> 
>> ---
>>   drivers/gpu/drm/i915/icl_dsi.c       | 108 ++++++++++
>>   drivers/gpu/drm/i915/intel_dsi.h     |   1 +
>>   drivers/gpu/drm/i915/intel_dsi_vbt.c | 282 +--------------------------
>>   drivers/gpu/drm/i915/vlv_dsi.c       | 170 ++++++++++++++++
>>   4 files changed, 280 insertions(+), 281 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
>> index 9d962ea1e635..511c76e788ef 100644
>> --- a/drivers/gpu/drm/i915/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>> @@ -1363,6 +1363,113 @@ static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
>>   	.transfer = gen11_dsi_host_transfer,
>>   };
>>   
>> +#define ICL_PREPARE_CNT_MAX	0x7
>> +#define ICL_CLK_ZERO_CNT_MAX	0xf
>> +#define ICL_TRAIL_CNT_MAX	0x7
>> +#define ICL_TCLK_PRE_CNT_MAX	0x3
>> +#define ICL_TCLK_POST_CNT_MAX	0x7
>> +#define ICL_HS_ZERO_CNT_MAX	0xf
>> +#define ICL_EXIT_ZERO_CNT_MAX	0x7
>> +
>> +static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
>> +{
>> +	struct drm_device *dev = intel_dsi->base.base.dev;
>> +	struct drm_i915_private *dev_priv = to_i915(dev);
>> +	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
>> +	u32 tlpx_ns;
>> +	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
>> +	u32 ths_prepare_ns, tclk_trail_ns;
>> +	u32 hs_zero_cnt;
>> +	u32 tclk_pre_cnt, tclk_post_cnt;
>> +
>> +	tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
>> +
>> +	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
>> +	ths_prepare_ns = max(mipi_config->ths_prepare,
>> +			     mipi_config->tclk_prepare);
>> +
>> +	/*
>> +	 * prepare cnt in escape clocks
>> +	 * this field represents a hexadecimal value with a precision
>> +	 * of 1.2 – i.e. the most significant bit is the integer
>> +	 * and the least significant 2 bits are fraction bits.
>> +	 * so, the field can represent a range of 0.25 to 1.75
>> +	 */
>> +	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
>> +	if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
>> +		DRM_DEBUG_KMS("prepare_cnt out of range (%d)\n", prepare_cnt);
>> +		prepare_cnt = ICL_PREPARE_CNT_MAX;
>> +	}
>> +
>> +	/* clk zero count in escape clocks */
>> +	clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
>> +				    ths_prepare_ns, tlpx_ns);
>> +	if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
>> +		DRM_DEBUG_KMS("clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
>> +		clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
>> +	}
>> +
>> +	/* trail cnt in escape clocks*/
>> +	trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
>> +	if (trail_cnt > ICL_TRAIL_CNT_MAX) {
>> +		DRM_DEBUG_KMS("trail_cnt out of range (%d)\n", trail_cnt);
>> +		trail_cnt = ICL_TRAIL_CNT_MAX;
>> +	}
>> +
>> +	/* tclk pre count in escape clocks */
>> +	tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
>> +	if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
>> +		DRM_DEBUG_KMS("tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
>> +		tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
>> +	}
>> +
>> +	/* tclk post count in escape clocks */
>> +	tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns);
>> +	if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) {
>> +		DRM_DEBUG_KMS("tclk_post_cnt out of range (%d)\n", tclk_post_cnt);
>> +		tclk_post_cnt = ICL_TCLK_POST_CNT_MAX;
>> +	}
>> +
>> +	/* hs zero cnt in escape clocks */
>> +	hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
>> +				   ths_prepare_ns, tlpx_ns);
>> +	if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
>> +		DRM_DEBUG_KMS("hs_zero_cnt out of range (%d)\n", hs_zero_cnt);
>> +		hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
>> +	}
>> +
>> +	/* hs exit zero cnt in escape clocks */
>> +	exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
>> +	if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
>> +		DRM_DEBUG_KMS("exit_zero_cnt out of range (%d)\n", exit_zero_cnt);
>> +		exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
>> +	}
>> +
>> +	/* clock lane dphy timings */
>> +	intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
>> +			       CLK_PREPARE(prepare_cnt) |
>> +			       CLK_ZERO_OVERRIDE |
>> +			       CLK_ZERO(clk_zero_cnt) |
>> +			       CLK_PRE_OVERRIDE |
>> +			       CLK_PRE(tclk_pre_cnt) |
>> +			       CLK_POST_OVERRIDE |
>> +			       CLK_POST(tclk_post_cnt) |
>> +			       CLK_TRAIL_OVERRIDE |
>> +			       CLK_TRAIL(trail_cnt));
>> +
>> +	/* data lanes dphy timings */
>> +	intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
>> +					 HS_PREPARE(prepare_cnt) |
>> +					 HS_ZERO_OVERRIDE |
>> +					 HS_ZERO(hs_zero_cnt) |
>> +					 HS_TRAIL_OVERRIDE |
>> +					 HS_TRAIL(trail_cnt) |
>> +					 HS_EXIT_OVERRIDE |
>> +					 HS_EXIT(exit_zero_cnt));
>> +
>> +	intel_dsi_log_params(intel_dsi);
>> +}
>> +
>>   void icl_dsi_init(struct drm_i915_private *dev_priv)
>>   {
>>   	struct drm_device *dev = &dev_priv->drm;
>> @@ -1455,6 +1562,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
>>   		goto err;
>>   	}
>>   
>> +	icl_dphy_param_init(intel_dsi);
>>   	return;
>>   
>>   err:
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
>> index 705a609050c0..2e997187fed5 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>> @@ -192,5 +192,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
>>   void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
>>   				 enum mipi_seq seq_id);
>>   void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec);
>> +void intel_dsi_log_params(struct intel_dsi *intel_dsi);
>>   
>>   #endif /* _INTEL_DSI_H */
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> index 3a187ffabfbd..26fcb3344ebb 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> @@ -41,13 +41,6 @@
>>   #define MIPI_VIRTUAL_CHANNEL_SHIFT	1
>>   #define MIPI_PORT_SHIFT			3
>>   
>> -#define PREPARE_CNT_MAX		0x3F
>> -#define EXIT_ZERO_CNT_MAX	0x3F
>> -#define CLK_ZERO_CNT_MAX	0xFF
>> -#define TRAIL_CNT_MAX		0x1F
>> -
>> -#define NS_KHZ_RATIO 1000000
>> -
>>   /* base offsets for gpio pads */
>>   #define VLV_GPIO_NC_0_HV_DDI0_HPD	0x4130
>>   #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA	0x4120
>> @@ -532,7 +525,7 @@ void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
>>   	msleep(msec);
>>   }
>>   
>> -static void intel_dsi_log_params(struct intel_dsi *intel_dsi)
>> +void intel_dsi_log_params(struct intel_dsi *intel_dsi)
>>   {
>>   	DRM_DEBUG_KMS("Pclk %d\n", intel_dsi->pclk);
>>   	DRM_DEBUG_KMS("Pixel overlap %d\n", intel_dsi->pixel_overlap);
>> @@ -570,274 +563,6 @@ static void intel_dsi_log_params(struct intel_dsi *intel_dsi)
>>   			enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
>>   }
>>   
>> -#define ICL_PREPARE_CNT_MAX	0x7
>> -#define ICL_CLK_ZERO_CNT_MAX	0xf
>> -#define ICL_TRAIL_CNT_MAX	0x7
>> -#define ICL_TCLK_PRE_CNT_MAX	0x3
>> -#define ICL_TCLK_POST_CNT_MAX	0x7
>> -#define ICL_HS_ZERO_CNT_MAX	0xf
>> -#define ICL_EXIT_ZERO_CNT_MAX	0x7
>> -
>> -static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
>> -{
>> -	struct drm_device *dev = intel_dsi->base.base.dev;
>> -	struct drm_i915_private *dev_priv = to_i915(dev);
>> -	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
>> -	u32 tlpx_ns;
>> -	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
>> -	u32 ths_prepare_ns, tclk_trail_ns;
>> -	u32 hs_zero_cnt;
>> -	u32 tclk_pre_cnt, tclk_post_cnt;
>> -
>> -	tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
>> -
>> -	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
>> -	ths_prepare_ns = max(mipi_config->ths_prepare,
>> -			     mipi_config->tclk_prepare);
>> -
>> -	/*
>> -	 * prepare cnt in escape clocks
>> -	 * this field represents a hexadecimal value with a precision
>> -	 * of 1.2 – i.e. the most significant bit is the integer
>> -	 * and the least significant 2 bits are fraction bits.
>> -	 * so, the field can represent a range of 0.25 to 1.75
>> -	 */
>> -	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
>> -	if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
>> -		DRM_DEBUG_KMS("prepare_cnt out of range (%d)\n", prepare_cnt);
>> -		prepare_cnt = ICL_PREPARE_CNT_MAX;
>> -	}
>> -
>> -	/* clk zero count in escape clocks */
>> -	clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
>> -				    ths_prepare_ns, tlpx_ns);
>> -	if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
>> -		DRM_DEBUG_KMS("clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
>> -		clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
>> -	}
>> -
>> -	/* trail cnt in escape clocks*/
>> -	trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
>> -	if (trail_cnt > ICL_TRAIL_CNT_MAX) {
>> -		DRM_DEBUG_KMS("trail_cnt out of range (%d)\n", trail_cnt);
>> -		trail_cnt = ICL_TRAIL_CNT_MAX;
>> -	}
>> -
>> -	/* tclk pre count in escape clocks */
>> -	tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
>> -	if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
>> -		DRM_DEBUG_KMS("tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
>> -		tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
>> -	}
>> -
>> -	/* tclk post count in escape clocks */
>> -	tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns);
>> -	if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) {
>> -		DRM_DEBUG_KMS("tclk_post_cnt out of range (%d)\n", tclk_post_cnt);
>> -		tclk_post_cnt = ICL_TCLK_POST_CNT_MAX;
>> -	}
>> -
>> -	/* hs zero cnt in escape clocks */
>> -	hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
>> -				   ths_prepare_ns, tlpx_ns);
>> -	if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
>> -		DRM_DEBUG_KMS("hs_zero_cnt out of range (%d)\n", hs_zero_cnt);
>> -		hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
>> -	}
>> -
>> -	/* hs exit zero cnt in escape clocks */
>> -	exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
>> -	if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
>> -		DRM_DEBUG_KMS("exit_zero_cnt out of range (%d)\n", exit_zero_cnt);
>> -		exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
>> -	}
>> -
>> -	/* clock lane dphy timings */
>> -	intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
>> -			       CLK_PREPARE(prepare_cnt) |
>> -			       CLK_ZERO_OVERRIDE |
>> -			       CLK_ZERO(clk_zero_cnt) |
>> -			       CLK_PRE_OVERRIDE |
>> -			       CLK_PRE(tclk_pre_cnt) |
>> -			       CLK_POST_OVERRIDE |
>> -			       CLK_POST(tclk_post_cnt) |
>> -			       CLK_TRAIL_OVERRIDE |
>> -			       CLK_TRAIL(trail_cnt));
>> -
>> -	/* data lanes dphy timings */
>> -	intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
>> -					 HS_PREPARE(prepare_cnt) |
>> -					 HS_ZERO_OVERRIDE |
>> -					 HS_ZERO(hs_zero_cnt) |
>> -					 HS_TRAIL_OVERRIDE |
>> -					 HS_TRAIL(trail_cnt) |
>> -					 HS_EXIT_OVERRIDE |
>> -					 HS_EXIT(exit_zero_cnt));
>> -
>> -	intel_dsi_log_params(intel_dsi);
>> -}
>> -
>> -static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
>> -{
>> -	struct drm_device *dev = intel_dsi->base.base.dev;
>> -	struct drm_i915_private *dev_priv = to_i915(dev);
>> -	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
>> -	u32 tlpx_ns, extra_byte_count, tlpx_ui;
>> -	u32 ui_num, ui_den;
>> -	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
>> -	u32 ths_prepare_ns, tclk_trail_ns;
>> -	u32 tclk_prepare_clkzero, ths_prepare_hszero;
>> -	u32 lp_to_hs_switch, hs_to_lp_switch;
>> -	u32 mul;
>> -
>> -	tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
>> -
>> -	switch (intel_dsi->lane_count) {
>> -	case 1:
>> -	case 2:
>> -		extra_byte_count = 2;
>> -		break;
>> -	case 3:
>> -		extra_byte_count = 4;
>> -		break;
>> -	case 4:
>> -	default:
>> -		extra_byte_count = 3;
>> -		break;
>> -	}
>> -
>> -	/* in Kbps */
>> -	ui_num = NS_KHZ_RATIO;
>> -	ui_den = intel_dsi_bitrate(intel_dsi);
>> -
>> -	tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
>> -	ths_prepare_hszero = mipi_config->ths_prepare_hszero;
>> -
>> -	/*
>> -	 * B060
>> -	 * LP byte clock = TLPX/ (8UI)
>> -	 */
>> -	intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
>> -
>> -	/* DDR clock period = 2 * UI
>> -	 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
>> -	 * UI(nsec) = 10^6 / bitrate
>> -	 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
>> -	 * DDR clock count  = ns_value / DDR clock period
>> -	 *
>> -	 * For GEMINILAKE dphy_param_reg will be programmed in terms of
>> -	 * HS byte clock count for other platform in HS ddr clock count
>> -	 */
>> -	mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
>> -	ths_prepare_ns = max(mipi_config->ths_prepare,
>> -			     mipi_config->tclk_prepare);
>> -
>> -	/* prepare count */
>> -	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
>> -
>> -	if (prepare_cnt > PREPARE_CNT_MAX) {
>> -		DRM_DEBUG_KMS("prepare count too high %u\n", prepare_cnt);
>> -		prepare_cnt = PREPARE_CNT_MAX;
>> -	}
>> -
>> -	/* exit zero count */
>> -	exit_zero_cnt = DIV_ROUND_UP(
>> -				(ths_prepare_hszero - ths_prepare_ns) * ui_den,
>> -				ui_num * mul
>> -				);
>> -
>> -	/*
>> -	 * Exit zero is unified val ths_zero and ths_exit
>> -	 * minimum value for ths_exit = 110ns
>> -	 * min (exit_zero_cnt * 2) = 110/UI
>> -	 * exit_zero_cnt = 55/UI
>> -	 */
>> -	if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
>> -		exit_zero_cnt += 1;
>> -
>> -	if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
>> -		DRM_DEBUG_KMS("exit zero count too high %u\n", exit_zero_cnt);
>> -		exit_zero_cnt = EXIT_ZERO_CNT_MAX;
>> -	}
>> -
>> -	/* clk zero count */
>> -	clk_zero_cnt = DIV_ROUND_UP(
>> -				(tclk_prepare_clkzero -	ths_prepare_ns)
>> -				* ui_den, ui_num * mul);
>> -
>> -	if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
>> -		DRM_DEBUG_KMS("clock zero count too high %u\n", clk_zero_cnt);
>> -		clk_zero_cnt = CLK_ZERO_CNT_MAX;
>> -	}
>> -
>> -	/* trail count */
>> -	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
>> -	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
>> -
>> -	if (trail_cnt > TRAIL_CNT_MAX) {
>> -		DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt);
>> -		trail_cnt = TRAIL_CNT_MAX;
>> -	}
>> -
>> -	/* B080 */
>> -	intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
>> -						clk_zero_cnt << 8 | prepare_cnt;
>> -
>> -	/*
>> -	 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
>> -	 *					mul + 10UI + Extra Byte Count
>> -	 *
>> -	 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
>> -	 * Extra Byte Count is calculated according to number of lanes.
>> -	 * High Low Switch Count is the Max of LP to HS and
>> -	 * HS to LP switch count
>> -	 *
>> -	 */
>> -	tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
>> -
>> -	/* B044 */
>> -	/* FIXME:
>> -	 * The comment above does not match with the code */
>> -	lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
>> -						exit_zero_cnt * mul + 10, 8);
>> -
>> -	hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
>> -
>> -	intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
>> -	intel_dsi->hs_to_lp_count += extra_byte_count;
>> -
>> -	/* B088 */
>> -	/* LP -> HS for clock lanes
>> -	 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
>> -	 *						extra byte count
>> -	 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
>> -	 *					2(in UI) + extra byte count
>> -	 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
>> -	 *					8 + extra byte count
>> -	 */
>> -	intel_dsi->clk_lp_to_hs_count =
>> -		DIV_ROUND_UP(
>> -			4 * tlpx_ui + prepare_cnt * 2 +
>> -			clk_zero_cnt * 2,
>> -			8);
>> -
>> -	intel_dsi->clk_lp_to_hs_count += extra_byte_count;
>> -
>> -	/* HS->LP for Clock Lanes
>> -	 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
>> -	 *						Extra byte count
>> -	 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
>> -	 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
>> -	 *						Extra byte count
>> -	 */
>> -	intel_dsi->clk_hs_to_lp_count =
>> -		DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
>> -			8);
>> -	intel_dsi->clk_hs_to_lp_count += extra_byte_count;
>> -
>> -	intel_dsi_log_params(intel_dsi);
>> -}
>> -
>>   bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>>   {
>>   	struct drm_device *dev = intel_dsi->base.base.dev;
>> @@ -925,11 +650,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>>   
>>   	intel_dsi->burst_mode_ratio = burst_mode_ratio;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 11)
>> -		icl_dphy_param_init(intel_dsi);
>> -	else
>> -		vlv_dphy_param_init(intel_dsi);
>> -
>>   	/* delays in VBT are in unit of 100us, so need to convert
>>   	 * here in ms
>>   	 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
>> diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
>> index 255996a71b91..59500c838b9d 100644
>> --- a/drivers/gpu/drm/i915/vlv_dsi.c
>> +++ b/drivers/gpu/drm/i915/vlv_dsi.c
>> @@ -1689,6 +1689,174 @@ static void intel_dsi_add_properties(struct intel_connector *connector)
>>   	}
>>   }
>>   
>> +#define NS_KHZ_RATIO		1000000
>> +
>> +#define PREPARE_CNT_MAX		0x3F
>> +#define EXIT_ZERO_CNT_MAX	0x3F
>> +#define CLK_ZERO_CNT_MAX	0xFF
>> +#define TRAIL_CNT_MAX		0x1F
>> +
>> +static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
>> +{
>> +	struct drm_device *dev = intel_dsi->base.base.dev;
>> +	struct drm_i915_private *dev_priv = to_i915(dev);
>> +	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
>> +	u32 tlpx_ns, extra_byte_count, tlpx_ui;
>> +	u32 ui_num, ui_den;
>> +	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
>> +	u32 ths_prepare_ns, tclk_trail_ns;
>> +	u32 tclk_prepare_clkzero, ths_prepare_hszero;
>> +	u32 lp_to_hs_switch, hs_to_lp_switch;
>> +	u32 mul;
>> +
>> +	tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
>> +
>> +	switch (intel_dsi->lane_count) {
>> +	case 1:
>> +	case 2:
>> +		extra_byte_count = 2;
>> +		break;
>> +	case 3:
>> +		extra_byte_count = 4;
>> +		break;
>> +	case 4:
>> +	default:
>> +		extra_byte_count = 3;
>> +		break;
>> +	}
>> +
>> +	/* in Kbps */
>> +	ui_num = NS_KHZ_RATIO;
>> +	ui_den = intel_dsi_bitrate(intel_dsi);
>> +
>> +	tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
>> +	ths_prepare_hszero = mipi_config->ths_prepare_hszero;
>> +
>> +	/*
>> +	 * B060
>> +	 * LP byte clock = TLPX/ (8UI)
>> +	 */
>> +	intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
>> +
>> +	/* DDR clock period = 2 * UI
>> +	 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
>> +	 * UI(nsec) = 10^6 / bitrate
>> +	 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
>> +	 * DDR clock count  = ns_value / DDR clock period
>> +	 *
>> +	 * For GEMINILAKE dphy_param_reg will be programmed in terms of
>> +	 * HS byte clock count for other platform in HS ddr clock count
>> +	 */
>> +	mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
>> +	ths_prepare_ns = max(mipi_config->ths_prepare,
>> +			     mipi_config->tclk_prepare);
>> +
>> +	/* prepare count */
>> +	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
>> +
>> +	if (prepare_cnt > PREPARE_CNT_MAX) {
>> +		DRM_DEBUG_KMS("prepare count too high %u\n", prepare_cnt);
>> +		prepare_cnt = PREPARE_CNT_MAX;
>> +	}
>> +
>> +	/* exit zero count */
>> +	exit_zero_cnt = DIV_ROUND_UP(
>> +				(ths_prepare_hszero - ths_prepare_ns) * ui_den,
>> +				ui_num * mul
>> +				);
>> +
>> +	/*
>> +	 * Exit zero is unified val ths_zero and ths_exit
>> +	 * minimum value for ths_exit = 110ns
>> +	 * min (exit_zero_cnt * 2) = 110/UI
>> +	 * exit_zero_cnt = 55/UI
>> +	 */
>> +	if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
>> +		exit_zero_cnt += 1;
>> +
>> +	if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
>> +		DRM_DEBUG_KMS("exit zero count too high %u\n", exit_zero_cnt);
>> +		exit_zero_cnt = EXIT_ZERO_CNT_MAX;
>> +	}
>> +
>> +	/* clk zero count */
>> +	clk_zero_cnt = DIV_ROUND_UP(
>> +				(tclk_prepare_clkzero -	ths_prepare_ns)
>> +				* ui_den, ui_num * mul);
>> +
>> +	if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
>> +		DRM_DEBUG_KMS("clock zero count too high %u\n", clk_zero_cnt);
>> +		clk_zero_cnt = CLK_ZERO_CNT_MAX;
>> +	}
>> +
>> +	/* trail count */
>> +	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
>> +	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
>> +
>> +	if (trail_cnt > TRAIL_CNT_MAX) {
>> +		DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt);
>> +		trail_cnt = TRAIL_CNT_MAX;
>> +	}
>> +
>> +	/* B080 */
>> +	intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
>> +						clk_zero_cnt << 8 | prepare_cnt;
>> +
>> +	/*
>> +	 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
>> +	 *					mul + 10UI + Extra Byte Count
>> +	 *
>> +	 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
>> +	 * Extra Byte Count is calculated according to number of lanes.
>> +	 * High Low Switch Count is the Max of LP to HS and
>> +	 * HS to LP switch count
>> +	 *
>> +	 */
>> +	tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
>> +
>> +	/* B044 */
>> +	/* FIXME:
>> +	 * The comment above does not match with the code */
>> +	lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
>> +						exit_zero_cnt * mul + 10, 8);
>> +
>> +	hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
>> +
>> +	intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
>> +	intel_dsi->hs_to_lp_count += extra_byte_count;
>> +
>> +	/* B088 */
>> +	/* LP -> HS for clock lanes
>> +	 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
>> +	 *						extra byte count
>> +	 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
>> +	 *					2(in UI) + extra byte count
>> +	 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
>> +	 *					8 + extra byte count
>> +	 */
>> +	intel_dsi->clk_lp_to_hs_count =
>> +		DIV_ROUND_UP(
>> +			4 * tlpx_ui + prepare_cnt * 2 +
>> +			clk_zero_cnt * 2,
>> +			8);
>> +
>> +	intel_dsi->clk_lp_to_hs_count += extra_byte_count;
>> +
>> +	/* HS->LP for Clock Lanes
>> +	 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
>> +	 *						Extra byte count
>> +	 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
>> +	 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
>> +	 *						Extra byte count
>> +	 */
>> +	intel_dsi->clk_hs_to_lp_count =
>> +		DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
>> +			8);
>> +	intel_dsi->clk_hs_to_lp_count += extra_byte_count;
>> +
>> +	intel_dsi_log_params(intel_dsi);
>> +}
>> +
>>   void vlv_dsi_init(struct drm_i915_private *dev_priv)
>>   {
>>   	struct drm_device *dev = &dev_priv->drm;
>> @@ -1778,6 +1946,8 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
>>   		goto err;
>>   	}
>>   
>> +	vlv_dphy_param_init(intel_dsi);
>> +
>>   	/*
>>   	 * In case of BYT with CRC PMIC, we need to use GPIO for
>>   	 * Panel control.
>> -- 
>> 2.21.0
> 
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH 3/3] drm/i915/dsi: Read back pclk set by GOP and use that as pclk (v3)

[Hans de Goede]

The GOP sometimes initializes the pclk at a (slightly) different frequency
then the pclk which we've calculated.

This commit makes the DSI code read-back the pclk set by the GOP and
if that is within a reasonable margin of the calculated pclk, uses
that instead.

This fixes the first modeset being a full modeset instead of a
fast modeset on systems where the GOP pclk is different.

Changes in v2:
-Use intel_encoder_current_mode() to get the pclk setup by the GOP

Changes in v3:
-Back to the readback approach, skipping the dsi_pll.ctrl / .dev checks
 in intel_pipe_config_compare() when adjust is set leads to:
 [drm:pipe_config_err [i915]] *ERROR* mismatch in dsi_pll.ctrl (...)
 [drm:pipe_config_err [i915]] *ERROR* mismatch in dsi_pll.div (...)
-Do the readback and pclk overriding from vlv_dsi_init(), rather then from
 intel_dsi_vbt_init() as the vbt code should not be touching the hw

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 drivers/gpu/drm/i915/vlv_dsi.c | 22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
index 59500c838b9d..6d96891984a5 100644
--- a/drivers/gpu/drm/i915/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/vlv_dsi.c
@@ -1865,7 +1865,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
 	struct drm_encoder *encoder;
 	struct intel_connector *intel_connector;
 	struct drm_connector *connector;
-	struct drm_display_mode *fixed_mode;
+	struct drm_display_mode *current_mode, *fixed_mode;
 	enum port port;
 
 	DRM_DEBUG_KMS("\n");
@@ -1909,6 +1909,9 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
 	intel_connector->get_hw_state = intel_connector_get_hw_state;
 
 	intel_encoder->port = port;
+	intel_encoder->type = INTEL_OUTPUT_DSI;
+	intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
+	intel_encoder->cloneable = 0;
 
 	/*
 	 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
@@ -1946,6 +1949,20 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
 		goto err;
 	}
 
+	/* Use clock read-back from current hw-state for fastboot */
+	current_mode = intel_encoder_current_mode(intel_encoder);
+	if (current_mode) {
+		DRM_DEBUG_KMS("Calculated pclk %d GOP %d\n",
+			      intel_dsi->pclk, current_mode->clock);
+		if (intel_fuzzy_clock_check(intel_dsi->pclk,
+					    current_mode->clock)) {
+			DRM_DEBUG_KMS("Using GOP pclk\n");
+			intel_dsi->pclk = current_mode->clock;
+		}
+
+		kfree(current_mode);
+	}
+
 	vlv_dphy_param_init(intel_dsi);
 
 	/*
@@ -1963,9 +1980,6 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
 		}
 	}
 
-	intel_encoder->type = INTEL_OUTPUT_DSI;
-	intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
-	intel_encoder->cloneable = 0;
 	drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
 			   DRM_MODE_CONNECTOR_DSI);
 
-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/dsi: Move logging of DSI VBT parameters to a helper function

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/dsi: Move logging of DSI VBT parameters to a helper function
URL   : https://patchwork.freedesktop.org/series/61679/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
e5829ea35195 drm/i915/dsi: Move logging of DSI VBT parameters to a helper function
-:59: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#59: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:575:
+	DRM_DEBUG_KMS("BTA %s\n",
+			enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));

total: 0 errors, 0 warnings, 1 checks, 101 lines checked
c48843171c41 drm/i915/dsi: Move vlv/icl_dphy_param_init call out of intel_dsi_vbt_init (v2)
-:552: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#552: FILE: drivers/gpu/drm/i915/vlv_dsi.c:1743:
+	exit_zero_cnt = DIV_ROUND_UP(

-:572: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#572: FILE: drivers/gpu/drm/i915/vlv_dsi.c:1763:
+	clk_zero_cnt = DIV_ROUND_UP(

-:608: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#608: FILE: drivers/gpu/drm/i915/vlv_dsi.c:1799:
+	 * The comment above does not match with the code */

-:627: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#627: FILE: drivers/gpu/drm/i915/vlv_dsi.c:1818:
+		DIV_ROUND_UP(

-:643: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#643: FILE: drivers/gpu/drm/i915/vlv_dsi.c:1834:
+		DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
+			8);

total: 0 errors, 1 warnings, 4 checks, 614 lines checked
9787f959f37c drm/i915/dsi: Read back pclk set by GOP and use that as pclk (v3)

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/dsi: Move logging of DSI VBT parameters to a helper function

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/dsi: Move logging of DSI VBT parameters to a helper function
URL   : https://patchwork.freedesktop.org/series/61679/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/dsi: Move logging of DSI VBT parameters to a helper function
Okay!

Commit: drm/i915/dsi: Move vlv/icl_dphy_param_init call out of intel_dsi_vbt_init (v2)
+drivers/gpu/drm/i915/icl_dsi.c:1404:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/icl_dsi.c:1404:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/icl_dsi.c:1405:26: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/icl_dsi.c:1405:26: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:599:25: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:599:25: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:600:26: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:600:26: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:737:26: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:737:26: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:779:25: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:779:25: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:811:37: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:811:37: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/vlv_dsi.c:1731:26: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/vlv_dsi.c:1731:26: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/vlv_dsi.c:1773:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/vlv_dsi.c:1773:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/vlv_dsi.c:1805:37: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/vlv_dsi.c:1805:37: warning: expression using sizeof(void)

Commit: drm/i915/dsi: Read back pclk set by GOP and use that as pclk (v3)
Okay!

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/dsi: Move logging of DSI VBT parameters to a helper function

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/dsi: Move logging of DSI VBT parameters to a helper function
URL   : https://patchwork.freedesktop.org/series/61679/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6196 -> Patchwork_13182
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/

Known issues
------------

  Here are the changes found in Patchwork_13182 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live_evict:
    - fi-bsw-kefka:       [PASS][1] -> [DMESG-WARN][2] ([fdo#107709])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/fi-bsw-kefka/igt@i915_selftest@live_evict.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/fi-bsw-kefka/igt@i915_selftest@live_evict.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-dsi:         [PASS][3] -> [FAIL][4] ([fdo#103167])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/fi-icl-dsi/igt@kms_frontbuffer_tracking@basic.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/fi-icl-dsi/igt@kms_frontbuffer_tracking@basic.html

  * igt@prime_vgem@basic-fence-flip:
    - fi-icl-u3:          [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/fi-icl-u3/igt@prime_vgem@basic-fence-flip.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/fi-icl-u3/igt@prime_vgem@basic-fence-flip.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [FAIL][7] ([fdo#108511]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  * igt@kms_addfb_basic@basic:
    - fi-icl-u3:          [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/fi-icl-u3/igt@kms_addfb_basic@basic.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/fi-icl-u3/igt@kms_addfb_basic@basic.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-hsw-peppy:       [DMESG-WARN][11] ([fdo#102614]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html

  
  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511


Participating hosts (52 -> 46)
------------------------------

  Additional (1): fi-cfl-guc 
  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6196 -> Patchwork_13182

  CI_DRM_6196: 7a984cf09665b9ef4c63e82a8551bdde5da229ae @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5040: f190ab5dcd3fa52f4b47bc28c01bcfbbdc888826 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13182: 9787f959f37c9f3324dfae43e4c2f0080a553f73 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

9787f959f37c drm/i915/dsi: Read back pclk set by GOP and use that as pclk (v3)
c48843171c41 drm/i915/dsi: Move vlv/icl_dphy_param_init call out of intel_dsi_vbt_init (v2)
e5829ea35195 drm/i915/dsi: Move logging of DSI VBT parameters to a helper function

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/dsi: Move logging of DSI VBT parameters to a helper function

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/dsi: Move logging of DSI VBT parameters to a helper function
URL   : https://patchwork.freedesktop.org/series/61679/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6196_full -> Patchwork_13182_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_13182_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@in-flight-suspend:
    - shard-glk:          [PASS][1] -> [FAIL][2] ([fdo#110667])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-glk6/igt@gem_eio@in-flight-suspend.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-glk9/igt@gem_eio@in-flight-suspend.html

  * igt@gem_pread@display:
    - shard-hsw:          [PASS][3] -> [INCOMPLETE][4] ([fdo#103540])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-hsw7/igt@gem_pread@display.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-hsw1/igt@gem_pread@display.html

  * igt@gem_softpin@noreloc-s3:
    - shard-glk:          [PASS][5] -> [INCOMPLETE][6] ([fdo#103359] / [k.org#198133])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-glk3/igt@gem_softpin@noreloc-s3.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-glk4/igt@gem_softpin@noreloc-s3.html
    - shard-skl:          [PASS][7] -> [INCOMPLETE][8] ([fdo#104108]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-skl4/igt@gem_softpin@noreloc-s3.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-skl4/igt@gem_softpin@noreloc-s3.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-glk:          [PASS][9] -> [DMESG-WARN][10] ([fdo#108686])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-glk7/igt@gem_tiled_swapping@non-threaded.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-glk9/igt@gem_tiled_swapping@non-threaded.html
    - shard-kbl:          [PASS][11] -> [DMESG-WARN][12] ([fdo#108686])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-kbl4/igt@gem_tiled_swapping@non-threaded.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-kbl2/igt@gem_tiled_swapping@non-threaded.html

  * igt@i915_selftest@live_hangcheck:
    - shard-iclb:         [PASS][13] -> [INCOMPLETE][14] ([fdo#107713] / [fdo#108569])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-iclb5/igt@i915_selftest@live_hangcheck.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-iclb2/igt@i915_selftest@live_hangcheck.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-apl:          [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +2 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-apl1/igt@i915_suspend@fence-restore-tiled2untiled.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-apl8/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding:
    - shard-skl:          [PASS][17] -> [FAIL][18] ([fdo#103232])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
    - shard-glk:          [PASS][19] -> [FAIL][20] ([fdo#104873])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-glk9/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-glk:          [PASS][21] -> [FAIL][22] ([fdo#102887])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-glk:          [PASS][23] -> [FAIL][24] ([fdo#105363])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-glk4/igt@kms_flip@flip-vs-expired-vblank.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-glk7/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
    - shard-snb:          [PASS][25] -> [INCOMPLETE][26] ([fdo#105411])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-snb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-snb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-hsw:          [PASS][27] -> [SKIP][28] ([fdo#109271]) +9 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-hsw8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-hsw1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbc-badstride:
    - shard-iclb:         [PASS][29] -> [FAIL][30] ([fdo#103167]) +3 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-badstride.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-badstride.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
    - shard-kbl:          [PASS][31] -> [INCOMPLETE][32] ([fdo#103665])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [PASS][33] -> [FAIL][34] ([fdo#108145] / [fdo#110403])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [PASS][35] -> [FAIL][36] ([fdo#108145])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-iclb:         [PASS][37] -> [FAIL][38] ([fdo#103166]) +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [PASS][39] -> [SKIP][40] ([fdo#109441]) +3 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-iclb3/igt@kms_psr@psr2_cursor_mmap_cpu.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-apl:          [DMESG-WARN][41] ([fdo#108566]) -> [PASS][42] +3 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-apl3/igt@gem_ctx_isolation@rcs0-s3.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-apl6/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_ctx_isolation@vcs0-s3:
    - shard-skl:          [INCOMPLETE][43] ([fdo#104108]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-skl3/igt@gem_ctx_isolation@vcs0-s3.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-skl7/igt@gem_ctx_isolation@vcs0-s3.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          [FAIL][45] ([fdo#105363]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite:
    - shard-hsw:          [SKIP][47] ([fdo#109271]) -> [PASS][48] +30 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-hsw1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-hsw6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
    - shard-iclb:         [FAIL][49] ([fdo#103167]) -> [PASS][50] +2 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html

  * igt@kms_psr@psr2_primary_blt:
    - shard-iclb:         [SKIP][51] ([fdo#109441]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-iclb6/igt@kms_psr@psr2_primary_blt.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-iclb2/igt@kms_psr@psr2_primary_blt.html

  * igt@kms_setmode@basic:
    - shard-kbl:          [FAIL][53] ([fdo#99912]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-kbl7/igt@kms_setmode@basic.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-kbl3/igt@kms_setmode@basic.html

  * igt@kms_sysfs_edid_timing:
    - shard-hsw:          [FAIL][55] ([fdo#100047]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-hsw1/igt@kms_sysfs_edid_timing.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-hsw2/igt@kms_sysfs_edid_timing.html

  * igt@perf@polling:
    - shard-skl:          [FAIL][57] ([fdo#110728]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-skl4/igt@perf@polling.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-skl3/igt@perf@polling.html

  * igt@perf_pmu@rc6-runtime-pm:
    - shard-apl:          [FAIL][59] ([fdo#105010]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/shard-apl1/igt@perf_pmu@rc6-runtime-pm.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/shard-apl5/igt@perf_pmu@rc6-runtime-pm.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
  [fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
  [fdo#105010]: https://bugs.freedesktop.org/show_bug.cgi?id=105010
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110667]: https://bugs.freedesktop.org/show_bug.cgi?id=110667
  [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
  [fdo#110851]: https://bugs.freedesktop.org/show_bug.cgi?id=110851
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_6196 -> Patchwork_13182

  CI_DRM_6196: 7a984cf09665b9ef4c63e82a8551bdde5da229ae @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5040: f190ab5dcd3fa52f4b47bc28c01bcfbbdc888826 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13182: 9787f959f37c9f3324dfae43e4c2f0080a553f73 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx