* [PATCH 01/13] KVM: nVMX: Use adjusted pin controls for vmcs02
2019-05-07 19:17 [PATCH 00/13] KVM: VMX: Reduce VMWRITEs to VMCS controls Sean Christopherson
@ 2019-05-07 19:17 ` Sean Christopherson
2019-06-06 16:55 ` Paolo Bonzini
2019-05-07 19:17 ` [PATCH 02/13] KVM: VMX: Add builder macros for shadowing controls Sean Christopherson
` (11 subsequent siblings)
12 siblings, 1 reply; 21+ messages in thread
From: Sean Christopherson @ 2019-05-07 19:17 UTC (permalink / raw)
To: Paolo Bonzini, Radim Krčmář; +Cc: kvm
KVM provides a module parameter to allow disabling virtual NMI support
to simplify testing (hardware *without* virtual NMI support is virtually
non-existent, pun intended). When preparing vmcs02, use the accessor
for pin controls to ensure that the module param is respected for nested
guests.
Opportunistically swap the order of applying L0's and L1's pin controls
to better align with other controls and to prepare for a future patche
that will ignore L1's, but not L0's, preemption timer flag.
Fixes: d02fcf50779ec ("kvm: vmx: Allow disabling virtual NMI support")
Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
---
arch/x86/kvm/vmx/nested.c | 5 ++---
arch/x86/kvm/vmx/vmx.c | 2 +-
arch/x86/kvm/vmx/vmx.h | 1 +
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index 04b40a98f60b..2a98d92f955b 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -1986,10 +1986,9 @@ static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
/*
* PIN CONTROLS
*/
- exec_control = vmcs12->pin_based_vm_exec_control;
-
+ exec_control = vmx_pin_based_exec_ctrl(vmx);
+ exec_control |= vmcs12->pin_based_vm_exec_control;
/* Preemption timer setting is computed directly in vmx_vcpu_run. */
- exec_control |= vmcs_config.pin_based_exec_ctrl;
exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
vmx->loaded_vmcs->hv_timer_armed = false;
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 60306f19105d..08f36881473f 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -3798,7 +3798,7 @@ void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
}
-static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
+u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
{
u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h
index 63d37ccce3dc..181acd906c75 100644
--- a/arch/x86/kvm/vmx/vmx.h
+++ b/arch/x86/kvm/vmx/vmx.h
@@ -467,6 +467,7 @@ static inline u32 vmx_vmexit_ctrl(void)
}
u32 vmx_exec_control(struct vcpu_vmx *vmx);
+u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx);
static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
{
--
2.21.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 02/13] KVM: VMX: Add builder macros for shadowing controls
2019-05-07 19:17 [PATCH 00/13] KVM: VMX: Reduce VMWRITEs to VMCS controls Sean Christopherson
2019-05-07 19:17 ` [PATCH 01/13] KVM: nVMX: Use adjusted pin controls for vmcs02 Sean Christopherson
@ 2019-05-07 19:17 ` Sean Christopherson
2019-05-07 19:17 ` [PATCH 03/13] KVM: VMX: Shadow VMCS pin controls Sean Christopherson
` (10 subsequent siblings)
12 siblings, 0 replies; 21+ messages in thread
From: Sean Christopherson @ 2019-05-07 19:17 UTC (permalink / raw)
To: Paolo Bonzini, Radim Krčmář; +Cc: kvm
... to pave the way for shadowing all (five) major VMCS control fields
without massive amounts of error prone copy+paste+modify.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
---
arch/x86/kvm/vmx/vmx.h | 102 +++++++++++++++--------------------------
1 file changed, 37 insertions(+), 65 deletions(-)
diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h
index 181acd906c75..bdc0df871be9 100644
--- a/arch/x86/kvm/vmx/vmx.h
+++ b/arch/x86/kvm/vmx/vmx.h
@@ -85,6 +85,11 @@ struct pt_desc {
struct pt_ctx guest;
};
+struct vmx_controls_shadow {
+ u32 vm_entry;
+ u32 vm_exit;
+};
+
/*
* The nested_vmx structure is part of vcpu_vmx, and holds information we need
* for correct emulation of VMX (i.e., nested VMX) on this vcpu.
@@ -183,6 +188,9 @@ struct vcpu_vmx {
u32 exit_intr_info;
u32 idt_vectoring_info;
ulong rflags;
+
+ struct vmx_controls_shadow controls_shadow;
+
struct shared_msr_entry *guest_msrs;
int nmsrs;
int save_nmsrs;
@@ -195,8 +203,6 @@ struct vcpu_vmx {
u64 spec_ctrl;
- u32 vm_entry_controls_shadow;
- u32 vm_exit_controls_shadow;
u32 secondary_exec_control;
/*
@@ -375,69 +381,35 @@ static inline u8 vmx_get_rvi(void)
return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
}
-static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
-{
- vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
-}
-
-static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
-{
- vmcs_write32(VM_ENTRY_CONTROLS, val);
- vmx->vm_entry_controls_shadow = val;
-}
-
-static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
-{
- if (vmx->vm_entry_controls_shadow != val)
- vm_entry_controls_init(vmx, val);
-}
-
-static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
-{
- return vmx->vm_entry_controls_shadow;
-}
-
-static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
-{
- vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
-}
-
-static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
-{
- vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
-}
-
-static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
-{
- vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
-}
-
-static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
-{
- vmcs_write32(VM_EXIT_CONTROLS, val);
- vmx->vm_exit_controls_shadow = val;
-}
-
-static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
-{
- if (vmx->vm_exit_controls_shadow != val)
- vm_exit_controls_init(vmx, val);
-}
-
-static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
-{
- return vmx->vm_exit_controls_shadow;
-}
-
-static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
-{
- vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
-}
-
-static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
-{
- vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
-}
+#define BUILD_CONTROLS_SHADOW(lname, uname) \
+static inline void lname##_controls_reset_shadow(struct vcpu_vmx *vmx) \
+{ \
+ vmx->controls_shadow.lname = vmcs_read32(uname); \
+} \
+static inline void lname##_controls_init(struct vcpu_vmx *vmx, u32 val) \
+{ \
+ vmcs_write32(uname, val); \
+ vmx->controls_shadow.lname = val; \
+} \
+static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val) \
+{ \
+ if (vmx->controls_shadow.lname != val) \
+ lname##_controls_init(vmx, val); \
+} \
+static inline u32 lname##_controls_get(struct vcpu_vmx *vmx) \
+{ \
+ return vmx->controls_shadow.lname; \
+} \
+static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val) \
+{ \
+ lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \
+} \
+static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \
+{ \
+ lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \
+}
+BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS)
+BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS)
static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
{
--
2.21.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 03/13] KVM: VMX: Shadow VMCS pin controls
2019-05-07 19:17 [PATCH 00/13] KVM: VMX: Reduce VMWRITEs to VMCS controls Sean Christopherson
2019-05-07 19:17 ` [PATCH 01/13] KVM: nVMX: Use adjusted pin controls for vmcs02 Sean Christopherson
2019-05-07 19:17 ` [PATCH 02/13] KVM: VMX: Add builder macros for shadowing controls Sean Christopherson
@ 2019-05-07 19:17 ` Sean Christopherson
2019-05-07 19:17 ` [PATCH 04/13] KVM: VMX: Shadow VMCS primary execution controls Sean Christopherson
` (9 subsequent siblings)
12 siblings, 0 replies; 21+ messages in thread
From: Sean Christopherson @ 2019-05-07 19:17 UTC (permalink / raw)
To: Paolo Bonzini, Radim Krčmář; +Cc: kvm
Prepare to shadow all major control fields on a per-VMCS basis, which
allows KVM to avoid costly VMWRITEs when switching between vmcs01 and
vmcs02.
Shadowing pin controls also allows a future patch to remove the per-VMCS
'hv_timer_armed' flag, as the shadow copy is a superset of said flag.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
---
arch/x86/kvm/vmx/nested.c | 3 ++-
arch/x86/kvm/vmx/vmx.c | 10 ++++------
arch/x86/kvm/vmx/vmx.h | 2 ++
3 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index 2a98d92f955b..95eda399fd71 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -254,6 +254,7 @@ static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
vm_entry_controls_reset_shadow(vmx);
vm_exit_controls_reset_shadow(vmx);
+ pin_controls_reset_shadow(vmx);
vmx_segment_cache_clear(vmx);
}
@@ -1999,7 +2000,7 @@ static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
} else {
exec_control &= ~PIN_BASED_POSTED_INTR;
}
- vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
+ pin_controls_init(vmx, exec_control);
/*
* EXEC CONTROLS
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 08f36881473f..c107a2dd9769 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -3817,7 +3817,7 @@ static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
{
struct vcpu_vmx *vmx = to_vmx(vcpu);
- vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
+ pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
if (cpu_has_secondary_exec_ctrls()) {
if (kvm_vcpu_apicv_active(vcpu))
vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
@@ -4015,7 +4015,7 @@ static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
/* Control */
- vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
+ pin_controls_init(vmx, vmx_pin_based_exec_ctrl(vmx));
vmx->hv_deadline_tsc = -1;
vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
@@ -6327,8 +6327,7 @@ static void vmx_arm_hv_timer(struct vcpu_vmx *vmx, u32 val)
{
vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, val);
if (!vmx->loaded_vmcs->hv_timer_armed)
- vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
- PIN_BASED_VMX_PREEMPTION_TIMER);
+ pin_controls_setbit(vmx, PIN_BASED_VMX_PREEMPTION_TIMER);
vmx->loaded_vmcs->hv_timer_armed = true;
}
@@ -6357,8 +6356,7 @@ static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
}
if (vmx->loaded_vmcs->hv_timer_armed)
- vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
- PIN_BASED_VMX_PREEMPTION_TIMER);
+ pin_controls_clearbit(vmx, PIN_BASED_VMX_PREEMPTION_TIMER);
vmx->loaded_vmcs->hv_timer_armed = false;
}
diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h
index bdc0df871be9..661ab4212cf7 100644
--- a/arch/x86/kvm/vmx/vmx.h
+++ b/arch/x86/kvm/vmx/vmx.h
@@ -88,6 +88,7 @@ struct pt_desc {
struct vmx_controls_shadow {
u32 vm_entry;
u32 vm_exit;
+ u32 pin;
};
/*
@@ -410,6 +411,7 @@ static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \
}
BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS)
BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS)
+BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL)
static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
{
--
2.21.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 04/13] KVM: VMX: Shadow VMCS primary execution controls
2019-05-07 19:17 [PATCH 00/13] KVM: VMX: Reduce VMWRITEs to VMCS controls Sean Christopherson
` (2 preceding siblings ...)
2019-05-07 19:17 ` [PATCH 03/13] KVM: VMX: Shadow VMCS pin controls Sean Christopherson
@ 2019-05-07 19:17 ` Sean Christopherson
2019-05-07 19:17 ` [PATCH 05/13] KVM: VMX: Shadow VMCS secondary " Sean Christopherson
` (8 subsequent siblings)
12 siblings, 0 replies; 21+ messages in thread
From: Sean Christopherson @ 2019-05-07 19:17 UTC (permalink / raw)
To: Paolo Bonzini, Radim Krčmář; +Cc: kvm
Prepare to shadow all major control fields on a per-VMCS basis, which
allows KVM to avoid VMREADs when switching between vmcs01 and vmcs02,
and more importantly can eliminate costly VMWRITEs to controls when
preparing vmcs02.
Shadowing exec controls also saves a VMREAD when opening virtual
INTR/NMI windows, yay...
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
---
arch/x86/kvm/vmx/nested.c | 14 ++++++--------
arch/x86/kvm/vmx/vmx.c | 38 +++++++++++++++-----------------------
arch/x86/kvm/vmx/vmx.h | 2 ++
3 files changed, 23 insertions(+), 31 deletions(-)
diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index 95eda399fd71..7212cd04e9c2 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -255,6 +255,7 @@ static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
vm_entry_controls_reset_shadow(vmx);
vm_exit_controls_reset_shadow(vmx);
pin_controls_reset_shadow(vmx);
+ exec_controls_reset_shadow(vmx);
vmx_segment_cache_clear(vmx);
}
@@ -2032,7 +2033,7 @@ static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
*/
exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
exec_control |= CPU_BASED_UNCOND_IO_EXITING;
- vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
+ exec_controls_init(vmx, exec_control);
/*
* SECONDARY EXEC CONTROLS
@@ -2873,8 +2874,7 @@ static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu)
* _not_ what the processor does but it's basically the
* only possibility we have.
*/
- vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
- CPU_BASED_TPR_SHADOW);
+ exec_controls_clearbit(vmx, CPU_BASED_TPR_SHADOW);
} else {
printk("bad virtual-APIC page address\n");
dump_vmcs();
@@ -2893,11 +2893,9 @@ static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu)
}
}
if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
- vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
- CPU_BASED_USE_MSR_BITMAPS);
+ exec_controls_setbit(vmx, CPU_BASED_USE_MSR_BITMAPS);
else
- vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
- CPU_BASED_USE_MSR_BITMAPS);
+ exec_controls_clearbit(vmx, CPU_BASED_USE_MSR_BITMAPS);
}
/*
@@ -2950,7 +2948,7 @@ int nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
u32 exit_reason = EXIT_REASON_INVALID_STATE;
u32 exit_qual;
- evaluate_pending_interrupts = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
+ evaluate_pending_interrupts = exec_controls_get(vmx) &
(CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_VIRTUAL_NMI_PENDING);
if (likely(!evaluate_pending_interrupts) && kvm_vcpu_apicv_active(vcpu))
evaluate_pending_interrupts |= vmx_has_apicv_interrupt(vcpu);
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index c107a2dd9769..278007885a8e 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -2766,22 +2766,20 @@ static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
unsigned long cr0,
struct kvm_vcpu *vcpu)
{
+ struct vcpu_vmx *vmx = to_vmx(vcpu);
+
if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
vmx_decache_cr3(vcpu);
if (!(cr0 & X86_CR0_PG)) {
/* From paging/starting to nonpaging */
- vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
- vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
- (CPU_BASED_CR3_LOAD_EXITING |
- CPU_BASED_CR3_STORE_EXITING));
+ exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
+ CPU_BASED_CR3_STORE_EXITING);
vcpu->arch.cr0 = cr0;
vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
} else if (!is_paging(vcpu)) {
/* From nonpaging to paging */
- vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
- vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
- ~(CPU_BASED_CR3_LOAD_EXITING |
- CPU_BASED_CR3_STORE_EXITING));
+ exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
+ CPU_BASED_CR3_STORE_EXITING);
vcpu->arch.cr0 = cr0;
vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
}
@@ -4018,7 +4016,7 @@ static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
pin_controls_init(vmx, vmx_pin_based_exec_ctrl(vmx));
vmx->hv_deadline_tsc = -1;
- vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
+ exec_controls_init(vmx, vmx_exec_control(vmx));
if (cpu_has_secondary_exec_ctrls()) {
vmx_compute_secondary_exec_control(vmx);
@@ -4208,8 +4206,7 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
static void enable_irq_window(struct kvm_vcpu *vcpu)
{
- vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
- CPU_BASED_VIRTUAL_INTR_PENDING);
+ exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
}
static void enable_nmi_window(struct kvm_vcpu *vcpu)
@@ -4220,8 +4217,7 @@ static void enable_nmi_window(struct kvm_vcpu *vcpu)
return;
}
- vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
- CPU_BASED_VIRTUAL_NMI_PENDING);
+ exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
}
static void vmx_inject_irq(struct kvm_vcpu *vcpu)
@@ -4771,8 +4767,7 @@ static int handle_dr(struct kvm_vcpu *vcpu)
}
if (vcpu->guest_debug == 0) {
- vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
- CPU_BASED_MOV_DR_EXITING);
+ exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
/*
* No more DR vmexits; force a reload of the debug registers
@@ -4816,7 +4811,7 @@ static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
- vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
+ exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
}
static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
@@ -4876,8 +4871,7 @@ static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
static int handle_interrupt_window(struct kvm_vcpu *vcpu)
{
- vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
- CPU_BASED_VIRTUAL_INTR_PENDING);
+ exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
kvm_make_request(KVM_REQ_EVENT, vcpu);
@@ -5131,8 +5125,7 @@ static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
static int handle_nmi_window(struct kvm_vcpu *vcpu)
{
WARN_ON_ONCE(!enable_vnmi);
- vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
- CPU_BASED_VIRTUAL_NMI_PENDING);
+ exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
++vcpu->stat.nmi_window_exits;
kvm_make_request(KVM_REQ_EVENT, vcpu);
@@ -5144,7 +5137,6 @@ static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
struct vcpu_vmx *vmx = to_vmx(vcpu);
enum emulation_result err = EMULATE_DONE;
int ret = 1;
- u32 cpu_exec_ctrl;
bool intr_window_requested;
unsigned count = 130;
@@ -5155,8 +5147,8 @@ static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
*/
WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
- cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
- intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
+ intr_window_requested = exec_controls_get(vmx) &
+ CPU_BASED_VIRTUAL_INTR_PENDING;
while (vmx->emulation_required && count-- != 0) {
if (intr_window_requested && vmx_interrupt_allowed(vcpu))
diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h
index 661ab4212cf7..673cab3f6f66 100644
--- a/arch/x86/kvm/vmx/vmx.h
+++ b/arch/x86/kvm/vmx/vmx.h
@@ -89,6 +89,7 @@ struct vmx_controls_shadow {
u32 vm_entry;
u32 vm_exit;
u32 pin;
+ u32 exec;
};
/*
@@ -412,6 +413,7 @@ static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \
BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS)
BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS)
BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL)
+BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL)
static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
{
--
2.21.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 05/13] KVM: VMX: Shadow VMCS secondary execution controls
2019-05-07 19:17 [PATCH 00/13] KVM: VMX: Reduce VMWRITEs to VMCS controls Sean Christopherson
` (3 preceding siblings ...)
2019-05-07 19:17 ` [PATCH 04/13] KVM: VMX: Shadow VMCS primary execution controls Sean Christopherson
@ 2019-05-07 19:17 ` Sean Christopherson
2019-06-06 16:59 ` Paolo Bonzini
2019-05-07 19:17 ` [PATCH 06/13] KVM: nVMX: Shadow VMCS controls on a per-VMCS basis Sean Christopherson
` (7 subsequent siblings)
12 siblings, 1 reply; 21+ messages in thread
From: Sean Christopherson @ 2019-05-07 19:17 UTC (permalink / raw)
To: Paolo Bonzini, Radim Krčmář; +Cc: kvm
Prepare to shadow all major control fields on a per-VMCS basis, which
allows KVM to avoid costly VMWRITEs when switching between vmcs01 and
vmcs02.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
---
arch/x86/kvm/vmx/nested.c | 12 ++++++------
arch/x86/kvm/vmx/vmx.c | 40 +++++++++++++++++++--------------------
arch/x86/kvm/vmx/vmx.h | 2 ++
3 files changed, 28 insertions(+), 26 deletions(-)
diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index 7212cd04e9c2..007d03a49484 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -182,7 +182,7 @@ static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
{
- vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
+ sec_exec_controls_clearbit(vmx, SECONDARY_EXEC_SHADOW_VMCS);
vmcs_write64(VMCS_LINK_POINTER, -1ull);
}
@@ -256,6 +256,7 @@ static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
vm_exit_controls_reset_shadow(vmx);
pin_controls_reset_shadow(vmx);
exec_controls_reset_shadow(vmx);
+ sec_exec_controls_reset_shadow(vmx);
vmx_segment_cache_clear(vmx);
}
@@ -2074,7 +2075,7 @@ static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
if (exec_control & SECONDARY_EXEC_ENCLS_EXITING)
vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
- vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
+ sec_exec_controls_init(vmx, exec_control);
}
/*
@@ -2849,8 +2850,8 @@ static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu)
hpa = page_to_phys(vmx->nested.apic_access_page);
vmcs_write64(APIC_ACCESS_ADDR, hpa);
} else {
- vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
- SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
+ sec_exec_controls_clearbit(vmx,
+ SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
}
}
@@ -4522,8 +4523,7 @@ static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
{
vmx->nested.current_vmptr = vmptr;
if (enable_shadow_vmcs) {
- vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
- SECONDARY_EXEC_SHADOW_VMCS);
+ sec_exec_controls_setbit(vmx, SECONDARY_EXEC_SHADOW_VMCS);
vmcs_write64(VMCS_LINK_POINTER,
__pa(vmx->vmcs01.shadow_vmcs));
vmx->nested.need_vmcs12_sync = true;
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 278007885a8e..274b870f6511 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -2879,6 +2879,7 @@ void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
{
+ struct vcpu_vmx *vmx = to_vmx(vcpu);
/*
* Pass through host's Machine Check Enable value to hw_cr4, which
* is in force while we are in guest mode. Do not let guests control
@@ -2889,20 +2890,19 @@ int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
if (enable_unrestricted_guest)
hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
- else if (to_vmx(vcpu)->rmode.vm86_active)
+ else if (vmx->rmode.vm86_active)
hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
else
hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
if (cr4 & X86_CR4_UMIP) {
- vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
- SECONDARY_EXEC_DESC);
+ sec_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
hw_cr4 &= ~X86_CR4_UMIP;
} else if (!is_guest_mode(vcpu) ||
- !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC))
- vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
- SECONDARY_EXEC_DESC);
+ !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
+ sec_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
+ }
}
if (cr4 & X86_CR4_VMXE) {
@@ -2917,7 +2917,7 @@ int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
return 1;
}
- if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
+ if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
return 1;
vcpu->arch.cr4 = cr4;
@@ -3535,7 +3535,7 @@ static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
u8 mode = 0;
if (cpu_has_secondary_exec_ctrls() &&
- (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
+ (sec_exec_controls_get(to_vmx(vcpu)) &
SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
mode |= MSR_BITMAP_MODE_X2APIC;
if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
@@ -3818,11 +3818,11 @@ static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
if (cpu_has_secondary_exec_ctrls()) {
if (kvm_vcpu_apicv_active(vcpu))
- vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
+ sec_exec_controls_setbit(vmx,
SECONDARY_EXEC_APIC_REGISTER_VIRT |
SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
else
- vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
+ sec_exec_controls_clearbit(vmx,
SECONDARY_EXEC_APIC_REGISTER_VIRT |
SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
}
@@ -4020,8 +4020,7 @@ static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
if (cpu_has_secondary_exec_ctrls()) {
vmx_compute_secondary_exec_control(vmx);
- vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
- vmx->secondary_exec_control);
+ sec_exec_controls_init(vmx, vmx->secondary_exec_control);
}
if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
@@ -5935,6 +5934,7 @@ static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
{
+ struct vcpu_vmx *vmx = to_vmx(vcpu);
u32 sec_exec_control;
if (!lapic_in_kernel(vcpu))
@@ -5946,11 +5946,11 @@ void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
/* Postpone execution until vmcs01 is the current VMCS. */
if (is_guest_mode(vcpu)) {
- to_vmx(vcpu)->nested.change_vmcs01_virtual_apic_mode = true;
+ vmx->nested.change_vmcs01_virtual_apic_mode = true;
return;
}
- sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
+ sec_exec_control = sec_exec_controls_get(vmx);
sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
@@ -5972,7 +5972,7 @@ void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
break;
}
- vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
+ sec_exec_controls_set(vmx, sec_exec_control);
vmx_update_msr_bitmap(vcpu);
}
@@ -6776,7 +6776,7 @@ static int vmx_get_lpage_level(void)
return PT_PDPE_LEVEL;
}
-static void vmcs_set_secondary_exec_control(u32 new_ctl)
+static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
{
/*
* These bits in the secondary execution controls field
@@ -6790,10 +6790,10 @@ static void vmcs_set_secondary_exec_control(u32 new_ctl)
SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
SECONDARY_EXEC_DESC;
- u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
+ u32 new_ctl = vmx->secondary_exec_control;
+ u32 cur_ctl = sec_exec_controls_get(vmx);
- vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
- (new_ctl & ~mask) | (cur_ctl & mask));
+ sec_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
}
/*
@@ -6955,7 +6955,7 @@ static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
if (cpu_has_secondary_exec_ctrls()) {
vmx_compute_secondary_exec_control(vmx);
- vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
+ vmcs_set_secondary_exec_control(vmx);
}
if (nested_vmx_allowed(vcpu))
diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h
index 673cab3f6f66..7655ed28f12c 100644
--- a/arch/x86/kvm/vmx/vmx.h
+++ b/arch/x86/kvm/vmx/vmx.h
@@ -90,6 +90,7 @@ struct vmx_controls_shadow {
u32 vm_exit;
u32 pin;
u32 exec;
+ u32 sec_exec;
};
/*
@@ -414,6 +415,7 @@ BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS)
BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS)
BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL)
BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL)
+BUILD_CONTROLS_SHADOW(sec_exec, SECONDARY_VM_EXEC_CONTROL)
static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
{
--
2.21.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 05/13] KVM: VMX: Shadow VMCS secondary execution controls
2019-05-07 19:17 ` [PATCH 05/13] KVM: VMX: Shadow VMCS secondary " Sean Christopherson
@ 2019-06-06 16:59 ` Paolo Bonzini
0 siblings, 0 replies; 21+ messages in thread
From: Paolo Bonzini @ 2019-06-06 16:59 UTC (permalink / raw)
To: Sean Christopherson, Radim Krčmář; +Cc: kvm
On 07/05/19 21:17, Sean Christopherson wrote:
> Prepare to shadow all major control fields on a per-VMCS basis, which
> allows KVM to avoid costly VMWRITEs when switching between vmcs01 and
> vmcs02.
>
> Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
> ---
> arch/x86/kvm/vmx/nested.c | 12 ++++++------
> arch/x86/kvm/vmx/vmx.c | 40 +++++++++++++++++++--------------------
> arch/x86/kvm/vmx/vmx.h | 2 ++
> 3 files changed, 28 insertions(+), 26 deletions(-)
>
> diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
> index 7212cd04e9c2..007d03a49484 100644
> --- a/arch/x86/kvm/vmx/nested.c
> +++ b/arch/x86/kvm/vmx/nested.c
> @@ -182,7 +182,7 @@ static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
>
> static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
> {
> - vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
> + sec_exec_controls_clearbit(vmx, SECONDARY_EXEC_SHADOW_VMCS);
Prefer "secondary_exec_controls_*". Yes, it's a mouthful but it's more
consistent with code that is not about the shadowed control (such as the
constants, as in this line).
Paolo
> vmcs_write64(VMCS_LINK_POINTER, -1ull);
> }
>
> @@ -256,6 +256,7 @@ static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
> vm_exit_controls_reset_shadow(vmx);
> pin_controls_reset_shadow(vmx);
> exec_controls_reset_shadow(vmx);
> + sec_exec_controls_reset_shadow(vmx);
> vmx_segment_cache_clear(vmx);
> }
>
> @@ -2074,7 +2075,7 @@ static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
> if (exec_control & SECONDARY_EXEC_ENCLS_EXITING)
> vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
>
> - vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
> + sec_exec_controls_init(vmx, exec_control);
> }
>
> /*
> @@ -2849,8 +2850,8 @@ static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu)
> hpa = page_to_phys(vmx->nested.apic_access_page);
> vmcs_write64(APIC_ACCESS_ADDR, hpa);
> } else {
> - vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
> - SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
> + sec_exec_controls_clearbit(vmx,
> + SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
> }
> }
>
> @@ -4522,8 +4523,7 @@ static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
> {
> vmx->nested.current_vmptr = vmptr;
> if (enable_shadow_vmcs) {
> - vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
> - SECONDARY_EXEC_SHADOW_VMCS);
> + sec_exec_controls_setbit(vmx, SECONDARY_EXEC_SHADOW_VMCS);
> vmcs_write64(VMCS_LINK_POINTER,
> __pa(vmx->vmcs01.shadow_vmcs));
> vmx->nested.need_vmcs12_sync = true;
> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> index 278007885a8e..274b870f6511 100644
> --- a/arch/x86/kvm/vmx/vmx.c
> +++ b/arch/x86/kvm/vmx/vmx.c
> @@ -2879,6 +2879,7 @@ void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
>
> int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
> {
> + struct vcpu_vmx *vmx = to_vmx(vcpu);
> /*
> * Pass through host's Machine Check Enable value to hw_cr4, which
> * is in force while we are in guest mode. Do not let guests control
> @@ -2889,20 +2890,19 @@ int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
> hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
> if (enable_unrestricted_guest)
> hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
> - else if (to_vmx(vcpu)->rmode.vm86_active)
> + else if (vmx->rmode.vm86_active)
> hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
> else
> hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
>
> if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
> if (cr4 & X86_CR4_UMIP) {
> - vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
> - SECONDARY_EXEC_DESC);
> + sec_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
> hw_cr4 &= ~X86_CR4_UMIP;
> } else if (!is_guest_mode(vcpu) ||
> - !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC))
> - vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
> - SECONDARY_EXEC_DESC);
> + !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
> + sec_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
> + }
> }
>
> if (cr4 & X86_CR4_VMXE) {
> @@ -2917,7 +2917,7 @@ int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
> return 1;
> }
>
> - if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
> + if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
> return 1;
>
> vcpu->arch.cr4 = cr4;
> @@ -3535,7 +3535,7 @@ static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
> u8 mode = 0;
>
> if (cpu_has_secondary_exec_ctrls() &&
> - (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
> + (sec_exec_controls_get(to_vmx(vcpu)) &
> SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
> mode |= MSR_BITMAP_MODE_X2APIC;
> if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
> @@ -3818,11 +3818,11 @@ static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
> pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
> if (cpu_has_secondary_exec_ctrls()) {
> if (kvm_vcpu_apicv_active(vcpu))
> - vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
> + sec_exec_controls_setbit(vmx,
> SECONDARY_EXEC_APIC_REGISTER_VIRT |
> SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
> else
> - vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
> + sec_exec_controls_clearbit(vmx,
> SECONDARY_EXEC_APIC_REGISTER_VIRT |
> SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
> }
> @@ -4020,8 +4020,7 @@ static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
>
> if (cpu_has_secondary_exec_ctrls()) {
> vmx_compute_secondary_exec_control(vmx);
> - vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
> - vmx->secondary_exec_control);
> + sec_exec_controls_init(vmx, vmx->secondary_exec_control);
> }
>
> if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
> @@ -5935,6 +5934,7 @@ static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
>
> void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
> {
> + struct vcpu_vmx *vmx = to_vmx(vcpu);
> u32 sec_exec_control;
>
> if (!lapic_in_kernel(vcpu))
> @@ -5946,11 +5946,11 @@ void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
>
> /* Postpone execution until vmcs01 is the current VMCS. */
> if (is_guest_mode(vcpu)) {
> - to_vmx(vcpu)->nested.change_vmcs01_virtual_apic_mode = true;
> + vmx->nested.change_vmcs01_virtual_apic_mode = true;
> return;
> }
>
> - sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
> + sec_exec_control = sec_exec_controls_get(vmx);
> sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
> SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
>
> @@ -5972,7 +5972,7 @@ void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
> SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
> break;
> }
> - vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
> + sec_exec_controls_set(vmx, sec_exec_control);
>
> vmx_update_msr_bitmap(vcpu);
> }
> @@ -6776,7 +6776,7 @@ static int vmx_get_lpage_level(void)
> return PT_PDPE_LEVEL;
> }
>
> -static void vmcs_set_secondary_exec_control(u32 new_ctl)
> +static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
> {
> /*
> * These bits in the secondary execution controls field
> @@ -6790,10 +6790,10 @@ static void vmcs_set_secondary_exec_control(u32 new_ctl)
> SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
> SECONDARY_EXEC_DESC;
>
> - u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
> + u32 new_ctl = vmx->secondary_exec_control;
> + u32 cur_ctl = sec_exec_controls_get(vmx);
>
> - vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
> - (new_ctl & ~mask) | (cur_ctl & mask));
> + sec_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
> }
>
> /*
> @@ -6955,7 +6955,7 @@ static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
>
> if (cpu_has_secondary_exec_ctrls()) {
> vmx_compute_secondary_exec_control(vmx);
> - vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
> + vmcs_set_secondary_exec_control(vmx);
> }
>
> if (nested_vmx_allowed(vcpu))
> diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h
> index 673cab3f6f66..7655ed28f12c 100644
> --- a/arch/x86/kvm/vmx/vmx.h
> +++ b/arch/x86/kvm/vmx/vmx.h
> @@ -90,6 +90,7 @@ struct vmx_controls_shadow {
> u32 vm_exit;
> u32 pin;
> u32 exec;
> + u32 sec_exec;
> };
>
> /*
> @@ -414,6 +415,7 @@ BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS)
> BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS)
> BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL)
> BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL)
> +BUILD_CONTROLS_SHADOW(sec_exec, SECONDARY_VM_EXEC_CONTROL)
>
> static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
> {
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 06/13] KVM: nVMX: Shadow VMCS controls on a per-VMCS basis
2019-05-07 19:17 [PATCH 00/13] KVM: VMX: Reduce VMWRITEs to VMCS controls Sean Christopherson
` (4 preceding siblings ...)
2019-05-07 19:17 ` [PATCH 05/13] KVM: VMX: Shadow VMCS secondary " Sean Christopherson
@ 2019-05-07 19:17 ` Sean Christopherson
2019-05-07 19:17 ` [PATCH 07/13] KVM: nVMX: Don't reset VMCS controls shadow on VMCS switch Sean Christopherson
` (6 subsequent siblings)
12 siblings, 0 replies; 21+ messages in thread
From: Sean Christopherson @ 2019-05-07 19:17 UTC (permalink / raw)
To: Paolo Bonzini, Radim Krčmář; +Cc: kvm
... to pave the way for not preserving the shadow copies across switches
between vmcs01 and vmcs02, and eventually to avoid VMWRITEs to vmcs02
when the desired value is unchanged across nested VM-Enters.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
---
arch/x86/kvm/vmx/vmcs.h | 9 +++++++++
arch/x86/kvm/vmx/vmx.h | 22 +++++++---------------
2 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/arch/x86/kvm/vmx/vmcs.h b/arch/x86/kvm/vmx/vmcs.h
index cb6079f8a227..c09ae69155a8 100644
--- a/arch/x86/kvm/vmx/vmcs.h
+++ b/arch/x86/kvm/vmx/vmcs.h
@@ -42,6 +42,14 @@ struct vmcs_host_state {
#endif
};
+struct vmcs_controls_shadow {
+ u32 vm_entry;
+ u32 vm_exit;
+ u32 pin;
+ u32 exec;
+ u32 sec_exec;
+};
+
/*
* Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
* remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
@@ -61,6 +69,7 @@ struct loaded_vmcs {
unsigned long *msr_bitmap;
struct list_head loaded_vmcss_on_cpu_link;
struct vmcs_host_state host_state;
+ struct vmcs_controls_shadow controls_shadow;
};
static inline bool is_exception_n(u32 intr_info, u8 vector)
diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h
index 7655ed28f12c..2c367011df98 100644
--- a/arch/x86/kvm/vmx/vmx.h
+++ b/arch/x86/kvm/vmx/vmx.h
@@ -85,14 +85,6 @@ struct pt_desc {
struct pt_ctx guest;
};
-struct vmx_controls_shadow {
- u32 vm_entry;
- u32 vm_exit;
- u32 pin;
- u32 exec;
- u32 sec_exec;
-};
-
/*
* The nested_vmx structure is part of vcpu_vmx, and holds information we need
* for correct emulation of VMX (i.e., nested VMX) on this vcpu.
@@ -192,8 +184,6 @@ struct vcpu_vmx {
u32 idt_vectoring_info;
ulong rflags;
- struct vmx_controls_shadow controls_shadow;
-
struct shared_msr_entry *guest_msrs;
int nmsrs;
int save_nmsrs;
@@ -387,21 +377,23 @@ static inline u8 vmx_get_rvi(void)
#define BUILD_CONTROLS_SHADOW(lname, uname) \
static inline void lname##_controls_reset_shadow(struct vcpu_vmx *vmx) \
{ \
- vmx->controls_shadow.lname = vmcs_read32(uname); \
+ vmx->loaded_vmcs->controls_shadow.lname = vmcs_read32(uname); \
} \
static inline void lname##_controls_init(struct vcpu_vmx *vmx, u32 val) \
{ \
vmcs_write32(uname, val); \
- vmx->controls_shadow.lname = val; \
+ vmx->loaded_vmcs->controls_shadow.lname = val; \
} \
static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val) \
{ \
- if (vmx->controls_shadow.lname != val) \
- lname##_controls_init(vmx, val); \
+ if (vmx->loaded_vmcs->controls_shadow.lname != val) { \
+ vmcs_write32(uname, val); \
+ vmx->loaded_vmcs->controls_shadow.lname = val; \
+ } \
} \
static inline u32 lname##_controls_get(struct vcpu_vmx *vmx) \
{ \
- return vmx->controls_shadow.lname; \
+ return vmx->loaded_vmcs->controls_shadow.lname; \
} \
static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val) \
{ \
--
2.21.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 07/13] KVM: nVMX: Don't reset VMCS controls shadow on VMCS switch
2019-05-07 19:17 [PATCH 00/13] KVM: VMX: Reduce VMWRITEs to VMCS controls Sean Christopherson
` (5 preceding siblings ...)
2019-05-07 19:17 ` [PATCH 06/13] KVM: nVMX: Shadow VMCS controls on a per-VMCS basis Sean Christopherson
@ 2019-05-07 19:17 ` Sean Christopherson
2019-05-07 19:18 ` [PATCH 08/13] KVM: VMX: Explicitly initialize controls shadow at VMCS allocation Sean Christopherson
` (5 subsequent siblings)
12 siblings, 0 replies; 21+ messages in thread
From: Sean Christopherson @ 2019-05-07 19:17 UTC (permalink / raw)
To: Paolo Bonzini, Radim Krčmář; +Cc: kvm
... now that the shadow copies are per-VMCS.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
---
arch/x86/kvm/vmx/nested.c | 5 -----
arch/x86/kvm/vmx/vmx.h | 4 ----
2 files changed, 9 deletions(-)
diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index 007d03a49484..23be882e3365 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -252,11 +252,6 @@ static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
vmx_vcpu_load(vcpu, cpu);
put_cpu();
- vm_entry_controls_reset_shadow(vmx);
- vm_exit_controls_reset_shadow(vmx);
- pin_controls_reset_shadow(vmx);
- exec_controls_reset_shadow(vmx);
- sec_exec_controls_reset_shadow(vmx);
vmx_segment_cache_clear(vmx);
}
diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h
index 2c367011df98..c12c0aec13a5 100644
--- a/arch/x86/kvm/vmx/vmx.h
+++ b/arch/x86/kvm/vmx/vmx.h
@@ -375,10 +375,6 @@ static inline u8 vmx_get_rvi(void)
}
#define BUILD_CONTROLS_SHADOW(lname, uname) \
-static inline void lname##_controls_reset_shadow(struct vcpu_vmx *vmx) \
-{ \
- vmx->loaded_vmcs->controls_shadow.lname = vmcs_read32(uname); \
-} \
static inline void lname##_controls_init(struct vcpu_vmx *vmx, u32 val) \
{ \
vmcs_write32(uname, val); \
--
2.21.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 08/13] KVM: VMX: Explicitly initialize controls shadow at VMCS allocation
2019-05-07 19:17 [PATCH 00/13] KVM: VMX: Reduce VMWRITEs to VMCS controls Sean Christopherson
` (6 preceding siblings ...)
2019-05-07 19:17 ` [PATCH 07/13] KVM: nVMX: Don't reset VMCS controls shadow on VMCS switch Sean Christopherson
@ 2019-05-07 19:18 ` Sean Christopherson
2019-05-07 19:18 ` [PATCH 09/13] KVM: nVMX: Preserve last USE_MSR_BITMAPS when preparing vmcs02 Sean Christopherson
` (4 subsequent siblings)
12 siblings, 0 replies; 21+ messages in thread
From: Sean Christopherson @ 2019-05-07 19:18 UTC (permalink / raw)
To: Paolo Bonzini, Radim Krčmář; +Cc: kvm
Or: Don't re-initialize vmcs02's controls on every nested VM-Entry.
VMWRITEs to the major VMCS controls are deceptively expensive. Intel
CPUs with VMCS caching (Westmere and later) also optimize away
consistency checks on VM-Entry, i.e. skip consistency checks if the
relevant fields have not changed since the last successful VM-Entry (of
the cached VMCS). Because uops are a precious commodity, uCode's dirty
VMCS field tracking isn't as precise as software would prefer. Notably,
writing any of the major VMCS fields effectively marks the entire VMCS
dirty, i.e. causes the next VM-Entry to perform all consistency checks,
which consumes several hundred cycles.
Zero out the controls' shadow copies during VMCS allocation and use the
optimized setter when "initializing" controls. While this technically
affects both non-nested and nested virtualization, nested virtualization
is the primary beneficiary as avoid VMWRITEs when prepare vmcs02 allows
hardware to optimizie away consistency checks.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
---
arch/x86/kvm/vmx/nested.c | 10 +++++-----
arch/x86/kvm/vmx/vmx.c | 12 +++++++-----
arch/x86/kvm/vmx/vmx.h | 5 -----
3 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index 23be882e3365..cd1daf3b63a4 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -1997,7 +1997,7 @@ static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
} else {
exec_control &= ~PIN_BASED_POSTED_INTR;
}
- pin_controls_init(vmx, exec_control);
+ pin_controls_set(vmx, exec_control);
/*
* EXEC CONTROLS
@@ -2029,7 +2029,7 @@ static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
*/
exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
exec_control |= CPU_BASED_UNCOND_IO_EXITING;
- exec_controls_init(vmx, exec_control);
+ exec_controls_set(vmx, exec_control);
/*
* SECONDARY EXEC CONTROLS
@@ -2070,7 +2070,7 @@ static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
if (exec_control & SECONDARY_EXEC_ENCLS_EXITING)
vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
- sec_exec_controls_init(vmx, exec_control);
+ sec_exec_controls_set(vmx, exec_control);
}
/*
@@ -2089,7 +2089,7 @@ static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
if (guest_efer != host_efer)
exec_control |= VM_ENTRY_LOAD_IA32_EFER;
}
- vm_entry_controls_init(vmx, exec_control);
+ vm_entry_controls_set(vmx, exec_control);
/*
* EXIT CONTROLS
@@ -2101,7 +2101,7 @@ static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
exec_control = vmx_vmexit_ctrl();
if (cpu_has_load_ia32_efer() && guest_efer != host_efer)
exec_control |= VM_EXIT_LOAD_IA32_EFER;
- vm_exit_controls_init(vmx, exec_control);
+ vm_exit_controls_set(vmx, exec_control);
/*
* Conceptually we want to copy the PML address and index from
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 274b870f6511..eaa74c1e9a02 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -2455,6 +2455,8 @@ int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
}
memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
+ memset(&loaded_vmcs->controls_shadow, 0,
+ sizeof(struct vmcs_controls_shadow));
return 0;
@@ -4013,14 +4015,14 @@ static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
/* Control */
- pin_controls_init(vmx, vmx_pin_based_exec_ctrl(vmx));
+ pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
vmx->hv_deadline_tsc = -1;
- exec_controls_init(vmx, vmx_exec_control(vmx));
+ exec_controls_set(vmx, vmx_exec_control(vmx));
if (cpu_has_secondary_exec_ctrls()) {
vmx_compute_secondary_exec_control(vmx);
- sec_exec_controls_init(vmx, vmx->secondary_exec_control);
+ sec_exec_controls_set(vmx, vmx->secondary_exec_control);
}
if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
@@ -4078,10 +4080,10 @@ static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
++vmx->nmsrs;
}
- vm_exit_controls_init(vmx, vmx_vmexit_ctrl());
+ vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
/* 22.2.1, 20.8.1 */
- vm_entry_controls_init(vmx, vmx_vmentry_ctrl());
+ vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h
index c12c0aec13a5..ac40fc6859c1 100644
--- a/arch/x86/kvm/vmx/vmx.h
+++ b/arch/x86/kvm/vmx/vmx.h
@@ -375,11 +375,6 @@ static inline u8 vmx_get_rvi(void)
}
#define BUILD_CONTROLS_SHADOW(lname, uname) \
-static inline void lname##_controls_init(struct vcpu_vmx *vmx, u32 val) \
-{ \
- vmcs_write32(uname, val); \
- vmx->loaded_vmcs->controls_shadow.lname = val; \
-} \
static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val) \
{ \
if (vmx->loaded_vmcs->controls_shadow.lname != val) { \
--
2.21.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 09/13] KVM: nVMX: Preserve last USE_MSR_BITMAPS when preparing vmcs02
2019-05-07 19:17 [PATCH 00/13] KVM: VMX: Reduce VMWRITEs to VMCS controls Sean Christopherson
` (7 preceding siblings ...)
2019-05-07 19:18 ` [PATCH 08/13] KVM: VMX: Explicitly initialize controls shadow at VMCS allocation Sean Christopherson
@ 2019-05-07 19:18 ` Sean Christopherson
2019-06-06 17:12 ` Paolo Bonzini
2019-05-07 19:18 ` [PATCH 10/13] KVM: nVMX: Preset *DT exiting in vmcs02 when emulating UMIP Sean Christopherson
` (3 subsequent siblings)
12 siblings, 1 reply; 21+ messages in thread
From: Sean Christopherson @ 2019-05-07 19:18 UTC (permalink / raw)
To: Paolo Bonzini, Radim Krčmář; +Cc: kvm
KVM dynamically toggles the CPU_BASED_USE_MSR_BITMAPS execution control
for nested guests based on whether or not both L0 and L1 want to pass
through the same MSRs to L2. Preserve the last used value from vmcs02
so as to avoid multiple VMWRITEs to (re)set/(re)clear the bit on nested
VM-Entry.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
---
arch/x86/kvm/vmx/nested.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index cd1daf3b63a4..e4d363661ae7 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -2029,6 +2029,8 @@ static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
*/
exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
exec_control |= CPU_BASED_UNCOND_IO_EXITING;
+ if (!(exec_controls_get(vmx) & CPU_BASED_USE_MSR_BITMAPS))
+ exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
exec_controls_set(vmx, exec_control);
/*
--
2.21.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 09/13] KVM: nVMX: Preserve last USE_MSR_BITMAPS when preparing vmcs02
2019-05-07 19:18 ` [PATCH 09/13] KVM: nVMX: Preserve last USE_MSR_BITMAPS when preparing vmcs02 Sean Christopherson
@ 2019-06-06 17:12 ` Paolo Bonzini
0 siblings, 0 replies; 21+ messages in thread
From: Paolo Bonzini @ 2019-06-06 17:12 UTC (permalink / raw)
To: Sean Christopherson, Radim Krčmář; +Cc: kvm
On 07/05/19 21:18, Sean Christopherson wrote:
> KVM dynamically toggles the CPU_BASED_USE_MSR_BITMAPS execution control
> for nested guests based on whether or not both L0 and L1 want to pass
> through the same MSRs to L2. Preserve the last used value from vmcs02
> so as to avoid multiple VMWRITEs to (re)set/(re)clear the bit on nested
> VM-Entry.
>
> Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Needs a comment in code, and also leaves you puzzled as to why it's only
necessary to clear it. We can even let the compiler merge the
two "exec_control &= ~FOO" so that we don't even spend a precious instruction
on the AND:
diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index 1150831e4a9b..2e086d5ab837 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -2048,10 +2048,18 @@ static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
* A vmexit (to either L1 hypervisor or L0 userspace) is always needed
* for I/O port accesses.
*/
- exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
exec_control |= CPU_BASED_UNCOND_IO_EXITING;
- if (!(exec_controls_get(vmx) & CPU_BASED_USE_MSR_BITMAPS))
- exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
+ exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
+
+ /*
+ * This bit will be computed in nested_get_vmcs12_pages, because
+ * we do not have access to L1's MSR bitmap yet. For now, keep
+ * the same bit as before, hoping to avoid multiple VMWRITEs that
+ * only set/clear this bit.
+ */
+ exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
+ exec_control |= exec_controls_get(vmx) & CPU_BASED_USE_MSR_BITMAPS;
+
exec_controls_set(vmx, exec_control);
/*
Paolo
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 10/13] KVM: nVMX: Preset *DT exiting in vmcs02 when emulating UMIP
2019-05-07 19:17 [PATCH 00/13] KVM: VMX: Reduce VMWRITEs to VMCS controls Sean Christopherson
` (8 preceding siblings ...)
2019-05-07 19:18 ` [PATCH 09/13] KVM: nVMX: Preserve last USE_MSR_BITMAPS when preparing vmcs02 Sean Christopherson
@ 2019-05-07 19:18 ` Sean Christopherson
2019-06-06 17:15 ` Paolo Bonzini
2019-05-07 19:18 ` [PATCH 11/13] KVM: VMX: Drop hv_timer_armed from 'struct loaded_vmcs' Sean Christopherson
` (2 subsequent siblings)
12 siblings, 1 reply; 21+ messages in thread
From: Sean Christopherson @ 2019-05-07 19:18 UTC (permalink / raw)
To: Paolo Bonzini, Radim Krčmář; +Cc: kvm
KVM dynamically toggles SECONDARY_EXEC_DESC to intercept (a subset of)
instructions that are subject to User-Mode Instruction Prevention, i.e.
VMCS.SECONDARY_EXEC_DESC == CR4.UMIP when emulating UMIP. Preset the
VMCS control when preparing vmcs02 to avoid unnecessarily VMWRITEs,
e.g. KVM will clear VMCS.SECONDARY_EXEC_DESC in prepare_vmcs02_early()
and then set it in vmx_set_cr4().
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
---
arch/x86/kvm/vmx/nested.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index e4d363661ae7..4b5be38cfc86 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -2057,6 +2057,11 @@ static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
/* VMCS shadowing for L2 is emulated for now */
exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
+ /* Preset *DT exiting when emulating UMIP (vmx_set_cr4()). */
+ if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated() &&
+ (vmcs12->guest_cr4 & X86_CR4_UMIP))
+ exec_control |= SECONDARY_EXEC_DESC;
+
if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
vmcs_write16(GUEST_INTR_STATUS,
vmcs12->guest_intr_status);
--
2.21.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 10/13] KVM: nVMX: Preset *DT exiting in vmcs02 when emulating UMIP
2019-05-07 19:18 ` [PATCH 10/13] KVM: nVMX: Preset *DT exiting in vmcs02 when emulating UMIP Sean Christopherson
@ 2019-06-06 17:15 ` Paolo Bonzini
0 siblings, 0 replies; 21+ messages in thread
From: Paolo Bonzini @ 2019-06-06 17:15 UTC (permalink / raw)
To: Sean Christopherson, Radim Krčmář; +Cc: kvm
On 07/05/19 21:18, Sean Christopherson wrote:
> KVM dynamically toggles SECONDARY_EXEC_DESC to intercept (a subset of)
> instructions that are subject to User-Mode Instruction Prevention, i.e.
> VMCS.SECONDARY_EXEC_DESC == CR4.UMIP when emulating UMIP. Preset the
> VMCS control when preparing vmcs02 to avoid unnecessarily VMWRITEs,
> e.g. KVM will clear VMCS.SECONDARY_EXEC_DESC in prepare_vmcs02_early()
> and then set it in vmx_set_cr4().
>
> Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
> ---
> arch/x86/kvm/vmx/nested.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
> index e4d363661ae7..4b5be38cfc86 100644
> --- a/arch/x86/kvm/vmx/nested.c
> +++ b/arch/x86/kvm/vmx/nested.c
> @@ -2057,6 +2057,11 @@ static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
> /* VMCS shadowing for L2 is emulated for now */
> exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
>
> + /* Preset *DT exiting when emulating UMIP (vmx_set_cr4()). */
> + if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated() &&
> + (vmcs12->guest_cr4 & X86_CR4_UMIP))
> + exec_control |= SECONDARY_EXEC_DESC;
I am not sure how used this functionality is, but I guess it's not a big
price to pay. However, --verbose is preferred:
/*
* Preset *DT exiting when emulating UMIP, so that vmx_set_cr4()
* will not have to rewrite the controls just for this bit.
*/
Paolo
> if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
> vmcs_write16(GUEST_INTR_STATUS,
> vmcs12->guest_intr_status);
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 11/13] KVM: VMX: Drop hv_timer_armed from 'struct loaded_vmcs'
2019-05-07 19:17 [PATCH 00/13] KVM: VMX: Reduce VMWRITEs to VMCS controls Sean Christopherson
` (9 preceding siblings ...)
2019-05-07 19:18 ` [PATCH 10/13] KVM: nVMX: Preset *DT exiting in vmcs02 when emulating UMIP Sean Christopherson
@ 2019-05-07 19:18 ` Sean Christopherson
2019-05-07 19:18 ` [PATCH 12/13] KVM: nVMX: Don't mark vmcs12 as dirty when L1 writes pin controls Sean Christopherson
2019-05-07 19:18 ` [PATCH 13/13] KVM: VMX: Leave preemption timer running when it's disabled Sean Christopherson
12 siblings, 0 replies; 21+ messages in thread
From: Sean Christopherson @ 2019-05-07 19:18 UTC (permalink / raw)
To: Paolo Bonzini, Radim Krčmář; +Cc: kvm
... now that it is fully redundant with the pin controls shadow.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
---
arch/x86/kvm/vmx/nested.c | 1 -
arch/x86/kvm/vmx/vmcs.h | 1 -
arch/x86/kvm/vmx/vmx.c | 8 ++------
3 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index 4b5be38cfc86..6ecdcfc67245 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -1988,7 +1988,6 @@ static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
exec_control |= vmcs12->pin_based_vm_exec_control;
/* Preemption timer setting is computed directly in vmx_vcpu_run. */
exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
- vmx->loaded_vmcs->hv_timer_armed = false;
/* Posted interrupts setting is only taken from vmcs12. */
if (nested_cpu_has_posted_intr(vmcs12)) {
diff --git a/arch/x86/kvm/vmx/vmcs.h b/arch/x86/kvm/vmx/vmcs.h
index c09ae69155a8..52657d747668 100644
--- a/arch/x86/kvm/vmx/vmcs.h
+++ b/arch/x86/kvm/vmx/vmcs.h
@@ -61,7 +61,6 @@ struct loaded_vmcs {
int cpu;
bool launched;
bool nmi_known_unmasked;
- bool hv_timer_armed;
/* Support for vnmi-less CPUs */
int soft_vnmi_blocked;
ktime_t entry_time;
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index eaa74c1e9a02..70e9109b6481 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -6320,9 +6320,7 @@ static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
static void vmx_arm_hv_timer(struct vcpu_vmx *vmx, u32 val)
{
vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, val);
- if (!vmx->loaded_vmcs->hv_timer_armed)
- pin_controls_setbit(vmx, PIN_BASED_VMX_PREEMPTION_TIMER);
- vmx->loaded_vmcs->hv_timer_armed = true;
+ pin_controls_setbit(vmx, PIN_BASED_VMX_PREEMPTION_TIMER);
}
static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
@@ -6349,9 +6347,7 @@ static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
return;
}
- if (vmx->loaded_vmcs->hv_timer_armed)
- pin_controls_clearbit(vmx, PIN_BASED_VMX_PREEMPTION_TIMER);
- vmx->loaded_vmcs->hv_timer_armed = false;
+ pin_controls_clearbit(vmx, PIN_BASED_VMX_PREEMPTION_TIMER);
}
void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
--
2.21.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 12/13] KVM: nVMX: Don't mark vmcs12 as dirty when L1 writes pin controls
2019-05-07 19:17 [PATCH 00/13] KVM: VMX: Reduce VMWRITEs to VMCS controls Sean Christopherson
` (10 preceding siblings ...)
2019-05-07 19:18 ` [PATCH 11/13] KVM: VMX: Drop hv_timer_armed from 'struct loaded_vmcs' Sean Christopherson
@ 2019-05-07 19:18 ` Sean Christopherson
2019-06-06 17:16 ` Paolo Bonzini
2019-06-06 17:24 ` Paolo Bonzini
2019-05-07 19:18 ` [PATCH 13/13] KVM: VMX: Leave preemption timer running when it's disabled Sean Christopherson
12 siblings, 2 replies; 21+ messages in thread
From: Sean Christopherson @ 2019-05-07 19:18 UTC (permalink / raw)
To: Paolo Bonzini, Radim Krčmář; +Cc: kvm
Pin controls doesn't affect dirty logic, e.g. the preemption timer value
is loaded from vmcs12 even if vmcs12 is "clean", i.e. there is no need
to mark vmcs12 dirty when L1 writes pin controls.
KVM currently toggles the VMX_PREEMPTION_TIMER control flag when it
disables or enables the timer. The VMWRITE to toggle the flag can be
responsible for a large percentage of vmcs12 dirtying when running KVM
as L1 (depending on the behavior of L2).
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
---
arch/x86/kvm/vmx/nested.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index 6ecdcfc67245..652022a77b64 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -4508,8 +4508,12 @@ static int handle_vmwrite(struct kvm_vcpu *vcpu)
/*
* The fields that can be updated by L1 without a vmexit are
* always updated in the vmcs02, the others go down the slow
- * path of prepare_vmcs02.
+ * path of prepare_vmcs02. Pin controls is an exception as
+ * writing pin controls doesn't affect KVM's dirty logic and
+ * the VMX_PREEMPTION_TIMER flag may be toggled frequently,
+ * but not frequently enough to justify shadowing.
*/
+ case PIN_BASED_VM_EXEC_CONTROL:
break;
default:
vmx->nested.dirty_vmcs12 = true;
--
2.21.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 12/13] KVM: nVMX: Don't mark vmcs12 as dirty when L1 writes pin controls
2019-05-07 19:18 ` [PATCH 12/13] KVM: nVMX: Don't mark vmcs12 as dirty when L1 writes pin controls Sean Christopherson
@ 2019-06-06 17:16 ` Paolo Bonzini
2019-06-06 17:24 ` Paolo Bonzini
1 sibling, 0 replies; 21+ messages in thread
From: Paolo Bonzini @ 2019-06-06 17:16 UTC (permalink / raw)
To: Sean Christopherson, Radim Krčmář; +Cc: kvm
On 07/05/19 21:18, Sean Christopherson wrote:
> + * path of prepare_vmcs02. Pin controls is an exception as
> + * writing pin controls doesn't affect KVM's dirty logic and
> + * the VMX_PREEMPTION_TIMER flag may be toggled frequently,
> + * but not frequently enough to justify shadowing.
> */
> + case PIN_BASED_VM_EXEC_CONTROL:
> break;
Hmm, is it really that bad to shadow it?
Paolo
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 12/13] KVM: nVMX: Don't mark vmcs12 as dirty when L1 writes pin controls
2019-05-07 19:18 ` [PATCH 12/13] KVM: nVMX: Don't mark vmcs12 as dirty when L1 writes pin controls Sean Christopherson
2019-06-06 17:16 ` Paolo Bonzini
@ 2019-06-06 17:24 ` Paolo Bonzini
2019-06-06 19:05 ` Sean Christopherson
1 sibling, 1 reply; 21+ messages in thread
From: Paolo Bonzini @ 2019-06-06 17:24 UTC (permalink / raw)
To: Sean Christopherson, Radim Krčmář; +Cc: kvm
On 07/05/19 21:18, Sean Christopherson wrote:
> Pin controls doesn't affect dirty logic, e.g. the preemption timer value
> is loaded from vmcs12 even if vmcs12 is "clean", i.e. there is no need
> to mark vmcs12 dirty when L1 writes pin controls.
>
> KVM currently toggles the VMX_PREEMPTION_TIMER control flag when it
> disables or enables the timer. The VMWRITE to toggle the flag can be
> responsible for a large percentage of vmcs12 dirtying when running KVM
> as L1 (depending on the behavior of L2).
>
> Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
I think either we wait for patch 13 to get in the wild so that
VMX_PREEMPTION_TIMER writes do not become so frequent, or we can do
something like
--------- 8< ------------
From: Paolo Bonzini <pbonzini@redhat.com>
Subject: [PATCH] KVM: nVMX: shadow pin based execution controls
The VMX_PREEMPTION_TIMER flag may be toggled frequently, though not
*very* frequently. Since it does not affect KVM's dirty logic, e.g.
the preemption timer value is loaded from vmcs12 even if vmcs12 is
"clean", there is no need to mark vmcs12 dirty when L1 writes pin
controls, and shadowing the field achieves that.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
diff --git a/arch/x86/kvm/vmx/vmcs_shadow_fields.h
b/arch/x86/kvm/vmx/vmcs_shadow_fields.h
index 4cea018ba285..eb1ecd16fd22 100644
--- a/arch/x86/kvm/vmx/vmcs_shadow_fields.h
+++ b/arch/x86/kvm/vmx/vmcs_shadow_fields.h
@@ -47,6 +47,7 @@
SHADOW_FIELD_RO(GUEST_CS_AR_BYTES, guest_cs_ar_bytes)
SHADOW_FIELD_RO(GUEST_SS_AR_BYTES, guest_ss_ar_bytes)
SHADOW_FIELD_RW(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control)
+SHADOW_FIELD_RW(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control)
SHADOW_FIELD_RW(EXCEPTION_BITMAP, exception_bitmap)
SHADOW_FIELD_RW(VM_ENTRY_EXCEPTION_ERROR_CODE,
vm_entry_exception_error_code)
SHADOW_FIELD_RW(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field)
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 12/13] KVM: nVMX: Don't mark vmcs12 as dirty when L1 writes pin controls
2019-06-06 17:24 ` Paolo Bonzini
@ 2019-06-06 19:05 ` Sean Christopherson
0 siblings, 0 replies; 21+ messages in thread
From: Sean Christopherson @ 2019-06-06 19:05 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: Radim Krčmář, kvm
On Thu, Jun 06, 2019 at 07:24:38PM +0200, Paolo Bonzini wrote:
> On 07/05/19 21:18, Sean Christopherson wrote:
> > Pin controls doesn't affect dirty logic, e.g. the preemption timer value
> > is loaded from vmcs12 even if vmcs12 is "clean", i.e. there is no need
> > to mark vmcs12 dirty when L1 writes pin controls.
> >
> > KVM currently toggles the VMX_PREEMPTION_TIMER control flag when it
> > disables or enables the timer. The VMWRITE to toggle the flag can be
> > responsible for a large percentage of vmcs12 dirtying when running KVM
> > as L1 (depending on the behavior of L2).
> >
> > Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
>
> I think either we wait for patch 13 to get in the wild so that
> VMX_PREEMPTION_TIMER writes do not become so frequent, or we can do
> something like
I'd prefer to get something in now. I assume a fair number of users will
be running current/older versions of KVM as L1 for years to come.
I have no objection to shadowing pin controls. I opted for the cheesy
approach because I couldn't provide numbers that actually showed a
performance improvement by shadowing.
> --------- 8< ------------
> From: Paolo Bonzini <pbonzini@redhat.com>
> Subject: [PATCH] KVM: nVMX: shadow pin based execution controls
>
> The VMX_PREEMPTION_TIMER flag may be toggled frequently, though not
> *very* frequently. Since it does not affect KVM's dirty logic, e.g.
> the preemption timer value is loaded from vmcs12 even if vmcs12 is
> "clean", there is no need to mark vmcs12 dirty when L1 writes pin
> controls, and shadowing the field achieves that.
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
>
> diff --git a/arch/x86/kvm/vmx/vmcs_shadow_fields.h
> b/arch/x86/kvm/vmx/vmcs_shadow_fields.h
> index 4cea018ba285..eb1ecd16fd22 100644
> --- a/arch/x86/kvm/vmx/vmcs_shadow_fields.h
> +++ b/arch/x86/kvm/vmx/vmcs_shadow_fields.h
> @@ -47,6 +47,7 @@
> SHADOW_FIELD_RO(GUEST_CS_AR_BYTES, guest_cs_ar_bytes)
> SHADOW_FIELD_RO(GUEST_SS_AR_BYTES, guest_ss_ar_bytes)
> SHADOW_FIELD_RW(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control)
> +SHADOW_FIELD_RW(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control)
> SHADOW_FIELD_RW(EXCEPTION_BITMAP, exception_bitmap)
> SHADOW_FIELD_RW(VM_ENTRY_EXCEPTION_ERROR_CODE,
> vm_entry_exception_error_code)
> SHADOW_FIELD_RW(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field)
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 13/13] KVM: VMX: Leave preemption timer running when it's disabled
2019-05-07 19:17 [PATCH 00/13] KVM: VMX: Reduce VMWRITEs to VMCS controls Sean Christopherson
` (11 preceding siblings ...)
2019-05-07 19:18 ` [PATCH 12/13] KVM: nVMX: Don't mark vmcs12 as dirty when L1 writes pin controls Sean Christopherson
@ 2019-05-07 19:18 ` Sean Christopherson
12 siblings, 0 replies; 21+ messages in thread
From: Sean Christopherson @ 2019-05-07 19:18 UTC (permalink / raw)
To: Paolo Bonzini, Radim Krčmář; +Cc: kvm
VMWRITEs to the major VMCS controls, pin controls included, are
deceptively expensive. CPUs with VMCS caching (Westmere and later) also
optimize away consistency checks on VM-Entry, i.e. skip consistency
checks if the relevant fields have not changed since the last successful
VM-Entry (of the cached VMCS). Because uops are a precious commodity,
uCode's dirty VMCS field tracking isn't as precise as software would
prefer. Notably, writing any of the major VMCS fields effectively marks
the entire VMCS dirty, i.e. causes the next VM-Entry to perform all
consistency checks, which consumes several hundred cycles.
As it pertains to KVM, toggling PIN_BASED_VMX_PREEMPTION_TIMER more than
doubles the latency of the next VM-Entry (and again when/if the flag is
toggled back). In a non-nested scenario, running a "standard" guest
with the preemption timer enabled, toggling the timer flag is uncommon
but not rare, e.g. roughly 1 in 10 entries. Disabling the preemption
timer can change these numbers due to its use for "immediate exits",
even when explicitly disabled by userspace.
Nested virtualization in particular is painful, as the timer flag is set
for the majority of VM-Enters, but prepare_vmcs02() initializes vmcs02's
pin controls to *clear* the flag since its the timer's final state isn't
known until vmx_vcpu_run(). I.e. the majority of nested VM-Enters end
up unnecessarily writing pin controls *twice*.
Rather than toggle the timer flag in pin controls, set the timer value
itself to the largest allowed value to put it into a "soft disabled"
state, and ignore any spurious preemption timer exits.
Sadly, the timer is a 32-bit value and so theoretically it can fire
before the head death of the universe, i.e. spurious exits are possible.
But because KVM does *not* save the timer value on VM-Exit and because
the timer runs at a slower rate than the TSC, the maximuma timer value
is still sufficiently large for KVM's purposes. E.g. on a modern CPU
with a timer that runs at 1/32 the frequency of a 2.4ghz constant-rate
TSC, the timer will fire after ~55 seconds of *uninterrupted* guest
execution. In other words, spurious VM-Exits are effectively only
possible if the *host* is tickless on the logical CPU, the guest is
not using the preemption timer, and the guest is not generating VM-Exits
for *any* other reason.
To be safe from bad/weird hardware, disable the preemption timer if its
maximum delay is less than ten seconds. Ten seconds is mostly arbitrary
and was selected in no small part because it's a nice round number.
For simplicity and paranoia, fall back to __kvm_request_immediate_exit()
if the preemption timer is disabled by KVM or userspace. Previously
KVM continued to use the preemption timer to force immediate exits even
when the timer was disabled by userspace. Now that KVM leaves the timer
running instead of truly disabling it, allow userspace to kill it
entirely in the unlikely event the timer (or KVM) malfunctions.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
---
arch/x86/kvm/vmx/nested.c | 5 ++--
arch/x86/kvm/vmx/vmcs.h | 1 +
arch/x86/kvm/vmx/vmx.c | 60 +++++++++++++++++++++++++--------------
3 files changed, 41 insertions(+), 25 deletions(-)
diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index 652022a77b64..0b86f0990943 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -1985,9 +1985,8 @@ static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
* PIN CONTROLS
*/
exec_control = vmx_pin_based_exec_ctrl(vmx);
- exec_control |= vmcs12->pin_based_vm_exec_control;
- /* Preemption timer setting is computed directly in vmx_vcpu_run. */
- exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
+ exec_control |= (vmcs12->pin_based_vm_exec_control &
+ ~PIN_BASED_VMX_PREEMPTION_TIMER);
/* Posted interrupts setting is only taken from vmcs12. */
if (nested_cpu_has_posted_intr(vmcs12)) {
diff --git a/arch/x86/kvm/vmx/vmcs.h b/arch/x86/kvm/vmx/vmcs.h
index 52657d747668..c0abf06f245f 100644
--- a/arch/x86/kvm/vmx/vmcs.h
+++ b/arch/x86/kvm/vmx/vmcs.h
@@ -61,6 +61,7 @@ struct loaded_vmcs {
int cpu;
bool launched;
bool nmi_known_unmasked;
+ bool hv_timer_soft_disabled;
/* Support for vnmi-less CPUs */
int soft_vnmi_blocked;
ktime_t entry_time;
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 70e9109b6481..795a2000dd3f 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -2435,6 +2435,7 @@ int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
return -ENOMEM;
loaded_vmcs->shadow_vmcs = NULL;
+ loaded_vmcs->hv_timer_soft_disabled = false;
loaded_vmcs_init(loaded_vmcs);
if (cpu_has_vmx_msr_bitmap()) {
@@ -3808,8 +3809,9 @@ u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
if (!enable_vnmi)
pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
- /* Enable the preemption timer dynamically */
- pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
+ if (!enable_preemption_timer)
+ pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
+
return pin_based_exec_ctrl;
}
@@ -5430,8 +5432,12 @@ static int handle_pml_full(struct kvm_vcpu *vcpu)
static int handle_preemption_timer(struct kvm_vcpu *vcpu)
{
- if (!to_vmx(vcpu)->req_immediate_exit)
+ struct vcpu_vmx *vmx = to_vmx(vcpu);
+
+ if (!vmx->req_immediate_exit &&
+ !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
kvm_lapic_expired_hv_timer(vcpu);
+
return 1;
}
@@ -6317,12 +6323,6 @@ static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
msrs[i].host, false);
}
-static void vmx_arm_hv_timer(struct vcpu_vmx *vmx, u32 val)
-{
- vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, val);
- pin_controls_setbit(vmx, PIN_BASED_VMX_PREEMPTION_TIMER);
-}
-
static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
{
struct vcpu_vmx *vmx = to_vmx(vcpu);
@@ -6330,11 +6330,9 @@ static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
u32 delta_tsc;
if (vmx->req_immediate_exit) {
- vmx_arm_hv_timer(vmx, 0);
- return;
- }
-
- if (vmx->hv_deadline_tsc != -1) {
+ vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
+ vmx->loaded_vmcs->hv_timer_soft_disabled = false;
+ } else if (vmx->hv_deadline_tsc != -1) {
tscl = rdtsc();
if (vmx->hv_deadline_tsc > tscl)
/* set_hv_timer ensures the delta fits in 32-bits */
@@ -6343,11 +6341,12 @@ static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
else
delta_tsc = 0;
- vmx_arm_hv_timer(vmx, delta_tsc);
- return;
+ vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
+ vmx->loaded_vmcs->hv_timer_soft_disabled = false;
+ } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
+ vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
+ vmx->loaded_vmcs->hv_timer_soft_disabled = true;
}
-
- pin_controls_clearbit(vmx, PIN_BASED_VMX_PREEMPTION_TIMER);
}
void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
@@ -6419,7 +6418,8 @@ static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
atomic_switch_perf_msrs(vmx);
- vmx_update_hv_timer(vcpu);
+ if (enable_preemption_timer)
+ vmx_update_hv_timer(vcpu);
/*
* If this vCPU has touched SPEC_CTRL, restore the guest's value if
@@ -7533,17 +7533,33 @@ static __init int hardware_setup(void)
}
if (!cpu_has_vmx_preemption_timer())
- kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
+ enable_preemption_timer = false;
- if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
+ if (enable_preemption_timer) {
+ u64 use_timer_freq = 5000ULL * 1000 * 1000;
u64 vmx_msr;
rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
cpu_preemption_timer_multi =
vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
- } else {
+
+ if (tsc_khz)
+ use_timer_freq = (u64)tsc_khz * 1000;
+ use_timer_freq >>= cpu_preemption_timer_multi;
+
+ /*
+ * KVM "disables" the preemption timer by setting it to its max
+ * value. Don't use the timer if it might cause spurious exits
+ * at a rate faster than 0.1 Hz (of uninterrupted guest time).
+ */
+ if ((0xffffffffu / use_timer_freq) < 10)
+ enable_preemption_timer = false;
+ }
+
+ if (!enable_preemption_timer) {
kvm_x86_ops->set_hv_timer = NULL;
kvm_x86_ops->cancel_hv_timer = NULL;
+ kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
}
kvm_set_posted_intr_wakeup_handler(wakeup_handler);
--
2.21.0
^ permalink raw reply related [flat|nested] 21+ messages in thread