From: Stephen Boyd <sboyd@kernel.org>
To: chunhui.dai@mediatek.com, drinkcat@chromium.org,
eddie.huang@mediatek.com, erin.lo@mediatek.com,
jamesjj.liao@mediatek.com, jasu@njomotys.info,
mark.rutland@arm.com, matthias.bgg@gmail.com,
mturquette@baylibre.com, owen.chen@mediatek.com,
p.zabel@pengutronix.de, robh+dt@kernel.org,
weiyi.lu@mediatek.com
Cc: "yong.liang" <yong.liang@mediatek.com>,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 2/2] clk: reset: Modify reset-controller driver
Date: Thu, 06 Jun 2019 13:33:31 -0700 [thread overview]
Message-ID: <20190606203331.ED6AD2083E@mail.kernel.org> (raw)
In-Reply-To: <1556607888-10301-2-git-send-email-yong.liang@mediatek.com>
Forgot to mention, please Cc linux-clk@vger.kernel.org on clk drivers.
Quoting Yong Liang (2019-04-30 00:04:48)
> From: "yong.liang" <yong.liang@mediatek.com>
>
> Set reset signal by a register and clear reset signal by another register for 8183.
>
> Signed-off-by: yong.liang <yong.liang@mediatek.com>
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@kernel.org>
To: Yong Liang <yong.liang@mediatek.com>,
chunhui.dai@mediatek.com, drinkcat@chromium.org,
eddie.huang@mediatek.com, erin.lo@mediatek.com,
jamesjj.liao@mediatek.com, jasu@njomotys.info,
mark.rutland@arm.com, matthias.bgg@gmail.com,
mturquette@baylibre.com, owen.chen@mediatek.com,
p.zabel@pengutronix.de, robh+dt@kernel.org,
weiyi.lu@mediatek.com
Cc: "yong.liang" <yong.liang@mediatek.com>,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 2/2] clk: reset: Modify reset-controller driver
Date: Thu, 06 Jun 2019 13:33:31 -0700 [thread overview]
Message-ID: <20190606203331.ED6AD2083E@mail.kernel.org> (raw)
In-Reply-To: <1556607888-10301-2-git-send-email-yong.liang@mediatek.com>
Forgot to mention, please Cc linux-clk@vger.kernel.org on clk drivers.
Quoting Yong Liang (2019-04-30 00:04:48)
> From: "yong.liang" <yong.liang@mediatek.com>
>
> Set reset signal by a register and clear reset signal by another register for 8183.
>
> Signed-off-by: yong.liang <yong.liang@mediatek.com>
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next prev parent reply other threads:[~2019-06-06 20:33 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-30 7:04 [PATCH v3 1/2] arm64: dts: mt8183: Add reset-cells in infracfg Yong Liang
2019-04-30 7:04 ` Yong Liang
2019-04-30 7:04 ` [PATCH v3 2/2] clk: reset: Modify reset-controller driver Yong Liang
2019-04-30 7:04 ` Yong Liang
2019-06-06 20:32 ` Stephen Boyd
2019-06-06 20:32 ` Stephen Boyd
2019-06-06 20:33 ` Stephen Boyd [this message]
2019-06-06 20:33 ` Stephen Boyd
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