From: Bjorn Helgaas <helgaas@kernel.org>
To: Hannes Reinecke <hare@suse.de>
Cc: Daniel Drake <drake@endlessm.com>, Jens Axboe <axboe@kernel.dk>,
Sagi Grimberg <sagi@grimberg.me>,
Linux PCI <linux-pci@vger.kernel.org>,
Keith Busch <keith.busch@gmail.com>,
linux-ide@vger.kernel.org,
linux-nvme <linux-nvme@lists.infradead.org>,
Keith Busch <kbusch@kernel.org>,
Linux Upstreaming Team <linux@endlessm.com>,
Christoph Hellwig <hch@lst.de>
Subject: Re: [PATCH] PCI: Add Intel remapped NVMe device support
Date: Wed, 19 Jun 2019 08:52:12 -0500 [thread overview]
Message-ID: <20190619135212.GB143205@google.com> (raw)
In-Reply-To: <1f56c881-9005-f8ad-1557-5efd6e0ef535@suse.de>
On Tue, Jun 18, 2019 at 05:15:52PM +0200, Hannes Reinecke wrote:
> On 6/18/19 10:06 AM, Daniel Drake wrote:
> > We can probably also use these registers for MSI support. I
> > started to experiment, doesn't quite work but I'll keep poking.
> > The doc suggests there is a single MSI-X vector for the AHCI SATA
> > device, and AHCI MSI-X Starting Vector (AMXV) has value 0x140 on
> > this platform. No idea how to interpret that value. From
> > experimentation, the AHCI SATA disk generates interrupts on vector
> > 0.
> >
> The 0x140 is probably the offset into the PCI config space where the
> AHCI MSI-X vector table can be found ...
An MSI-X vector table is in memory space, not config space. You'd
have to look at PCI_MSIX_TABLE_BIR to find which BAR maps it, and then
add PCI_MSIX_TABLE_OFFSET to the BAR value.
Bjorn
WARNING: multiple messages have this Message-ID (diff)
From: helgaas@kernel.org (Bjorn Helgaas)
Subject: [PATCH] PCI: Add Intel remapped NVMe device support
Date: Wed, 19 Jun 2019 08:52:12 -0500 [thread overview]
Message-ID: <20190619135212.GB143205@google.com> (raw)
In-Reply-To: <1f56c881-9005-f8ad-1557-5efd6e0ef535@suse.de>
On Tue, Jun 18, 2019@05:15:52PM +0200, Hannes Reinecke wrote:
> On 6/18/19 10:06 AM, Daniel Drake wrote:
> > We can probably also use these registers for MSI support. I
> > started to experiment, doesn't quite work but I'll keep poking.
> > The doc suggests there is a single MSI-X vector for the AHCI SATA
> > device, and AHCI MSI-X Starting Vector (AMXV) has value 0x140 on
> > this platform. No idea how to interpret that value. From
> > experimentation, the AHCI SATA disk generates interrupts on vector
> > 0.
> >
> The 0x140 is probably the offset into the PCI config space where the
> AHCI MSI-X vector table can be found ...
An MSI-X vector table is in memory space, not config space. You'd
have to look at PCI_MSIX_TABLE_BIR to find which BAR maps it, and then
add PCI_MSIX_TABLE_OFFSET to the BAR value.
Bjorn
next prev parent reply other threads:[~2019-06-19 13:52 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-10 7:44 [PATCH] PCI: Add Intel remapped NVMe device support Daniel Drake
2019-06-10 7:44 ` Daniel Drake
2019-06-10 16:00 ` Keith Busch
2019-06-10 16:00 ` Keith Busch
2019-06-11 2:46 ` Daniel Drake
2019-06-11 2:46 ` Daniel Drake
2019-06-12 14:32 ` Keith Busch
2019-06-12 14:32 ` Keith Busch
2019-06-13 8:54 ` Christoph Hellwig
2019-06-13 8:54 ` Christoph Hellwig
2019-06-14 2:26 ` Daniel Drake
2019-06-14 2:26 ` Daniel Drake
2019-06-14 19:36 ` Keith Busch
2019-06-14 19:36 ` Keith Busch
2019-06-14 20:05 ` Bjorn Helgaas
2019-06-14 20:05 ` Bjorn Helgaas
2019-06-14 21:05 ` Keith Busch
2019-06-14 21:05 ` Keith Busch
2019-06-18 7:48 ` Hannes Reinecke
2019-06-18 7:48 ` Hannes Reinecke
2019-06-18 7:46 ` Hannes Reinecke
2019-06-18 7:46 ` Hannes Reinecke
2019-06-18 8:06 ` Daniel Drake
2019-06-18 8:06 ` Daniel Drake
2019-06-18 15:15 ` Hannes Reinecke
2019-06-18 15:15 ` Hannes Reinecke
2019-06-19 13:52 ` Bjorn Helgaas [this message]
2019-06-19 13:52 ` Bjorn Helgaas
2019-06-10 21:16 ` Bjorn Helgaas
2019-06-10 21:16 ` Bjorn Helgaas
2019-06-11 3:25 ` Daniel Drake
2019-06-11 3:25 ` Daniel Drake
2019-06-11 19:52 ` Bjorn Helgaas
2019-06-11 19:52 ` Bjorn Helgaas
2019-06-12 3:16 ` Daniel Drake
2019-06-12 3:16 ` Daniel Drake
2019-06-12 13:49 ` Bjorn Helgaas
2019-06-12 13:49 ` Bjorn Helgaas
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190619135212.GB143205@google.com \
--to=helgaas@kernel.org \
--cc=axboe@kernel.dk \
--cc=drake@endlessm.com \
--cc=hare@suse.de \
--cc=hch@lst.de \
--cc=kbusch@kernel.org \
--cc=keith.busch@gmail.com \
--cc=linux-ide@vger.kernel.org \
--cc=linux-nvme@lists.infradead.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux@endlessm.com \
--cc=sagi@grimberg.me \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.