From: Maxime Ripard <maxime.ripard@bootlin.com>
To: Icenowy Zheng <icenowy@aosc.io>
Cc: Rob Herring <robh+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Linus Walleij <linus.walleij@linaro.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com
Subject: Re: [PATCH v3 1/9] pinctrl: sunxi: v3s: introduce support for V3
Date: Mon, 24 Jun 2019 14:40:19 +0200 [thread overview]
Message-ID: <20190624124019.o6acnnkjikekshl5@flea> (raw)
In-Reply-To: <20190623043801.14040-2-icenowy@aosc.io>
[-- Attachment #1: Type: text/plain, Size: 1578 bytes --]
On Sun, Jun 23, 2019 at 12:37:53PM +0800, Icenowy Zheng wrote:
> Introduce the GPIO pins that is only available on V3 (not on V3s) to the
> V3s pinctrl driver.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> Changes in v3:
> - Fixed code alignment.
> - Fixed LVDS function number.
>
> Changes in v2:
> - Dropped the driver rename patch and apply the changes directly on V3s
> driver.
>
> drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 473 +++++++++++++++++-----
> drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 +
> 2 files changed, 366 insertions(+), 109 deletions(-)
>
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
> index 6704ce8e5e3d..721c997d472b 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
> @@ -1,5 +1,5 @@
> /*
> - * Allwinner V3s SoCs pinctrl driver.
> + * Allwinner V3/V3s SoCs pinctrl driver.
> *
> * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
> *
> @@ -28,235 +28,433 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = {
> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> - SUNXI_FUNCTION(0x2, "uart2"), /* TX */
> - SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */
> + SUNXI_FUNCTION(0x2, "uart2"), /* TX */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */
I'm not sure why all that churn is needed.
Looks good otherwise.
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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WARNING: multiple messages have this Message-ID (diff)
From: Maxime Ripard <maxime.ripard@bootlin.com>
To: Icenowy Zheng <icenowy@aosc.io>
Cc: devicetree@vger.kernel.org,
Linus Walleij <linus.walleij@linaro.org>,
linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,
linux-gpio@vger.kernel.org, Chen-Yu Tsai <wens@csie.org>,
Rob Herring <robh+dt@kernel.org>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 1/9] pinctrl: sunxi: v3s: introduce support for V3
Date: Mon, 24 Jun 2019 14:40:19 +0200 [thread overview]
Message-ID: <20190624124019.o6acnnkjikekshl5@flea> (raw)
In-Reply-To: <20190623043801.14040-2-icenowy@aosc.io>
[-- Attachment #1.1: Type: text/plain, Size: 1578 bytes --]
On Sun, Jun 23, 2019 at 12:37:53PM +0800, Icenowy Zheng wrote:
> Introduce the GPIO pins that is only available on V3 (not on V3s) to the
> V3s pinctrl driver.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> Changes in v3:
> - Fixed code alignment.
> - Fixed LVDS function number.
>
> Changes in v2:
> - Dropped the driver rename patch and apply the changes directly on V3s
> driver.
>
> drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 473 +++++++++++++++++-----
> drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 +
> 2 files changed, 366 insertions(+), 109 deletions(-)
>
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
> index 6704ce8e5e3d..721c997d472b 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
> @@ -1,5 +1,5 @@
> /*
> - * Allwinner V3s SoCs pinctrl driver.
> + * Allwinner V3/V3s SoCs pinctrl driver.
> *
> * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
> *
> @@ -28,235 +28,433 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = {
> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> - SUNXI_FUNCTION(0x2, "uart2"), /* TX */
> - SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */
> + SUNXI_FUNCTION(0x2, "uart2"), /* TX */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */
I'm not sure why all that churn is needed.
Looks good otherwise.
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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WARNING: multiple messages have this Message-ID (diff)
From: Maxime Ripard <maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org>
To: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>,
Linus Walleij
<linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org
Subject: Re: [PATCH v3 1/9] pinctrl: sunxi: v3s: introduce support for V3
Date: Mon, 24 Jun 2019 14:40:19 +0200 [thread overview]
Message-ID: <20190624124019.o6acnnkjikekshl5@flea> (raw)
In-Reply-To: <20190623043801.14040-2-icenowy-h8G6r0blFSE@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1618 bytes --]
On Sun, Jun 23, 2019 at 12:37:53PM +0800, Icenowy Zheng wrote:
> Introduce the GPIO pins that is only available on V3 (not on V3s) to the
> V3s pinctrl driver.
>
> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
> ---
> Changes in v3:
> - Fixed code alignment.
> - Fixed LVDS function number.
>
> Changes in v2:
> - Dropped the driver rename patch and apply the changes directly on V3s
> driver.
>
> drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 473 +++++++++++++++++-----
> drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 +
> 2 files changed, 366 insertions(+), 109 deletions(-)
>
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
> index 6704ce8e5e3d..721c997d472b 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
> @@ -1,5 +1,5 @@
> /*
> - * Allwinner V3s SoCs pinctrl driver.
> + * Allwinner V3/V3s SoCs pinctrl driver.
> *
> * Copyright (C) 2016 Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> *
> @@ -28,235 +28,433 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = {
> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> - SUNXI_FUNCTION(0x2, "uart2"), /* TX */
> - SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */
> + SUNXI_FUNCTION(0x2, "uart2"), /* TX */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */
I'm not sure why all that churn is needed.
Looks good otherwise.
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
next prev parent reply other threads:[~2019-06-24 12:40 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-23 4:37 [PATCH v3 0/9] Support for Allwinner V3/S3L and Sochip S3 Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-06-23 4:37 ` [PATCH v3 1/9] pinctrl: sunxi: v3s: introduce support for V3 Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-06-24 12:40 ` Maxime Ripard [this message]
2019-06-24 12:40 ` Maxime Ripard
2019-06-24 12:40 ` Maxime Ripard
2019-06-25 13:57 ` Linus Walleij
2019-06-25 13:57 ` Linus Walleij
2019-06-25 13:57 ` Linus Walleij
2019-06-25 14:10 ` Maxime Ripard
2019-06-25 14:10 ` Maxime Ripard
2019-06-25 14:10 ` Maxime Ripard
2019-06-23 4:37 ` [PATCH v3 2/9] clk: sunxi-ng: v3s: add the missing PLL_DDR1 Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-06-23 4:37 ` [PATCH v3 3/9] dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-06-23 4:37 ` [PATCH v3 4/9] clk: sunxi-ng: v3s: add Allwinner V3 support Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-07-09 22:56 ` Rob Herring
2019-07-09 22:56 ` Rob Herring
2019-06-23 4:37 ` [PATCH v3 5/9] dt-bindings: vendor-prefixes: add SoChip Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-06-25 13:55 ` Linus Walleij
2019-06-25 13:55 ` Linus Walleij
2019-06-25 13:55 ` Linus Walleij
2019-06-25 17:39 ` Rob Herring
2019-06-25 17:39 ` Rob Herring
2019-06-23 4:37 ` [PATCH v3 6/9] ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-06-23 4:37 ` [PATCH v3 7/9] dt-bindings: vendor-prefixes: add Sipeed Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-07-09 22:57 ` Rob Herring
2019-07-09 22:57 ` Rob Herring
2019-07-09 22:57 ` Rob Herring
2019-06-23 4:38 ` [PATCH v3 8/9] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board Icenowy Zheng
2019-06-23 4:38 ` Icenowy Zheng
2019-06-23 4:38 ` Icenowy Zheng
2019-06-24 12:42 ` Maxime Ripard
2019-06-24 12:42 ` Maxime Ripard
2019-06-24 12:42 ` Maxime Ripard
2019-06-23 4:38 ` [PATCH v3 9/9] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 Icenowy Zheng
2019-06-23 4:38 ` Icenowy Zheng
2019-06-24 12:43 ` Maxime Ripard
2019-06-24 12:43 ` Maxime Ripard
2019-06-24 12:43 ` Maxime Ripard
2019-06-24 13:43 ` Icenowy Zheng
2019-06-24 13:43 ` Icenowy Zheng
2019-06-24 13:43 ` Icenowy Zheng
2019-06-24 13:48 ` Maxime Ripard
2019-06-24 13:48 ` Maxime Ripard
2019-06-24 13:48 ` Maxime Ripard
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