All of lore.kernel.org
 help / color / mirror / Atom feed
From: Marc Zyngier <maz@kernel.org>
To: Thomas Gleixner <tglx@linutronix.de>,
	Jason Cooper <jason@lakedaemon.net>,
	Julien Thierry <julien.thierry.kdev@gmail.com>,
	Rob Herring <robh+dt@kernel.org>
Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/9] dt-bindings: interrupt-controller: arm, gic-v3: Describe ESPI range support
Date: Tue, 23 Jul 2019 11:44:31 +0100	[thread overview]
Message-ID: <20190723104437.154403-4-maz@kernel.org> (raw)
In-Reply-To: <20190723104437.154403-1-maz@kernel.org>

GICv3.1 introduces support for new interrupt ranges, one of them being
the Extended SPI range (ESPI). The DT binding is extended to deal with
it as a new interrupt class.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 .../devicetree/bindings/interrupt-controller/arm,gic-v3.yaml | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
index c34df35a25fc..98a3ecda8e07 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
@@ -44,11 +44,12 @@ properties:
       be at least 4.
 
       The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
-      interrupts. Other values are reserved for future use.
+      interrupts, 2 for interrupts in the Extended SPI range. Other values
+      are reserved for future use.
 
       The 2nd cell contains the interrupt number for the interrupt type.
       SPI interrupts are in the range [0-987]. PPI interrupts are in the
-      range [0-15].
+      range [0-15]. Extented SPI interrupts are in the range [0-1023].
 
       The 3rd cell is the flags, encoded as follows:
       bits[3:0] trigger type and level flags.
-- 
2.20.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Thomas Gleixner <tglx@linutronix.de>,
	Jason Cooper <jason@lakedaemon.net>,
	Julien Thierry <julien.thierry.kdev@gmail.com>,
	Rob Herring <robh+dt@kernel.org>
Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/9] dt-bindings: interrupt-controller: arm,gic-v3: Describe ESPI range support
Date: Tue, 23 Jul 2019 11:44:31 +0100	[thread overview]
Message-ID: <20190723104437.154403-4-maz@kernel.org> (raw)
In-Reply-To: <20190723104437.154403-1-maz@kernel.org>

GICv3.1 introduces support for new interrupt ranges, one of them being
the Extended SPI range (ESPI). The DT binding is extended to deal with
it as a new interrupt class.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 .../devicetree/bindings/interrupt-controller/arm,gic-v3.yaml | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
index c34df35a25fc..98a3ecda8e07 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
@@ -44,11 +44,12 @@ properties:
       be at least 4.
 
       The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
-      interrupts. Other values are reserved for future use.
+      interrupts, 2 for interrupts in the Extended SPI range. Other values
+      are reserved for future use.
 
       The 2nd cell contains the interrupt number for the interrupt type.
       SPI interrupts are in the range [0-987]. PPI interrupts are in the
-      range [0-15].
+      range [0-15]. Extented SPI interrupts are in the range [0-1023].
 
       The 3rd cell is the flags, encoded as follows:
       bits[3:0] trigger type and level flags.
-- 
2.20.1


  parent reply	other threads:[~2019-07-23 10:46 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-23 10:44 [PATCH 0/9] irqchip/gic-v3: Add support for GICv3.1 extended PPI/SPI ranges Marc Zyngier
2019-07-23 10:44 ` Marc Zyngier
2019-07-23 10:44 ` [PATCH 1/9] irqchip/gic: Rework gic_configure_irq to take the full ICFGR base Marc Zyngier
2019-07-23 10:44   ` Marc Zyngier
2019-07-23 10:44 ` [PATCH 2/9] irqchip/gic-v3: Add INTID range and convertion primitives Marc Zyngier
2019-07-23 10:44   ` Marc Zyngier
2019-07-23 10:44 ` Marc Zyngier [this message]
2019-07-23 10:44   ` [PATCH 3/9] dt-bindings: interrupt-controller: arm,gic-v3: Describe ESPI range support Marc Zyngier
2019-07-23 12:59   ` [PATCH 3/9] dt-bindings: interrupt-controller: arm, gic-v3: " Lokesh Vutla
2019-07-23 12:59     ` Lokesh Vutla
2019-07-23 13:15     ` Marc Zyngier
2019-07-23 13:15       ` Marc Zyngier
2019-07-23 13:35       ` Lokesh Vutla
2019-07-23 13:35         ` Lokesh Vutla
2019-07-23 10:44 ` [PATCH 4/9] irqchip/gic-v3: Add " Marc Zyngier
2019-07-23 10:44   ` Marc Zyngier
2019-07-23 12:50   ` Lokesh Vutla
2019-07-23 12:50     ` Lokesh Vutla
2019-07-23 13:04     ` Marc Zyngier
2019-07-23 13:04       ` Marc Zyngier
2019-07-23 10:44 ` [PATCH 5/9] irqchip/gic: Prepare for more than 16 PPIs Marc Zyngier
2019-07-23 10:44   ` Marc Zyngier
2019-07-23 10:44 ` [PATCH 6/9] irqchip/gic-v3: Dynamically allocate PPI NMI refcounts Marc Zyngier
2019-07-23 10:44   ` Marc Zyngier
2019-07-23 10:44 ` [PATCH 7/9] irqchip/gic-v3: Dynamically allocate PPI partition descriptors Marc Zyngier
2019-07-23 10:44   ` Marc Zyngier
2019-07-23 10:44 ` [PATCH 8/9] dt-bindings: interrupt-controller: arm, gic-v3: Describe EPPI range support Marc Zyngier
2019-07-23 10:44   ` [PATCH 8/9] dt-bindings: interrupt-controller: arm,gic-v3: " Marc Zyngier
2019-07-23 10:44 ` [PATCH 9/9] irqchip/gic-v3: Add " Marc Zyngier
2019-07-23 10:44   ` Marc Zyngier

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20190723104437.154403-4-maz@kernel.org \
    --to=maz@kernel.org \
    --cc=jason@lakedaemon.net \
    --cc=julien.thierry.kdev@gmail.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=robh+dt@kernel.org \
    --cc=tglx@linutronix.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.