* [PATCH 0/3] Tiger Lake: register moves
@ 2019-07-26 0:24 Lucas De Marchi
2019-07-26 0:24 ` [PATCH 1/3] drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers Lucas De Marchi
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: Lucas De Marchi @ 2019-07-26 0:24 UTC (permalink / raw)
To: intel-gfx
Patches extracted from https://patchwork.freedesktop.org/series/63670/
and rebased.
Jordan Justen (1):
drm/i915/tgl: allow the reg_read ioctl to read the RCS TIMESTAMP
register
José Roberto de Souza (1):
drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers
Michel Thierry (1):
drm/i915/tgl: add support for reading the timestamp frequency
drivers/gpu/drm/i915/i915_debugfs.c | 21 +++++++++++++--------
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
4 files changed, 17 insertions(+), 10 deletions(-)
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/3] drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers
2019-07-26 0:24 [PATCH 0/3] Tiger Lake: register moves Lucas De Marchi
@ 2019-07-26 0:24 ` Lucas De Marchi
2019-07-26 4:04 ` Gupta, Anshuman
2019-07-26 0:24 ` [PATCH 2/3] drm/i915/tgl: allow the reg_read ioctl to read the RCS TIMESTAMP register Lucas De Marchi
` (3 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Lucas De Marchi @ 2019-07-26 0:24 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
Tiger Lake has a new register offset for DC5 and DC6 residency counters.
v2:
- Rename registers since they are not in the CSR memory range
(requested by Anshuman)
- Fix type (requested by Matthew)
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 21 +++++++++++++--------
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 24787bb48c9f..6dbd85b38759 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2465,6 +2465,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
intel_wakeref_t wakeref;
struct intel_csr *csr;
+ i915_reg_t dc5_reg, dc6_reg = {};
if (!HAS_CSR(dev_priv))
return -ENODEV;
@@ -2482,15 +2483,19 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
CSR_VERSION_MINOR(csr->version));
- if (WARN_ON(INTEL_GEN(dev_priv) > 11))
- goto out;
+ if (INTEL_GEN(dev_priv) >= 12) {
+ dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
+ dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
+ } else {
+ dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
+ SKL_CSR_DC3_DC5_COUNT;
+ if (!IS_GEN9_LP(dev_priv))
+ dc6_reg = SKL_CSR_DC5_DC6_COUNT;
+ }
- seq_printf(m, "DC3 -> DC5 count: %d\n",
- I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
- SKL_CSR_DC3_DC5_COUNT));
- if (!IS_GEN9_LP(dev_priv))
- seq_printf(m, "DC5 -> DC6 count: %d\n",
- I915_READ(SKL_CSR_DC5_DC6_COUNT));
+ seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(dc5_reg));
+ if (dc6_reg.reg)
+ seq_printf(m, "DC5 -> DC6 count: %d\n", I915_READ(dc6_reg));
out:
seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 24f2a52a2b42..e999ce94b45c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7268,6 +7268,8 @@ enum {
#define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
+#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
+#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
/* interrupts */
#define DE_MASTER_IRQ_CONTROL (1 << 31)
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/3] drm/i915/tgl: allow the reg_read ioctl to read the RCS TIMESTAMP register
2019-07-26 0:24 [PATCH 0/3] Tiger Lake: register moves Lucas De Marchi
2019-07-26 0:24 ` [PATCH 1/3] drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers Lucas De Marchi
@ 2019-07-26 0:24 ` Lucas De Marchi
2019-07-26 19:05 ` Rodrigo Vivi
2019-07-26 0:24 ` [PATCH 3/3] drm/i915/tgl: add support for reading the timestamp frequency Lucas De Marchi
` (2 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Lucas De Marchi @ 2019-07-26 0:24 UTC (permalink / raw)
To: intel-gfx
From: Jordan Justen <jordan.l.justen@intel.com>
This enables the Mesa driver to advertise support for ARB_timer_query,
and thus an OpenGL version higher than 3.2.
Based on the ICL patch by Paulo Zanoni and CNL patch by Nanley Chery.
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 475ab3d4d91d..2b839acfa0f6 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1776,7 +1776,7 @@ static const struct reg_whitelist {
} reg_read_whitelist[] = { {
.offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
- .gen_mask = INTEL_GEN_MASK(4, 11),
+ .gen_mask = INTEL_GEN_MASK(4, 12),
.size = 8
} };
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/3] drm/i915/tgl: add support for reading the timestamp frequency
2019-07-26 0:24 [PATCH 0/3] Tiger Lake: register moves Lucas De Marchi
2019-07-26 0:24 ` [PATCH 1/3] drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers Lucas De Marchi
2019-07-26 0:24 ` [PATCH 2/3] drm/i915/tgl: allow the reg_read ioctl to read the RCS TIMESTAMP register Lucas De Marchi
@ 2019-07-26 0:24 ` Lucas De Marchi
2019-07-26 3:37 ` ✓ Fi.CI.BAT: success for Tiger Lake: register moves Patchwork
2019-07-27 7:47 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 8+ messages in thread
From: Lucas De Marchi @ 2019-07-26 0:24 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry, Paulo Zanoni
From: Michel Thierry <michel.thierry@intel.com>
There are no changes with respect to GEN11, which Paulo wrote.
This gets rid of the "Missing switch case in read_timestamp_frequency"
message at boot for Tiger Lake.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index f99c9fd497b2..a3017d16b7f3 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -716,7 +716,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
}
return freq;
- } else if (INTEL_GEN(dev_priv) <= 11) {
+ } else if (INTEL_GEN(dev_priv) <= 12) {
u32 ctc_reg = I915_READ(CTC_MODE);
u32 freq = 0;
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* ✓ Fi.CI.BAT: success for Tiger Lake: register moves
2019-07-26 0:24 [PATCH 0/3] Tiger Lake: register moves Lucas De Marchi
` (2 preceding siblings ...)
2019-07-26 0:24 ` [PATCH 3/3] drm/i915/tgl: add support for reading the timestamp frequency Lucas De Marchi
@ 2019-07-26 3:37 ` Patchwork
2019-07-27 7:47 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2019-07-26 3:37 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Tiger Lake: register moves
URL : https://patchwork.freedesktop.org/series/64277/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6557 -> Patchwork_13767
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/
Known issues
------------
Here are the changes found in Patchwork_13767 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-blb-e6850/igt@i915_module_load@reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/fi-blb-e6850/igt@i915_module_load@reload.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u2: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] / [fdo#108569])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
* igt@vgem_basic@unload:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u3/igt@vgem_basic@unload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/fi-icl-u3/igt@vgem_basic@unload.html
#### Possible fixes ####
* igt@gem_ctx_exec@basic:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u3/igt@gem_ctx_exec@basic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/fi-icl-u3/igt@gem_ctx_exec@basic.html
* igt@i915_selftest@live_blt:
- fi-icl-dsi: [DMESG-FAIL][9] ([fdo#110899]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-dsi/igt@i915_selftest@live_blt.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/fi-icl-dsi/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-dsi: [INCOMPLETE][11] ([fdo#107713] / [fdo#108569]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: [WARN][13] ([fdo#109380]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-kbl-7567u/igt@kms_chamelium@common-hpd-after-suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/fi-kbl-7567u/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u: [SKIP][15] ([fdo#109271]) -> [PASS][16] +23 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-kbl-7567u/igt@kms_pipe_crc_basic@read-crc-pipe-c.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/fi-kbl-7567u/igt@kms_pipe_crc_basic@read-crc-pipe-c.html
#### Warnings ####
* igt@i915_module_load@reload:
- fi-icl-u3: [TIMEOUT][17] ([fdo#109673] / [fdo#111214]) -> [TIMEOUT][18] ([fdo#111214])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u3/igt@i915_module_load@reload.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/fi-icl-u3/igt@i915_module_load@reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
[fdo#110899]: https://bugs.freedesktop.org/show_bug.cgi?id=110899
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
Participating hosts (53 -> 46)
------------------------------
Additional (1): fi-pnv-d510
Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6557 -> Patchwork_13767
CI-20190529: 20190529
CI_DRM_6557: 2ebd69f583d23b295265832f168e39427a8bd863 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5112: 7e4d10507088055413769a020dd674f52b4bc1b0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13767: 2270b496234228cc38d706349c12b803f0f0289d @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2270b4962342 drm/i915/tgl: add support for reading the timestamp frequency
4976d96d503a drm/i915/tgl: allow the reg_read ioctl to read the RCS TIMESTAMP register
bdcfd5d99600 drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers
2019-07-26 0:24 ` [PATCH 1/3] drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers Lucas De Marchi
@ 2019-07-26 4:04 ` Gupta, Anshuman
0 siblings, 0 replies; 8+ messages in thread
From: Gupta, Anshuman @ 2019-07-26 4:04 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
On 7/26/2019 5:54 AM, Lucas De Marchi wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
>
> Tiger Lake has a new register offset for DC5 and DC6 residency counters.
>
> v2:
> - Rename registers since they are not in the CSR memory range
> (requested by Anshuman)
> - Fix type (requested by Matthew)
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Looks Good to me.
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 21 +++++++++++++--------
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 2 files changed, 15 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 24787bb48c9f..6dbd85b38759 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2465,6 +2465,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> intel_wakeref_t wakeref;
> struct intel_csr *csr;
> + i915_reg_t dc5_reg, dc6_reg = {};
>
> if (!HAS_CSR(dev_priv))
> return -ENODEV;
> @@ -2482,15 +2483,19 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
> CSR_VERSION_MINOR(csr->version));
>
> - if (WARN_ON(INTEL_GEN(dev_priv) > 11))
> - goto out;
> + if (INTEL_GEN(dev_priv) >= 12) {
> + dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> + dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> + } else {
> + dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
> + SKL_CSR_DC3_DC5_COUNT;
> + if (!IS_GEN9_LP(dev_priv))
> + dc6_reg = SKL_CSR_DC5_DC6_COUNT;
> + }
>
> - seq_printf(m, "DC3 -> DC5 count: %d\n",
> - I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
> - SKL_CSR_DC3_DC5_COUNT));
> - if (!IS_GEN9_LP(dev_priv))
> - seq_printf(m, "DC5 -> DC6 count: %d\n",
> - I915_READ(SKL_CSR_DC5_DC6_COUNT));
> + seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(dc5_reg));
> + if (dc6_reg.reg)
> + seq_printf(m, "DC5 -> DC6 count: %d\n", I915_READ(dc6_reg));
>
> out:
> seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 24f2a52a2b42..e999ce94b45c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7268,6 +7268,8 @@ enum {
> #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
> #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
> #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
> +#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
> +#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
>
> /* interrupts */
> #define DE_MASTER_IRQ_CONTROL (1 << 31)
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/3] drm/i915/tgl: allow the reg_read ioctl to read the RCS TIMESTAMP register
2019-07-26 0:24 ` [PATCH 2/3] drm/i915/tgl: allow the reg_read ioctl to read the RCS TIMESTAMP register Lucas De Marchi
@ 2019-07-26 19:05 ` Rodrigo Vivi
0 siblings, 0 replies; 8+ messages in thread
From: Rodrigo Vivi @ 2019-07-26 19:05 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Thu, Jul 25, 2019 at 05:24:11PM -0700, Lucas De Marchi wrote:
> From: Jordan Justen <jordan.l.justen@intel.com>
>
> This enables the Mesa driver to advertise support for ARB_timer_query,
> and thus an OpenGL version higher than 3.2.
>
> Based on the ICL patch by Paulo Zanoni and CNL patch by Nanley Chery.
>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 475ab3d4d91d..2b839acfa0f6 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1776,7 +1776,7 @@ static const struct reg_whitelist {
> } reg_read_whitelist[] = { {
> .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
> .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
> - .gen_mask = INTEL_GEN_MASK(4, 11),
> + .gen_mask = INTEL_GEN_MASK(4, 12),
> .size = 8
> } };
>
> --
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* ✓ Fi.CI.IGT: success for Tiger Lake: register moves
2019-07-26 0:24 [PATCH 0/3] Tiger Lake: register moves Lucas De Marchi
` (3 preceding siblings ...)
2019-07-26 3:37 ` ✓ Fi.CI.BAT: success for Tiger Lake: register moves Patchwork
@ 2019-07-27 7:47 ` Patchwork
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2019-07-27 7:47 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Tiger Lake: register moves
URL : https://patchwork.freedesktop.org/series/64277/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6557_full -> Patchwork_13767_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_13767_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@system-suspend-modeset:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#108840])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb1/igt@i915_pm_rpm@system-suspend-modeset.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/shard-iclb2/igt@i915_pm_rpm@system-suspend-modeset.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled:
- shard-skl: [PASS][5] -> [FAIL][6] ([fdo#103184] / [fdo#103232]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-skl9/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/shard-skl4/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-glk: [PASS][7] -> [FAIL][8] ([fdo#105363])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/shard-glk4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend:
- shard-hsw: [PASS][9] -> [INCOMPLETE][10] ([fdo#103540])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-hsw6/igt@kms_flip@flip-vs-suspend.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/shard-hsw5/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
- shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +3 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109642] / [fdo#111068])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb2/igt@kms_psr2_su@page_flip.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/shard-iclb8/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([fdo#108566]) +5 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@perf@oa-exponents:
- shard-glk: [PASS][19] -> [FAIL][20] ([fdo#105483])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-glk8/igt@perf@oa-exponents.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/shard-glk8/igt@perf@oa-exponents.html
#### Possible fixes ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: [DMESG-WARN][21] ([fdo#108566]) -> [PASS][22] +2 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-apl6/igt@gem_ctx_isolation@rcs0-s3.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/shard-apl5/igt@gem_ctx_isolation@rcs0-s3.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][23] ([fdo#108566]) -> [PASS][24] +3 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-skl: [INCOMPLETE][25] ([fdo#110741]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-skl5/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/shard-skl5/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: [FAIL][27] ([fdo#105363]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [FAIL][29] ([fdo#105363]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend:
- shard-skl: [INCOMPLETE][31] ([fdo#109507]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-skl3/igt@kms_flip@flip-vs-suspend.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/shard-skl6/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@modeset-vs-vblank-race:
- shard-glk: [FAIL][33] ([fdo#103060]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-glk9/igt@kms_flip@modeset-vs-vblank-race.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/shard-glk5/igt@kms_flip@modeset-vs-vblank-race.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [FAIL][35] ([fdo#103167]) -> [PASS][36] +7 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-skl: [INCOMPLETE][37] ([fdo#104108]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-skl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/shard-skl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [SKIP][39] ([fdo#109441]) -> [PASS][40] +2 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb6/igt@kms_psr@psr2_primary_page_flip.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
* igt@perf_pmu@busy-hang-bcs0:
- shard-iclb: [FAIL][41] -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb1/igt@perf_pmu@busy-hang-bcs0.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/shard-iclb3/igt@perf_pmu@busy-hang-bcs0.html
* igt@perf_pmu@rc6-runtime-pm-long:
- shard-iclb: [FAIL][43] ([fdo#105010]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb6/igt@perf_pmu@rc6-runtime-pm-long.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/shard-iclb8/igt@perf_pmu@rc6-runtime-pm-long.html
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105010]: https://bugs.freedesktop.org/show_bug.cgi?id=105010
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105483]: https://bugs.freedesktop.org/show_bug.cgi?id=105483
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110741]: https://bugs.freedesktop.org/show_bug.cgi?id=110741
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6557 -> Patchwork_13767
CI-20190529: 20190529
CI_DRM_6557: 2ebd69f583d23b295265832f168e39427a8bd863 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5112: 7e4d10507088055413769a020dd674f52b4bc1b0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13767: 2270b496234228cc38d706349c12b803f0f0289d @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-07-27 7:47 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-07-26 0:24 [PATCH 0/3] Tiger Lake: register moves Lucas De Marchi
2019-07-26 0:24 ` [PATCH 1/3] drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers Lucas De Marchi
2019-07-26 4:04 ` Gupta, Anshuman
2019-07-26 0:24 ` [PATCH 2/3] drm/i915/tgl: allow the reg_read ioctl to read the RCS TIMESTAMP register Lucas De Marchi
2019-07-26 19:05 ` Rodrigo Vivi
2019-07-26 0:24 ` [PATCH 3/3] drm/i915/tgl: add support for reading the timestamp frequency Lucas De Marchi
2019-07-26 3:37 ` ✓ Fi.CI.BAT: success for Tiger Lake: register moves Patchwork
2019-07-27 7:47 ` ✓ Fi.CI.IGT: " Patchwork
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