From: Andrew Lunn <andrew@lunn.ch>
To: Claudiu Manoil <claudiu.manoil@nxp.com>
Cc: devicetree@vger.kernel.org, netdev@vger.kernel.org,
alexandru.marginean@nxp.com, linux-kernel@vger.kernel.org,
Li Yang <leoyang.li@nxp.com>, Rob Herring <robh+dt@kernel.org>,
"David S . Miller" <davem@davemloft.net>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH net-next v3 4/4] arm64: dts: fsl: ls1028a: Enable eth port1 on the ls1028a QDS board
Date: Mon, 29 Jul 2019 17:37:45 +0200 [thread overview]
Message-ID: <20190729153745.GI4110@lunn.ch> (raw)
In-Reply-To: <1564394627-3810-5-git-send-email-claudiu.manoil@nxp.com>
On Mon, Jul 29, 2019 at 01:03:47PM +0300, Claudiu Manoil wrote:
> LS1028a has one Ethernet management interface. On the QDS board, the
> MDIO signals are multiplexed to either on-board AR8035 PHY device or
> to 4 PCIe slots allowing for SGMII cards.
> To enable the Ethernet ENETC Port 1, which can only be connected to a
> RGMII PHY, the multiplexer needs to be configured to route the MDIO to
> the AR8035 PHY. The MDIO/MDC routing is controlled by bits 7:4 of FPGA
> board config register 0x54, and value 0 selects the on-board RGMII PHY.
> The FPGA board config registers are accessible on the i2c bus, at address
> 0x66.
>
> The PF3 MDIO PCIe integrated endpoint device allows for centralized access
> to the MDIO bus. Add the corresponding devicetree node and set it to be
> the MDIO bus parent.
>
> Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
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WARNING: multiple messages have this Message-ID (diff)
From: Andrew Lunn <andrew@lunn.ch>
To: Claudiu Manoil <claudiu.manoil@nxp.com>
Cc: devicetree@vger.kernel.org, netdev@vger.kernel.org,
alexandru.marginean@nxp.com, linux-kernel@vger.kernel.org,
Li Yang <leoyang.li@nxp.com>, Rob Herring <robh+dt@kernel.org>,
"David S . Miller" <davem@davemloft.net>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH net-next v3 4/4] arm64: dts: fsl: ls1028a: Enable eth port1 on the ls1028a QDS board
Date: Mon, 29 Jul 2019 17:37:45 +0200 [thread overview]
Message-ID: <20190729153745.GI4110@lunn.ch> (raw)
In-Reply-To: <1564394627-3810-5-git-send-email-claudiu.manoil@nxp.com>
On Mon, Jul 29, 2019 at 01:03:47PM +0300, Claudiu Manoil wrote:
> LS1028a has one Ethernet management interface. On the QDS board, the
> MDIO signals are multiplexed to either on-board AR8035 PHY device or
> to 4 PCIe slots allowing for SGMII cards.
> To enable the Ethernet ENETC Port 1, which can only be connected to a
> RGMII PHY, the multiplexer needs to be configured to route the MDIO to
> the AR8035 PHY. The MDIO/MDC routing is controlled by bits 7:4 of FPGA
> board config register 0x54, and value 0 selects the on-board RGMII PHY.
> The FPGA board config registers are accessible on the i2c bus, at address
> 0x66.
>
> The PF3 MDIO PCIe integrated endpoint device allows for centralized access
> to the MDIO bus. Add the corresponding devicetree node and set it to be
> the MDIO bus parent.
>
> Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Lunn <andrew@lunn.ch>
To: Claudiu Manoil <claudiu.manoil@nxp.com>
Cc: "David S . Miller" <davem@davemloft.net>,
Rob Herring <robh+dt@kernel.org>, Li Yang <leoyang.li@nxp.com>,
alexandru.marginean@nxp.com, netdev@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH net-next v3 4/4] arm64: dts: fsl: ls1028a: Enable eth port1 on the ls1028a QDS board
Date: Mon, 29 Jul 2019 17:37:45 +0200 [thread overview]
Message-ID: <20190729153745.GI4110@lunn.ch> (raw)
In-Reply-To: <1564394627-3810-5-git-send-email-claudiu.manoil@nxp.com>
On Mon, Jul 29, 2019 at 01:03:47PM +0300, Claudiu Manoil wrote:
> LS1028a has one Ethernet management interface. On the QDS board, the
> MDIO signals are multiplexed to either on-board AR8035 PHY device or
> to 4 PCIe slots allowing for SGMII cards.
> To enable the Ethernet ENETC Port 1, which can only be connected to a
> RGMII PHY, the multiplexer needs to be configured to route the MDIO to
> the AR8035 PHY. The MDIO/MDC routing is controlled by bits 7:4 of FPGA
> board config register 0x54, and value 0 selects the on-board RGMII PHY.
> The FPGA board config registers are accessible on the i2c bus, at address
> 0x66.
>
> The PF3 MDIO PCIe integrated endpoint device allows for centralized access
> to the MDIO bus. Add the corresponding devicetree node and set it to be
> the MDIO bus parent.
>
> Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
next prev parent reply other threads:[~2019-07-29 15:37 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-29 10:03 [PATCH net-next v3 0/4] enetc: Add mdio bus driver for the PCIe MDIO endpoint Claudiu Manoil
2019-07-29 10:03 ` Claudiu Manoil
2019-07-29 10:03 ` [PATCH net-next v3 1/4] enetc: Clean up local mdio bus allocation Claudiu Manoil
2019-07-29 10:03 ` Claudiu Manoil
2019-07-29 15:32 ` Andrew Lunn
2019-07-29 15:32 ` Andrew Lunn
2019-07-29 15:32 ` Andrew Lunn
2019-07-29 10:03 ` [PATCH net-next v3 2/4] enetc: Add mdio bus driver for the PCIe MDIO endpoint Claudiu Manoil
2019-07-29 10:03 ` Claudiu Manoil
2019-07-29 15:35 ` Andrew Lunn
2019-07-29 15:35 ` Andrew Lunn
2019-07-29 15:35 ` Andrew Lunn
2019-07-29 15:39 ` Claudiu Manoil
2019-07-29 15:39 ` Claudiu Manoil
2019-07-29 15:46 ` Claudiu Manoil
2019-07-29 15:46 ` Claudiu Manoil
2019-07-29 10:03 ` [PATCH net-next v3 3/4] dt-bindings: net: fsl: enetc: Add bindings for the central MDIO PCIe endpoint Claudiu Manoil
2019-07-29 10:03 ` Claudiu Manoil
2019-07-29 15:36 ` Andrew Lunn
2019-07-29 15:36 ` Andrew Lunn
2019-07-29 15:36 ` Andrew Lunn
2019-07-29 10:03 ` [PATCH net-next v3 4/4] arm64: dts: fsl: ls1028a: Enable eth port1 on the ls1028a QDS board Claudiu Manoil
2019-07-29 10:03 ` Claudiu Manoil
2019-07-29 15:37 ` Andrew Lunn [this message]
2019-07-29 15:37 ` Andrew Lunn
2019-07-29 15:37 ` Andrew Lunn
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