[PATCH 0/2] [Backport for 4.9.y stable] arm64 CTR

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* [PATCH 0/2] [Backport for 4.9.y stable] arm64 CTR_EL0 cpufeature fixes
@ 2019-08-05 17:13 Will Deacon
  2019-08-05 17:13 ` [PATCH 1/2] arm64: cpufeature: Fix CTR_EL0 field definitions Will Deacon
                   ` (2 more replies)
  0 siblings, 3 replies; 5+ messages in thread
From: Will Deacon @ 2019-08-05 17:13 UTC (permalink / raw)
  To: gregkh; +Cc: stable, Will Deacon

Hi,

These two patches are backports for 4.9.y stable kernels after one of
them failed to apply:

  https://lkml.kernel.org/r/156498316660175@kroah.com

Cheers,

Will

--->8

Will Deacon (2):
  arm64: cpufeature: Fix CTR_EL0 field definitions
  arm64: cpufeature: Fix feature comparison for CTR_EL0.{CWG,ERG}

 arch/arm64/include/asm/cpufeature.h |  7 ++++---
 arch/arm64/kernel/cpufeature.c      | 14 ++++++++++----
 2 files changed, 14 insertions(+), 7 deletions(-)

-- 
2.11.0


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 1/2] arm64: cpufeature: Fix CTR_EL0 field definitions
  2019-08-05 17:13 [PATCH 0/2] [Backport for 4.9.y stable] arm64 CTR_EL0 cpufeature fixes Will Deacon
@ 2019-08-05 17:13 ` Will Deacon
  2019-08-05 17:13 ` [PATCH 2/2] arm64: cpufeature: Fix feature comparison for CTR_EL0.{CWG,ERG} Will Deacon
  2019-08-06 21:27 ` [PATCH 0/2] [Backport for 4.9.y stable] arm64 CTR_EL0 cpufeature fixes Sasha Levin
  2 siblings, 0 replies; 5+ messages in thread
From: Will Deacon @ 2019-08-05 17:13 UTC (permalink / raw)
  To: gregkh; +Cc: stable, Will Deacon, Shanker Donthineni, Will Deacon

From: Will Deacon <will.deacon@arm.com>

commit be68a8aaf925aaf35574260bf820bb09d2f9e07f upstream.

Our field definitions for CTR_EL0 suffer from a number of problems:

  - The IDC and DIC fields are missing, which causes us to enable CTR
    trapping on CPUs with either of these returning non-zero values.

  - The ERG is FTR_LOWER_SAFE, whereas it should be treated like CWG as
    FTR_HIGHER_SAFE so that applications can use it to avoid false sharing.

  - [nit] A RES1 field is described as "RAO"

This patch updates the CTR_EL0 field definitions to fix these issues.

Cc: <stable@vger.kernel.org> # 4.9.y only
Cc: Shanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
---
 arch/arm64/kernel/cpufeature.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index a3ab7dfad50a..e2ac72b7e89c 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -148,10 +148,12 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 };
 
 static const struct arm64_ftr_bits ftr_ctr[] = {
-	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1),	/* RAO */
-	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
+	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1),	/* RES1 */
+	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 30, 1, 0),
+	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 29, 1, 1),	/* DIC */
+	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 1, 1),	/* IDC */
 	ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0),	/* CWG */
-	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),	/* ERG */
+	ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 20, 4, 0),	/* ERG */
 	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
 	/*
 	 * Linux can handle differing I-cache policies. Userspace JITs will
-- 
2.11.0


^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [PATCH 2/2] arm64: cpufeature: Fix feature comparison for CTR_EL0.{CWG,ERG}
  2019-08-05 17:13 [PATCH 0/2] [Backport for 4.9.y stable] arm64 CTR_EL0 cpufeature fixes Will Deacon
  2019-08-05 17:13 ` [PATCH 1/2] arm64: cpufeature: Fix CTR_EL0 field definitions Will Deacon
@ 2019-08-05 17:13 ` Will Deacon
  2019-08-06 21:27 ` [PATCH 0/2] [Backport for 4.9.y stable] arm64 CTR_EL0 cpufeature fixes Sasha Levin
  2 siblings, 0 replies; 5+ messages in thread
From: Will Deacon @ 2019-08-05 17:13 UTC (permalink / raw)
  To: gregkh; +Cc: stable, Will Deacon, Catalin Marinas

commit 147b9635e6347104b91f48ca9dca61eb0fbf2a54 upstream.

If CTR_EL0.{CWG,ERG} are 0b0000 then they must be interpreted to have
their architecturally maximum values, which defeats the use of
FTR_HIGHER_SAFE when sanitising CPU ID registers on heterogeneous
machines.

Introduce FTR_HIGHER_OR_ZERO_SAFE so that these fields effectively
saturate at zero.

Fixes: 3c739b571084 ("arm64: Keep track of CPU feature registers")
Cc: <stable@vger.kernel.org> # 4.9.y only
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/include/asm/cpufeature.h | 7 ++++---
 arch/arm64/kernel/cpufeature.c      | 8 ++++++--
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 15868eca58de..e7bef3d936d8 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -31,9 +31,10 @@
 
 /* CPU feature register tracking */
 enum ftr_type {
-	FTR_EXACT,	/* Use a predefined safe value */
-	FTR_LOWER_SAFE,	/* Smaller value is safe */
-	FTR_HIGHER_SAFE,/* Bigger value is safe */
+	FTR_EXACT,			/* Use a predefined safe value */
+	FTR_LOWER_SAFE,			/* Smaller value is safe */
+	FTR_HIGHER_SAFE,		/* Bigger value is safe */
+	FTR_HIGHER_OR_ZERO_SAFE,	/* Bigger value is safe, but 0 is biggest */
 };
 
 #define FTR_STRICT	true	/* SANITY check strict matching required */
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index e2ac72b7e89c..9a8e45dc36bd 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -152,8 +152,8 @@ static const struct arm64_ftr_bits ftr_ctr[] = {
 	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 30, 1, 0),
 	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 29, 1, 1),	/* DIC */
 	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 1, 1),	/* IDC */
-	ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0),	/* CWG */
-	ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 20, 4, 0),	/* ERG */
+	ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 24, 4, 0),	/* CWG */
+	ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 20, 4, 0),	/* ERG */
 	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
 	/*
 	 * Linux can handle differing I-cache policies. Userspace JITs will
@@ -392,6 +392,10 @@ static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
 	case FTR_LOWER_SAFE:
 		ret = new < cur ? new : cur;
 		break;
+	case FTR_HIGHER_OR_ZERO_SAFE:
+		if (!cur || !new)
+			break;
+		/* Fallthrough */
 	case FTR_HIGHER_SAFE:
 		ret = new > cur ? new : cur;
 		break;
-- 
2.11.0


^ permalink raw reply related	[flat|nested] 5+ messages in thread

* Re: [PATCH 0/2] [Backport for 4.9.y stable] arm64 CTR_EL0 cpufeature fixes
  2019-08-05 17:13 [PATCH 0/2] [Backport for 4.9.y stable] arm64 CTR_EL0 cpufeature fixes Will Deacon
  2019-08-05 17:13 ` [PATCH 1/2] arm64: cpufeature: Fix CTR_EL0 field definitions Will Deacon
  2019-08-05 17:13 ` [PATCH 2/2] arm64: cpufeature: Fix feature comparison for CTR_EL0.{CWG,ERG} Will Deacon
@ 2019-08-06 21:27 ` Sasha Levin
  2 siblings, 0 replies; 5+ messages in thread
From: Sasha Levin @ 2019-08-06 21:27 UTC (permalink / raw)
  To: Will Deacon; +Cc: gregkh, stable

On Mon, Aug 05, 2019 at 06:13:53PM +0100, Will Deacon wrote:
>Hi,
>
>These two patches are backports for 4.9.y stable kernels after one of
>them failed to apply:
>
>  https://lkml.kernel.org/r/156498316660175@kroah.com

I took the 4.9 patches, thanks!

--
Thanks,
Sasha

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 0/2] [Backport for 4.4.y stable] arm64 CTR_EL0 cpufeature fixes
@ 2019-08-05 17:13 Will Deacon
  2019-08-05 17:13 ` [PATCH 1/2] arm64: cpufeature: Fix CTR_EL0 field definitions Will Deacon
  0 siblings, 1 reply; 5+ messages in thread
From: Will Deacon @ 2019-08-05 17:13 UTC (permalink / raw)
  To: gregkh; +Cc: stable, Will Deacon

Hi,

These two patches are backports for 4.4.y stable kernels after one of
them failed to apply:

  https://lkml.kernel.org/r/156498316752100@kroah.com

Cheers,

Will

--->8

Will Deacon (2):
  arm64: cpufeature: Fix CTR_EL0 field definitions
  arm64: cpufeature: Fix feature comparison for CTR_EL0.{CWG,ERG}

 arch/arm64/include/asm/cpufeature.h |  7 ++++---
 arch/arm64/kernel/cpufeature.c      | 14 ++++++++++----
 2 files changed, 14 insertions(+), 7 deletions(-)

-- 
2.11.0


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 1/2] arm64: cpufeature: Fix CTR_EL0 field definitions
  2019-08-05 17:13 [PATCH 0/2] [Backport for 4.4.y " Will Deacon
@ 2019-08-05 17:13 ` Will Deacon
  0 siblings, 0 replies; 5+ messages in thread
From: Will Deacon @ 2019-08-05 17:13 UTC (permalink / raw)
  To: gregkh; +Cc: stable, Will Deacon, Shanker Donthineni, Will Deacon

From: Will Deacon <will.deacon@arm.com>

commit be68a8aaf925aaf35574260bf820bb09d2f9e07f upstream.

Our field definitions for CTR_EL0 suffer from a number of problems:

  - The IDC and DIC fields are missing, which causes us to enable CTR
    trapping on CPUs with either of these returning non-zero values.

  - The ERG is FTR_LOWER_SAFE, whereas it should be treated like CWG as
    FTR_HIGHER_SAFE so that applications can use it to avoid false sharing.

  - [nit] A RES1 field is described as "RAO"

This patch updates the CTR_EL0 field definitions to fix these issues.

Cc: <stable@vger.kernel.org> # 4.4.y only
Cc: Shanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
---
 arch/arm64/kernel/cpufeature.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index c1eddc07d996..fff0bf2f889e 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -126,10 +126,12 @@ static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 };
 
 static struct arm64_ftr_bits ftr_ctr[] = {
-	U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1),	/* RAO */
-	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
+	U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1),	/* RES1 */
+	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 30, 1, 0),
+	U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 29, 1, 1),	/* DIC */
+	U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 1, 1),	/* IDC */
 	U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0),	/* CWG */
-	U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),	/* ERG */
+	U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 20, 4, 0),	/* ERG */
 	U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1),	/* DminLine */
 	/*
 	 * Linux can handle differing I-cache policies. Userspace JITs will
-- 
2.11.0


^ permalink raw reply related	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2019-08-06 21:27 UTC | newest]

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2019-08-05 17:13 [PATCH 0/2] [Backport for 4.9.y stable] arm64 CTR_EL0 cpufeature fixes Will Deacon
2019-08-05 17:13 ` [PATCH 1/2] arm64: cpufeature: Fix CTR_EL0 field definitions Will Deacon
2019-08-05 17:13 ` [PATCH 2/2] arm64: cpufeature: Fix feature comparison for CTR_EL0.{CWG,ERG} Will Deacon
2019-08-06 21:27 ` [PATCH 0/2] [Backport for 4.9.y stable] arm64 CTR_EL0 cpufeature fixes Sasha Levin
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